WO2014000361A1 - 一种阵列基板过孔的制作方法及阵列基板制作工艺 - Google Patents

一种阵列基板过孔的制作方法及阵列基板制作工艺 Download PDF

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Publication number
WO2014000361A1
WO2014000361A1 PCT/CN2012/084244 CN2012084244W WO2014000361A1 WO 2014000361 A1 WO2014000361 A1 WO 2014000361A1 CN 2012084244 W CN2012084244 W CN 2012084244W WO 2014000361 A1 WO2014000361 A1 WO 2014000361A1
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Prior art keywords
etching
metal layer
via holes
shallow
photoresist
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PCT/CN2012/084244
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English (en)
French (fr)
Inventor
封宾
白金超
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Publication of WO2014000361A1 publication Critical patent/WO2014000361A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present disclosure relates to the field of array substrate processing technology, and in particular, to a method for fabricating via holes of an array substrate and a process for fabricating the array substrate. Background technique
  • the via process is an important process in the fabrication of array substrates for liquid crystal display panels.
  • the metal strips at different levels or the different metal portions at the same level are usually exposed by a via process, and then the exposed portions of the metals at different levels are connected by a subsequent process, or Connected to different metal parts located at the same level, such as the connection between the gate line and the data line of the array substrate, the connection between the data line and the pixel electrode, and the formation of a matrix structure of the common electrode line.
  • the quality of the via process directly affects the yield of the product and the associated performance of the final panel.
  • the metals at different levels are different in depth from the upper surface of the product to be etched, that is, the etching depth is different. In some cases, even the different metal portions of the same layer have different depths relative to the upper surface of the product to be etched, i.e., the etch depth is different.
  • the etching depth in the array substrate is two: a metal layer far away from the etching surface of the array substrate is called a deep-region metal layer, and a via hole corresponding to the deep-region metal layer is called a deep
  • the hole, the area where the deep hole is opened is called the deep hole area; the metal layer which is closer to the etching surface of the array substrate is called the shallow area metal layer, and the corresponding hole of the shallow area metal layer is called the shallow hole, and the shallow hole is opened.
  • the area is called the shallow hole area.
  • both the deep hole in the deep hole region and the shallow hole in the shallow hole region are uniformly formed by one mask etching, which is easy to cause the shallow layer metal layer to be engraved. Excessive eclipse.
  • FIG. 1 shows that the shallow hole in the shallow hole region of the data line metal layer in the conventional via process has been etched to Schematic diagram of the structure of the data line metal layer
  • FIG. 2 is a structural schematic view of the deep hole of the deep hole region where the gate line metal layer is etched to the gate line metal layer in the conventional via process.
  • the array substrate shown in FIG. 1 includes a substrate 01, a gate line metal layer 06 deposited on the substrate 01 and etched, and a gate deposited on the gate line metal layer 06 and the substrate 01. a pole insulating layer 02, which is sequentially deposited on the gate insulating layer 02 and the active layer 03 and the data line metal layer 04, And an insulating layer 05 covering the above layers.
  • the gate insulating layer 02 and the insulating layer 05 are provided on the gate line metal layer 06, and the etching depth is deep when forming the via hole from the upper surface of the array substrate, and belongs to the deep hole region;
  • the data line metal layer 04 has only the insulating layer 05.
  • the etching depth is shallow and belongs to the shallow hole region.
  • the deep hole 061 connected to the gate line metal layer 06 needs to etch the gate insulating layer 02 and the data insulating layer 05, and the shallow hole 041 connected to the data line metal layer 04 only needs to etch the insulating layer 05, so when the shallow hole After the 041 etching is completed, the surface metal of the data line metal layer 04 is exposed, and the deep hole 061 is etched only to the gate insulating layer 02, and the gate insulating layer 02 of the etching depth dl is also required to be etched.
  • the exposed metal will continue to etch.
  • the etchant will have a depth d2 through the shallow hole 041 to the already exposed metal in the data line metal layer 04.
  • the over-etching causes a poor alignment of the data line metal layer 04.
  • the present disclosure provides a method for fabricating via holes of an array substrate and a process for fabricating the array substrate, so as to improve the over-cut defects generated in the via holes having a shallow via hole depth in the prior art via-hole process, thereby improving the yield of the product.
  • an embodiment of the present disclosure provides a method for fabricating a via of an array substrate, including: a pre-etching step corresponding to at least one of a plurality of regions in which a via is required to be generated, respectively The hierarchical structure above the metal layer is partially etched such that the etch depth margin to the corresponding metal layer is the same in the plurality of regions where the via holes are to be formed; and the etching step is performed on the plurality of regions where the via holes are required to be formed Simultaneous etching until each via reaches its metal layer.
  • the etch depth of the via holes generated in the plurality of regions where the via holes are required to be formed is two, wherein the deep etch holes are called deep holes, and the etch depth is shallow.
  • the hole is called a shallow hole; in the pre-etching step, the deep hole region where the deep hole is located is partially etched, so that the etching depth margin of the deep hole region and the shallow hole region where the shallow hole is located are etched. The depth is the same.
  • the method further includes the following steps prior to the pre-etching step: coating Photoresist; exposure and development, full exposure of the photoresist in the deep hole region, half exposure of the photoresist in the shallow hole region, thereby retaining a portion of the photoresist in the shallow hole region; the etching step and The pre-etching step further includes the steps of: ashing, ashing to remove a portion of the photoresist remaining in the shallow hole region; the etching step further comprising the steps of: stripping, the remaining portion of the photoresist Remove.
  • the exposing step exposure is performed using a half mask having an all-transmissive region and a semi-transmissive region, wherein the semi-transmissive region of the semi-transmissive mask corresponds to the deep-hole region, The semi-transmissive region corresponds to the shallow hole region.
  • an embodiment of the present disclosure provides an array substrate fabrication process including the steps of: forming a gate line metal layer on a substrate; forming a gate insulating layer on the gate line metal layer; An active layer and a data line metal layer are sequentially formed on the gate insulating layer; an insulating layer is formed on the data line metal layer and the gate insulating layer; and pre-etching is performed on a plurality of regions that need to generate via holes respectively
  • the layer structure above the metal layer corresponding to at least one of the regions is partially etched such that the etch depth margin to the corresponding metal layer is the same in the plurality of regions where the via holes are to be formed; etching, A plurality of regions where via holes are to be formed are simultaneously etched until each via reaches the corresponding metal layer; an electrode layer is deposited to fill the via holes to achieve connection between the metal layers.
  • the metal layer in the deep hole region is a gate line metal layer
  • the metal layer in the shallow hole region is a data line metal layer
  • the electrode layer connects the gate line metal layer and the data line metal Floor.
  • a photoresist in the step of coating a photoresist, a photoresist is coated on the insulating layer; in the exposing and developing steps, photolithography of a deep hole region where a gate line metal layer is located The glue is completely exposed, and the photoresist in the shallow hole region where the data line metal layer is located is half-exposed, and a part of the photoresist in the shallow hole region is retained after development; in the pre-etching step, the depth of the full exposure is deep The hole region is partially etched, and a predetermined etch depth margin is left over the gate line metal layer, the predetermined etch depth margin and the etch depth of the shallow hole region where the data line metal layer is located In the ashing step, ashing removes a portion of the photoresist remaining in the shallow hole region; in the etching step, etching the shallow hole region and the deep hole region until the deep hole of the deep hole region reaches The gate line metal layer, at the same time, the shallow hole of the shallow hole region
  • stepwise etching is performed on each of the regions where the via holes are required to be formed according to the etching depth of the etching to the corresponding metal layer.
  • a region having a deep etching depth etched into a corresponding metal layer in a region where a via hole is to be formed by a pre-etching step The region is partially etched such that the etch depth margins etched into the corresponding metal layers in the plurality of regions where the vias are to be formed are the same.
  • the same meaning here is only the same theoretical meaning.
  • the etch depth margin of each region may have The difference is that the difference between the etching depths of the respective metal layers when the regions in which the plurality of via holes are required to be formed in the etching step can be reduced. Then, through the etching step, all the regions that need to generate via holes are synchronously etched, so that each via hole reaches the metal layer at the same time; by this method, the etching depth in the via region is required to be different in the etching depth.
  • the deep via region is etched away to ensure that the etching margin between the vias is nearly the same during the etching step, so that each via reaches its corresponding metal layer at the same time, and the etching depth is reduced. Over-engraving phenomenon at the via.
  • the method for fabricating the via hole of the array substrate provided by the present disclosure can improve the over-cutting phenomenon at the via hole with a shallow etching depth in the via process, and improve the product yield.
  • FIG. 1 is a schematic view showing the structure of a shallow hole in a shallow hole region where a data line metal layer is etched to a data line metal layer in a via process in the prior art;
  • FIG. 2 is a schematic structural view of a deep hole etched to a gate line metal layer of the deep hole region of a gate line metal layer in a via process in the prior art
  • FIG. 3 is a flowchart of a method for fabricating a via hole of an array substrate according to Embodiment 1 of the present disclosure
  • FIG. 4 is a flowchart of a method for fabricating a via hole of an array substrate according to Embodiment 2 of the present disclosure
  • FIG. 6 is a flow chart of a process for fabricating an array substrate according to Embodiment 4 of the present disclosure
  • FIG. 7 is a schematic structural view of an array substrate after a step of coating a photoresist in an array substrate manufacturing process according to Embodiment 4 of the present disclosure
  • 8 is a schematic structural view of an array substrate after exposure of a step in an array substrate manufacturing process according to Embodiment 4 of the present disclosure
  • FIG. 9 is a schematic structural view of an array substrate after pre-etching in a process of fabricating an array substrate according to Embodiment 4 of the present disclosure.
  • FIG. 10 is a schematic structural view of an array substrate after ashing in an array substrate manufacturing process according to Embodiment 4 of the present disclosure
  • FIG. 11 is a schematic structural view of an array substrate after step etching in an array substrate fabrication process according to Embodiment 4 of the present disclosure
  • FIG. 12 is a schematic structural view of an array substrate after stripping steps in an array substrate fabrication process according to Embodiment 4 of the present disclosure
  • FIG. 13 is a schematic structural view of an array substrate after a step of depositing an etched electrode layer in a process of fabricating an array substrate according to Embodiment 4 of the present disclosure. detailed description
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the embodiment provides a method for fabricating a via hole of an array substrate, and the method includes:
  • Step 101 pre-etching, partially etching a hierarchical structure above the metal layer corresponding to at least one of the plurality of regions in which the via holes are to be formed, so as to etch in a plurality of regions where the via holes are required to be formed
  • the etching depth of the corresponding metal layer is the same;
  • Step 102 Etching, synchronously etching a plurality of regions where via holes are to be formed until each via reaches a corresponding metal layer.
  • stepwise etching is performed on each of the regions where the via holes are required to be formed according to the etching depth of the etching to the corresponding metal layer.
  • the etching depth to the corresponding metal layer in the region where the via hole is to be formed is deep by the step 101 pre-etching.
  • the area is partially etched such that the etch depth margins etched into the corresponding metal layers in the plurality of regions where the vias are to be formed are the same.
  • the same meaning here is only the same meaning in theory.
  • the etch depth margin of each region may have The difference is that the difference between the etching depths of the metal layers in the etching of the regions in which the plurality of via holes are required to be formed in the etching in step 102 can be reduced. Then, after etching in step 102, all the regions that need to generate via holes are synchronously etched, so that each via hole reaches the metal layer at the same time; by this method, the etching depth in the via region is required to be different in etching depth first.
  • a deeper via region is etched away to ensure that the etching margin between the vias is nearly the same in the etching in step 102, so that each via reaches its corresponding metal layer at the same time, and the etching depth is lowered. Overcutting at shallow vias.
  • the method for fabricating the via hole of the array substrate provided by the present disclosure can improve the over-cutting phenomenon at the via hole with a shallow etching depth in the via process, and improve the product yield.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the etch depth of the via holes in the region of the array substrate where a plurality of via holes are required to be formed is two, wherein the deep etching depth is called deep hole, and the shallow etching depth is called shallow hole.
  • the area where the deep hole is located is called the deep hole area
  • the area where the shallow hole is located is called the shallow hole area.
  • Step 201 coating a photoresist
  • Step 202 exposing and developing, completely exposing the photoresist in the deep hole region, and semi-exposing the photoresist in the shallow hole region, thereby retaining a portion of the photoresist in the shallow hole region after development;
  • Step 203 pre-etching, partially etching the deep hole region, and leaving a predetermined etching depth margin above the metal layer in the deep hole region, the predetermined etching depth margin and the shallow hole region engraving
  • the etch depth is the same:
  • Step 204 ashing and ashing to remove a portion of the photoresist in the shallow hole region
  • Step 205 etching, synchronously etching the shallow hole region and the deep hole region until the deep hole of the deep hole region reaches the corresponding metal layer, and at the same time, the shallow hole of the shallow hole region reaches the corresponding metal layer; The excess photoresist is peeled off.
  • the etching portion of the deep hole region is exposed by exposure in step 202, and the etching portion of the shallow hole region is protected by the photoresist remaining after the half exposure. Therefore, the effect of etching only the deep hole region during etching is achieved; after the pre-etching is completed in step 203, the photoresist is removed by the step 204, and the remaining photoresist in the shallow hole region is removed by ashing to remove the shallow hole region.
  • the etched portion of the region is exposed, and then etching is performed in step 205 to simultaneously etch the deep hole region and the shallow hole region. After the etching in step 205 is completed, the remaining photoresist is removed by stripping in step 206, so that Affect the subsequent process.
  • the semi-transmissive mask having the full transparent region and the semi-transmissive region is used for exposure, wherein the semi-transmissive region of the semi-transmissive mask corresponds to the deep-hole region, and the semi-transparent The area corresponds to the shallow hole area.
  • the stepwise etching of the deep hole region and the shallow hole region can be realized by applying a primary photoresist by a half exposure technique using a semi-transparent mask, which simplifies the process.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the present disclosure also provides an array substrate fabrication process using the method described in Embodiment 1.
  • the process includes:
  • Step 301 forming a gate line metal layer on the substrate
  • Step 302 forming a gate insulating layer on the gate line metal layer
  • Step 303 sequentially forming an active layer and a data line metal layer on the gate insulating layer
  • Step 304 forming an insulating layer over the data line metal layer and the gate insulating layer.
  • the etch depth of the via holes in the region of the array substrate where a plurality of via holes are required to be formed is two, wherein the deep etching depth is called deep hole, and the shallow etching depth is called shallow hole.
  • the area where the deep hole is located is called the deep hole area
  • the area where the shallow hole is located is called the shallow hole area.
  • Step 305 Pre-etching, respectively, partially etching a hierarchical structure above the metal layer corresponding to at least one of the plurality of regions in which the via holes are to be generated, so that a plurality of regions of the via holes need to be generated to the corresponding metal
  • the etching depth of the layer is the same, that is, the gate insulating layer and the insulating layer above the gate line metal layer are partially etched, so that the etching depth of the deep hole region of the gate line metal layer that needs to generate the via hole is The amount of etching depth of the shallow hole region of the metal layer of the data line where the via hole is to be formed is the same;
  • Step 306 etching, performing synchronous etching on the plurality of regions that need to generate via holes, until each via hole reaches a corresponding metal layer;
  • Step 307 depositing an electrode layer in the via hole to realize a connection between the corresponding metal layers, that is, a connection between the gate line metal layer and the data line metal layer.
  • the array substrate fabricated by using the above array substrate fabrication process has greatly improved the overetching phenomenon at the shallow via hole, and reduces the resistance in the region where the via hole having a shallow etching depth is excessive or Bad disconnection and other factors have improved the yield of the product.
  • the deep hole region where the deep hole is located is partially etched so that the etching depth of the deep hole region is the same as the etching depth of the shallow hole region where the shallow hole is located.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the array substrate manufacturing process provided by this embodiment uses the method described in the second embodiment.
  • the process includes:
  • Step 401 forming a gate line metal layer 6 on the substrate 1;
  • Step 402 forming a gate insulating layer 2 on the gate line metal layer 6;
  • Step 403 sequentially forming an active layer 3 and a data line metal layer 4 on the gate insulating layer 2;
  • Step 404 forming an insulating layer 5 over the data line metal layer 4 and the gate insulating layer 2;
  • Step 405, as shown in 7 is coated with a photoresist 7 on the insulating layer 5;
  • Step 406 exposing and developing, as shown in FIG. 8, completely exposing the photoresist of the deep hole region A of the gate line metal layer 6 to the photoresist of the shallow hole region B of the data line metal layer 4.
  • a portion of the photoresist 8 remains in the shallow hole region after development; after the photoresist in the deep hole region A is completely exposed, the etched surface in the deep hole region A is completely exposed; and the shallow hole region B is engraved The etched surface is also protected by the photoresist portion 8;
  • Step 407 as shown in FIG. 9, partially etching the fully exposed deep hole region A, the etching depth D1 is as shown in FIG. 9, and leaving a predetermined etching depth above the gate line metal layer 6.
  • the amount D2, the etch depth margin D2 is as shown in FIG. 9; the predetermined etch depth margin D2 remaining above the gate line metal layer 6 is the same as the etch depth D3 of the shallow hole region;
  • Step 408 as shown in FIG. 10, ashing to remove the exposure margin of the photoresist in the shallow hole region; by ashing, the exposure margin of the half-exposure photoresist in the shallow hole region is removed by ashing, The etched surface in the shallow hole region is exposed;
  • Step 409 etching the shallow hole region and the deep hole region until the deep hole of the deep hole region is connected to the gate line metal layer 6, and the shallow hole of the shallow hole region is connected to the data line metal Layer 5;
  • Step 410 removes excess photoresist.
  • the etching depth of the insulating layer 5 is the same as the etching depth of the gate insulating layer 2. Therefore, in the step pre-etching, the deep hole is pre-etched to the gate insulating layer 2.
  • Step 411 deposits an electrode layer to achieve a connection between the respective metal layers, that is, a connection between the gate line metal layer and the data line metal layer.
  • the via holes of the array substrate described in the first embodiment and the second embodiment are used to fabricate via holes.
  • the specific structure of the array substrate is various, and the metal layers in the array substrate that require via connections are various.
  • the number of deep holes and shallow holes may also have various options according to actual needs.
  • the deep metal layer may be a data line metal layer
  • the shallow metal layer is a pixel. Electrode layer, the electrode layer realizes the connection between the data line metal layer and the pixel electrode layer.

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Abstract

本公开涉及一种阵列基板过孔的制作方法，包括预刻蚀步骤，分别对多个需要生成过孔的区域中的至少一个区域所对的金属层上方的层级结构进行部分刻蚀，使得需要生成过孔的多个区域中与其相应金属层之间的刻蚀深度余量相同；刻蚀步骤，对所述多个需要生成过孔的区域进行同步刻蚀，直至各个过孔达到对应的金属层。本公开提供的阵列基板过孔的制作方法中各个刻蚀深度不同的区域进行分步刻蚀，预刻蚀步骤之后，各个过孔的刻蚀深度余量相同，然后经过刻蚀步骤对所有过孔进行同步刻蚀，使各个过孔同时达到对应的金属层，降低刻蚀深度较浅的过孔处产生的过刻不良现象，提高产品良率。

Description

一种阵列基板过孔的制作方法及阵列基板制作工艺 技术领域
本公开涉及阵列基板加工技术领域， 特别涉及一种阵列基板过孔的制作 方法及阵列基板制作工艺。 背景技术
在液晶显示面板的阵列基板制备工艺中， 过孔工艺是一项很重要的工 艺。 在阵列基板的制备工艺中， 通常通过过孔工艺将位于不同层级的金属棵 露或位于同一层级的不同金属部分棵露， 然后通过后续工艺将位于不同层级 的金属的棵露部分连接， 或将同位于同一层级的不同金属部分连接， 例如阵 列基板的栅极线与数据线之间的连接、 数据线与像素电极之间的连接以及公 共电极线的矩阵结构的形成等。 过孔工艺的优劣直接影响到产品的良率以及 最终面板的相关性能。
在阵列基板中， 位于不同层级的金属相对于待刻蚀的产品的上表面的深 度不同， 即刻蚀深度不同。 在某些情况下， 甚至同一层的不同金属部分相对 于待刻蚀的产品的上表面的深度也不同， 即刻蚀深度不同。 为便于描述， 在 本文中， 阵列基板中的刻蚀深度为两种： 距离阵列基板的刻蚀表面距离较远 的金属层称为深区金属层， 深区金属层对应的过孔称为深孔， 开设深孔的区 域称为深孔区域； 而距离阵列基板的刻蚀表面距离较近的金属层称为浅区金 属层， 浅区金属层对应的过孔称为浅孔， 开设浅孔的区域称为浅孔区域。 在 目前阵列基板制备工艺的过孔工艺中， 无论是深孔区域的深孔或浅孔区域的 浅孔， 都统一使用一掩膜板一次曝光刻蚀完成， 极易导致浅区金属层产生刻 蚀过度的现象。
以栅极线和数据线之间的过孔工艺为例， 如图 1和图 2所示， 图 1为常 规的过孔工艺中数据线金属层所处浅孔区域的浅孔已刻蚀至数据线金属层的 结构示意图； 图 2为常规的过孔工艺中栅极线金属层所处深孔区域的深孔已 刻蚀至栅极线金属层的结构示意图。
如图 1所示， 图 1所示的阵列基板包括基板 01 , 沉积于基板 01之上并 刻蚀之后的栅极线金属层 06,沉积于上述栅极线金属层 06及基板 01上的栅 极绝缘层 02, 依次沉积于栅极绝缘层 02且有源层 03以及数据线金属层 04, 以及， 覆盖于上述各层之上的绝缘层 05。
根据图 1所示的结构， 在栅极线金属层 06上具有栅极绝缘层 02和绝缘 层 05 , 从阵列基板的上表面形成过孔时的刻蚀深度较深， 属于深孔区域； 而 数据线金属层 04上只具有绝缘层 05 , 从阵列基板的上表面形成过孔时的刻 蚀深度较浅，属于浅孔区域。连接到栅极线金属层 06的深孔 061需要刻蚀栅 极绝缘层 02和数据绝缘层 05 , 而连接到数据线金属层 04的浅孔 041只需要 刻蚀绝缘层 05 , 因此当浅孔 041刻蚀完成后， 数据线金属层 04的表层金属 已暴露， 而深孔 061只刻蚀到栅极绝缘层 02, 还需要对刻蚀深度 dl的栅极 绝缘层 02进行刻蚀.
如图 2所示结构， 当深孔 061继续刻蚀时， 数据线金属层 04通过浅孔
041已经棵露的金属会继续刻蚀， 当深孔 061刻蚀至栅极线金属层 06时， 刻 蚀液会通过浅孔 041对数据线金属层 04中已经棵露的金属产生深度为 d2的 过度刻蚀， 进而对数据线金属层 04造成过刻不良。
过刻不良会导致金属表面氧化， 进而引起电阻过大或断路等不良的出 现， 直接影响产品的良率。 发明内容
本公开提供了一种阵列基板过孔的制作方法及阵列基板制作工艺， 以改 善现有技术中的过孔工艺中过孔深度较浅的过孔处产生的过刻不良， 提高产 品良率。
为达到上述目的， 本公开提供以下技术方案。
根据一方面， 本公开的实施例提供了一种阵列基板过孔的制作方法， 其 特征在于， 包括： 预刻蚀步骤， 分别对多个需要生成过孔的区域中的至少一 个区域所对应的金属层上方的层级结构进行部分刻蚀， 使得需要生成过孔的 多个区域中至相应金属层的刻蚀深度余量相同； 和刻蚀步骤， 对所述多个需 要生成过孔的区域进行同步刻蚀， 直至各个过孔达到其金属层。
在一个示例中， 所述多个需要生成过孔的区域中生成的过孔的刻蚀深度 为两种， 其中， 刻蚀深度较深的过孔称为深孔， 刻蚀深度较浅的过孔称为浅 孔； 预刻蚀步骤中， 对深孔所处的深孔区域进行部分刻蚀， 使得深孔区域的 刻蚀深度余量与所述浅孔所处的浅孔区域的刻蚀深度相同。
在一个示例中， 在所述预刻蚀步骤之前所述方法还包括以下步骤： 涂覆 光刻胶； 曝光和显影， 对深孔区域的光刻胶进行完全曝光， 对浅孔区域的光 刻胶进行半曝光， 从而保留浅孔区域中的部分光刻胶； 所述刻蚀步骤与所述 预刻蚀步骤之间还包括步骤：灰化，灰化去除浅孔区域内保留的部分光刻胶； 所述刻蚀步骤之后还包括步骤： 剥离， 将所述保留的部分光刻胶去除。
在一个示例中， 所述曝光步骤中， 使用具有全透光区和半透光区的半掩 膜板进行曝光， 其中， 所述半透掩膜板的全透光区与深孔区域对应， 半透光 区与浅孔区域对应。
根据另一方面， 本公开的实施例提供了一种阵列基板制作工艺， 其包括 以下步骤： 在基板上形成栅极线金属层； 在所述栅极线金属层上形成栅极绝 缘层； 在所述栅极绝缘层上依次形成有源层和数据线金属层； 在所述数据线 金属层以及栅极绝缘层之上形成绝缘层； 预刻蚀， 分别对多个需要生成过孔 的区域中的至少一个区域所对应的金属层上方的层级结构进行部分刻蚀， 使 得需要生成过孔的多个区域中至所述对应的金属层的刻蚀深度余量相同； 刻 蚀， 对所述多个需要生成过孔的区域进行同步刻蚀， 直至各个过孔到达所述 相应的金属层； 沉积电极层来填充所述过孔， 实现各金属层之间的连接。
在一个示例中， 位于所述深孔区域的金属层为栅极线金属层， 位于浅孔 区域的金属层为数据线金属层， 所述电极层连接所述栅极线金属层和数据线 金属层。
在一个示例中， 所述涂覆光刻胶步骤中， 在所述绝缘层上涂覆光刻胶； 所述曝光和显影步骤中， 对栅极线金属层所处的深孔区域的光刻胶进行完全 曝光， 对数据线金属层所处的浅孔区域的光刻胶进行半曝光， 显影后保留浅 孔区域中的部分光刻胶； 所述预刻蚀步骤中， 对完全曝光的深孔区域进行部 分刻蚀， 并在栅极线金属层上方留有预定的刻蚀深度余量， 所述预定的刻蚀 深度余量与上述数据线金属层所处的浅孔区域的刻蚀深度相同； 所述灰化步 骤中， 灰化去除浅孔区域内保留的部分光刻胶； 所述刻蚀步骤中， 对浅孔区 域以及深孔区域进行刻蚀， 直至深孔区域的深孔达到所述栅极线金属层， 同 时， 浅孔区域的浅孔达到所述数据线金属层； 所述剥离步骤中， 将多余光刻 胶剥离去除。
本公开提供的阵列基板过孔的制作方法中， 对各个需要生成过孔的区 域， 根据刻蚀至相应金属层的刻蚀深度不同而进行分步刻蚀。 首先， 通过预 刻蚀步骤对需要生成过孔的区域中刻蚀至相应的金属层的刻蚀深度较深的区 域进行部分刻蚀， 使得需要生成过孔的多个区域中刻蚀至相应金属层的刻蚀 深度余量相同。 当然， 这里所说的相同只是理论上相同的意思， 实际操作过 程中， 由于人为因素，刻蚀液等因素以及操作误差等各种不确定因素的存在， 各区域的刻蚀深度余量可以有所不同， 只要能够减小刻蚀步骤中对多个需要 生成过孔的区域进行同步刻蚀时至各金属层的刻蚀深度之间的差值即可。 然 后经过刻蚀步骤， 对所有需要生成过孔的区域进行同步刻蚀， 使各个过孔同 时达到其金属层； 通过该方法， 先将刻蚀深度不同的需要生成过孔区域中刻 蚀深度较深的过孔区域刻蚀掉一部分， 从而保证在刻蚀步骤中， 各个过孔之 间的刻蚀余量接近相同， 使各个过孔同时达到其对应的金属层， 降低刻蚀深 度较浅的过孔处产生的过刻现象。
所以， 本公开提供的阵列基板过孔的制作方法能够改善过孔工艺中刻蚀 深度较浅的过孔处产生的过刻不良现象， 提高产品良率。 附图说明
为了更清楚地说明本公开或现有技术中的技术方案， 下面将对本公开提 供的技术方案或现有技术描述中所需要使用的附图作简单地介绍， 显而易见 地， 下面描述中的附图仅仅是本公开的技术方案的部分具体实施方式图示说 明， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以 根据这些附图获得其他的附图。
图 1为现有技术中的过孔工艺中数据线金属层所处浅孔区域的浅孔已刻 蚀至数据线金属层的结构示意图；
图 2为现有技术中的过孔工艺中栅极线金属层所述深孔区域的深孔刻蚀 至栅极线金属层的结构示意图；
图 3为本公开实施例一提供的阵列基板过孔的制作方法的流程图； 图 4为本公开实施例二提供的阵列基板过孔的制作方法的流程图； 图 5为本公开实施例三提供的阵列基板制作工艺的流程图；
图 6为本公开实施例四提供的阵列基板制作工艺的流程图；
图 7为本公开实施例四提供的阵列基板制作工艺中步骤涂覆光刻胶之后 的阵列基板的结构示意图； 图 8为本公开实施例四提供的阵列基板制作工艺中步骤曝光之后的阵列 基板的结构示意图；
图 9为本公开实施例四提供的阵列基板制作工艺中步骤预刻蚀之后的阵 列基板的结构示意图；
图 10 为本公开实施例四提供的阵列基板制作工艺中步骤灰化之后的阵 列基板的结构示意图；
图 11 为本公开实施例四提供的阵列基板制作工艺中步骤刻蚀之后的阵 列基板的结构示意图；
图 12 为本公开实施例四提供的阵列基板制作工艺中步骤剥离之后的阵 列基板的结构示意图；
图 13 为本公开实施例四提供的阵列基板制作工艺中步骤沉积刻蚀电极 层之后的阵列基板的结构示意图。 具体实施方式
下面将结合本公开实施例中的附图， 对本公开实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本公开一部分实施例， 而 不是全部的实施例。 基于本公开中的实施例， 本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例， 都属于本公开保护的范围。
实施例一：
如图 3所示， 本实施例提供了一种阵列基板过孔的制作方法， 该方法包 括：
步骤 101 : 预刻蚀， 分别对多个需要生成过孔的区域中的至少一个区域 所对应的金属层上方的层级结构进行部分刻蚀， 使得在需要生成过孔的多个 区域中刻蚀至相应金属层的刻蚀深度余量相同；
步骤 102: 刻蚀， 对多个需要生成过孔的区域进行同步刻蚀， 直至各个 过孔达到相应金属层。
本公开提供的阵列基板过孔的制作方法中， 对各个需要生成过孔的区 域， 根据刻蚀至相应金属层的刻蚀深度不同而进行分步刻蚀。 首先， 通过步 骤 101预刻蚀对需要生成过孔的区域中刻蚀至相应的金属层的刻蚀深度较深 的区域进行部分刻蚀， 使得需要生成过孔的多个区域中刻蚀至相应金属层的 刻蚀深度余量相同。 当然， 这里所说的相同只是理论上相同的意思， 实际操 作过程中， 由于人为因素， 刻蚀液等因素以及操作误差等各种不确定因素的 存在， 各区域的刻蚀深度余量可以有所不同， 只要能够减小步骤 102刻蚀中 对多个需要生成过孔的区域进行同步刻蚀时至各金属层的刻蚀深度之间的差 值即可。然后经过步骤 102刻蚀，对所有需要生成过孔的区域进行同步刻蚀， 使各个过孔同时达到其金属层； 通过该方法， 先将刻蚀深度不同的需要生成 过孔区域中刻蚀深度较深的过孔区域刻蚀掉一部分， 从而保证在步骤 102刻 蚀中， 各个过孔之间的刻蚀余量接近相同， 使各个过孔同时达到其对应的金 属层， 降低刻蚀深度较浅的过孔处产生的过刻现象。
所以， 本公开提供的阵列基板过孔的制作方法能够改善过孔工艺中刻蚀 深度较浅的过孔处产生的过刻不良现象， 提高产品良率。
实施例二：
如上所述， 在阵列基板的多个需要生成过孔的区域中的过孔的刻蚀深度 为两种， 其中， 刻蚀深度较深的称为深孔， 刻蚀深度较浅的称为浅孔。 对应 地， 深孔所处的区域称为深孔区域， 浅孔所处的区域称为浅孔区域。 如图 4 所示， 本实施例提供的阵列基板过孔的制作方法包括：
步骤 201 : 涂覆光刻胶；
步骤 202: 曝光和显影， 对深孔区域的光刻胶进行完全曝光， 对浅孔区 域的光刻胶进行半曝光， 从而在显影后在浅孔区域保留部分的光刻胶；
步骤 203: 预刻蚀， 对深孔区域进行部分刻蚀， 并在深孔区域的金属层 上方留有预定的刻蚀深度余量， 所述预定的刻蚀深度余量与浅孔区域的刻蚀 深度相同：
步骤 204, 灰化， 灰化去除浅孔区域内部分的光刻胶；
步骤 205 , 刻蚀， 对浅孔区域以及深孔区域进行同步刻蚀， 直至深孔区 域的深孔达到对应的金属层， 同时， 浅孔区域的浅孔达到对应的金属层； 步骤 206剥离， 将多余光刻胶剥离去除。
本实施例中， 在步骤 201涂覆光刻胶之后， 通过步骤 202曝光， 将深孔 区域的刻蚀部位棵露， 而浅孔区域的刻蚀部位被半曝光之后剩余的光刻胶保 护，从而实现刻蚀时只对深孔区域刻蚀的效果；在步骤 203预刻蚀完成之后， 经过步骤 204灰化， 将浅孔区域内半曝光剩余的光刻胶灰化去除， 将浅孔区 域内的刻蚀部位棵露 , 然后进行步骤 205刻蚀 , 对深孔区域以及浅孔区域进 行同步刻蚀， 步骤 205刻蚀完成之后， 通过步骤 206剥离将剩余的光刻胶去 除， 从而不会影响后续工艺。
优选地， 上述步骤 202曝光中， 使用具有全透光区和半透光区的半透掩 膜板进行曝光， 其中， 半透掩膜板的全透光区与深孔区域对应， 半透光区与 浅孔区域对应。
本实施例通过釆用半透掩膜板进行的半曝光技术， 通过涂覆一次光刻胶 即可实现对深孔区域和浅孔区域的分步刻蚀， 可以简化工艺。
实施例三：
如图 5所示， 本公开还提供了一种阵列基板制作工艺， 该工艺釆用了实 施例一所述的方法。 该工艺包括：
步骤 301 , 在基板上形成栅极线金属层；
步骤 302 , 在栅极线金属层上形成栅极绝缘层；
步骤 303 , 在栅极绝缘层上依次形成有源层和数据线金属层；
步骤 304 , 在数据线金属层以及栅极绝缘层之上形成绝缘层。
如上所述， 在阵列基板的多个需要生成过孔的区域中的过孔的刻蚀深度 为两种， 其中， 刻蚀深度较深的称为深孔， 刻蚀深度较浅的称为浅孔。 对应 地， 深孔所处的区域称为深孔区域， 浅孔所处的区域称为浅孔区域。
步骤 305 , 预刻蚀， 分别对多个需要生成过孔的区域中的至少一个区域 所对应的金属层上方的层级结构进行部分刻蚀， 使得需要生成过孔的多个区 域中至对应的金属层的刻蚀深度余量相同， 即对栅极线金属层上方的栅极绝 缘层和绝缘层进行部分刻蚀， 使得需要生成过孔的栅极线金属层的深孔区域 的刻蚀深度余量与需要生成过孔的数据线金属层的浅孔区域的刻蚀深度余量 相同；
步骤 306 , 刻蚀， 对所述多个需要生成过孔的区域进行同步刻蚀， 直至 各个过孔达到对应的金属层；
步骤 307 , 在过孔中沉积电极层， 实现相应金属层之间的连接， 即栅极 线金属层和数据线金属层之间的连接。
使用上述阵列基板制作工艺制作的阵列基板， 其刻蚀深度较浅的过孔处 的过刻现象得到了极大地改善， 减少了刻蚀深度较浅的过孔所对的区域内电 阻过大或者断路等不良， 提高了产品的良率。 在步骤 305预刻蚀中， 对深孔所处的深孔区域进行部分刻蚀， 使得深孔 区域的刻蚀深度余量与浅孔所处的浅孔区域的刻蚀深度相同。
实施例四：
如图 6和图 7所示， 本实施例提供的阵列基板制作工艺， 该工艺釆用了 实施例二所述的方法。 该工艺包括：
步骤 401 , 在基板 1上形成栅极线金属层 6;
步骤 402 , 在栅极线金属层 6上形成栅极绝缘层 2；
步骤 403 , 在栅极绝缘层 2上依次形成有源层 3和数据线金属层 4; 步骤 404, 在数据线金属层 4以及栅极绝缘层 2之上形成绝缘层 5; 步骤 405 , 如图 7所示， 在绝缘层 5上涂覆光刻胶 7;
步骤 406, 曝光和显影， 如图 8所示， 对栅极线金属层 6所对深孔区域 A的光刻胶进行完全曝光， 对数据线金属层 4所对浅孔区域 B的光刻胶进行 半曝光， 显影后在浅孔区域保留部分的光刻胶 8; 深孔区域 A的光刻胶完全 曝光之后， 深孔区域 A内的刻蚀表面完全棵露； 而浅孔区域 B的刻蚀表面还 被光刻胶部分 8保护；
步骤 407 , 如图 9所示， 对完全曝光的深孔区域 A进行部分刻蚀， 刻蚀 深度 D1如图 9中所示， 并在栅极线金属层 6上方留有预定的刻蚀深度余量 D2, 刻蚀深度余量 D2如图 9中所示； 栅极线金属层 6上方留有的预定的刻 蚀深度余量 D2与浅孔区域的刻蚀深度 D3相同；
步骤 408, 如图 10所示， 灰化去除浅孔区域内光刻胶的曝光余量 8; 通 过灰化， 将浅孔区域内半曝光的光刻胶的曝光余量 8灰化去除， 是浅孔区域 内的刻蚀表面棵露；
步骤 409, 如图 11所示， 对浅孔区域以及深孔区域进行刻蚀， 直至深孔 区域的深孔连接到栅极线金属层 6, 同时， 浅孔区域的浅孔连接到数据线金 属层 5;
步骤 410, 如图 12所示， 将多余光刻胶剥离去除。
具体的， 上述绝缘层 5的刻蚀深度与栅极绝缘层 2的刻蚀深度相同， 因 此， 上述步骤预刻蚀中， 所述深孔预刻蚀至栅极绝缘层 2。
步骤 411沉积电极层， 实现相应金属层之间的连接， 即栅极线金属层和 数据线金属层之间的连接。
上述实施例三以及实施例四， 仅仅列举了一种阵列基板的制作工艺， 该 工艺中釆用了实施例一以及实施例二描述的阵列基板过孔的制作方法制作过 孔； 当然， 阵列基板的具体结构多种多样， 阵列基板中需要过孔连接的金属 层多种多样， 深孔和浅孔的个数根据实际需要也可以有多种选择， 上述的阵 如， 具有其它层级结构的阵列基板中， 其深区金属层可以为数据线金属 层， 浅区金属层为像素电极层， 电极层实现数据线金属层与像素电极层之间 的连接。
当然，深区金属层和浅区金属层还可以有其他选择，这里不再——赘述。 以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关技术领 域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各 种变化和变型， 因此所有等同的技术方案也属于本发明的范畴， 本发明的专 利保护范围应由权利要求限定。

Claims

权利要求书
1、 一种阵列基板过孔的制作方法， 其特征在于， 包括：
预刻蚀步骤， 分别对多个需要生成过孔的区域中的至少一个区域所对应 的金属层上方的层级结构进行部分刻蚀， 使得需要生成过孔的多个区域中至 相应金属层的刻蚀深度余量相同；
刻蚀步骤， 对所述多个需要生成过孔的区域进行同步刻蚀， 直至各个过 孔达到其金属层。
2、 根据权利要求 1 所述的阵列基板过孔的制作方法， 其特征在于， 所 述多个需要生成过孔的区域中生成的过孔的刻蚀深度为两种， 其中， 刻蚀深 度较深的过孔称为深孔， 刻蚀深度较浅的过孔称为浅孔；
预刻蚀步骤中， 对深孔所处的深孔区域进行部分刻蚀， 使得深孔区域的 刻蚀深度余量与所述浅孔所处的浅孔区域的刻蚀深度相同。
3、 根据权利要求 2所述的阵列基板过孔的制作方法， 其特征在于， 在 所述预刻蚀步骤之前所述方法还包括以下步骤：
涂覆光刻胶；
曝光和显影， 对深孔区域的光刻胶进行完全曝光， 对浅孔区域的光刻胶 进行半曝光， 从而保留浅孔区域中的部分光刻胶；
所述刻蚀步骤与所述预刻蚀步骤之间还包括步骤：
灰化， 灰化去除浅孔区域内保留的部分光刻胶；
所述刻蚀步骤之后还包括步骤：
剥离， 将所述保留的部分光刻胶去除。
4、 根据权利要求 3 所述的阵列基板过孔的制作方法， 其特征在于， 所 述曝光步骤中， 使用具有全透光区和半透光区的半掩膜板进行曝光， 其中， 所述半透掩膜板的全透光区与深孔区域对应， 半透光区与浅孔区域对应。
5、 一种阵列基板制作工艺， 其特征在于， 包括以下步骤：
在基板上形成栅极线金属层；
在所述栅极线金属层上形成栅极绝缘层；
在所述栅极绝缘层上依次形成有源层和数据线金属层；
在所述数据线金属层以及栅极绝缘层之上形成绝缘层；
预刻蚀， 分别对多个需要生成过孔的区域中的至少一个区域所对应的金 属层上方的层级结构进行部分刻蚀， 使得需要生成过孔的多个区域中至所述 对应的金属层的刻蚀深度余量相同；
刻蚀， 对所述多个需要生成过孔的区域进行同步刻蚀， 直至各个过孔到 达所述相应的金属层；
沉积电极层来填充所述过孔， 实现各金属层之间的连接。
6、 根据权利要求 5所述的阵列基板制作工艺， 其特征在于， 所述多个 需要生成过孔的区域中生成的过孔需刻蚀的刻蚀深度为两种， 其中， 刻蚀深 度较深的过孔称为深孔， 刻蚀深度较浅的过孔称为浅孔；
在预刻蚀步骤中， 对深孔所处的深孔区域进行部分刻蚀， 使得深孔区域 的刻蚀深度余量与所述浅孔所处的浅孔区域的刻蚀深度相同。
7、 根据权利要求 6所述的阵列基板制作工艺， 其特征在于， 位于所述 深孔区域的金属层为栅极线金属层，位于浅孔区域的金属层为数据线金属层， 所述电极层连接所述栅极线金属层和数据线金属层。
8、 根据权利要求 7所述的阵列基板制作工艺， 其特征在于， 在所述预 刻蚀步骤之前所述方法还包括以下步骤：
涂覆光刻胶；
曝光和显影， 对深孔区域的光刻胶进行完全曝光， 对浅孔区域的光刻胶 进行半曝光， 从而保留浅孔区域中的部分光刻胶；
所述刻蚀步骤与所述预刻蚀步骤之间还包括步骤：
灰化， 灰化去除浅孔区域内保留的部分光刻胶；
所述刻蚀步骤之后还包括步骤：
剥离， 将所述保留的部分光刻胶去除
9、 根据权利要求 8所述的阵列基板制作工艺， 其特征在于：
所述涂覆光刻胶步骤中， 在所述绝缘层上涂覆光刻胶；
所述曝光和显影步骤中， 对栅极线金属层所处的深孔区域的光刻胶进行 完全曝光， 对数据线金属层所处的浅孔区域的光刻胶进行半曝光， 显影后保 留浅孔区域中的部分光刻胶；
所述预刻蚀步骤中， 对完全曝光的深孔区域进行部分刻蚀， 并在栅极线 金属层上方留有预定的刻蚀深度余量， 所述预定的刻蚀深度余量与上述数据 线金属层所处的浅孔区域的刻蚀深度相同；
所述灰化步骤中， 灰化去除浅孔区域内保留的部分光刻胶； 所述刻蚀步骤中， 对浅孔区域以及深孔区域进行刻蚀， 直至深孔区域的 深孔达到所述栅极线金属层， 同时， 浅孔区域的浅孔达到所述数据线金属层； 所述步骤剥离中， 将多余光刻胶剥离去除。
10、 根据权利要求 9所述的阵列基板制作工艺， 其特征在于， 在所述曝 光和显影步骤中， 使用具有完全曝光区和半曝光区的半掩模板， 所述完全曝 光区对应于所述深孔区域， 所述半曝光区对应于所述浅孔区域。
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