WO2013179648A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2013179648A1 WO2013179648A1 PCT/JP2013/003357 JP2013003357W WO2013179648A1 WO 2013179648 A1 WO2013179648 A1 WO 2013179648A1 JP 2013003357 W JP2013003357 W JP 2013003357W WO 2013179648 A1 WO2013179648 A1 WO 2013179648A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0839—Cathode regions of thyristors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Definitions
- the present disclosure relates to a semiconductor device having an insulated gate bipolar transistor (hereinafter simply referred to as IGBT) element.
- IGBT insulated gate bipolar transistor
- an N ⁇ type drift layer is formed on a P + type collector layer, and a P type base layer is formed on a surface layer portion of the drift layer.
- An N + -type emitter layer is formed on the surface layer of the base layer.
- a plurality of trenches that penetrate the base layer and the emitter layer and reach the drift layer are extended in a stripe shape.
- a gate insulating film and a gate electrode are sequentially formed on the wall surface of each trench, and a trench gate structure is configured by the trench, the gate insulating film, and the gate electrode.
- an emitter electrode is provided on the base layer and the emitter layer via an interlayer insulating film, and the base layer, the emitter layer, and the emitter electrode are electrically connected via a contact hole formed in the interlayer insulating film. It is connected to the.
- a collector electrode electrically connected to the collector layer is provided on the back surface of the collector layer.
- a predetermined voltage is applied to a part of the plurality of gate electrodes via the first resistor, and the remaining part of the plurality of gate electrodes.
- a predetermined voltage is applied to the gate electrode via a second resistor having a resistance value smaller than that of the first resistor.
- the turn-off voltage is applied to a part of the gate electrodes through the first resistor and the turn-off voltage is applied to the remaining gate electrode through the second resistor. For this reason, the gate voltage drop rate of the remaining gate electrodes is faster than the gate voltage drop rate of some of the gate electrodes.
- the gate voltage of the remaining gate electrode can be made lower than the threshold voltage before the gate voltage of some of the gate electrodes becomes lower than the threshold voltage of the MOS gate (hereinafter simply referred to as threshold voltage).
- the collector current can be reduced in advance.
- the collector current becomes zero and the IGBT element is turned off. That is, the collector current can be reduced stepwise by providing a time difference so that the gate voltage of each gate electrode becomes smaller than the threshold voltage. For this reason, compared with the case where each gate electrode is made lower than a threshold voltage at once, the magnitude
- a predetermined voltage is applied to a part of the gate electrodes via the first resistance, and a predetermined voltage is applied to the remaining gate electrodes via the second resistance having a resistance value smaller than that of the first resistance. It doesn't happen only to things. That is, the same occurs in the semiconductor device in which the gate voltage change rate (rise rate and fall rate) in the remaining gate electrode is faster than the gate voltage change rate (rise rate and fall rate) in some gate electrodes. To do.
- the above phenomenon occurs not only in a trench gate type semiconductor device but also in a planar gate type semiconductor device, and not only in a semiconductor device in which an N channel type IGBT element is formed, but also in a P channel type semiconductor device. The same occurs in a semiconductor device in which an IGBT element is formed.
- an object of the present disclosure is to provide a semiconductor device that can suppress a surge voltage at turn-on while suppressing a surge voltage at turn-off in a semiconductor device having an IGBT element.
- An emitter electrode electrically connected to the emitter layer and the base layer, and a collector electrode electrically connected to the collector layer, and the gate voltage of the remaining gate electrode has a rate of change in the gate voltage in a part of the gate electrodes
- the emitter layer is formed only in contact with the gate insulating film in which a part of the gate electrode is disposed, and is not formed in contact with the gate insulating film in which the remaining gate electrode is disposed.
- the emitter layer is not formed in contact with the gate insulating film where the remaining gate electrode is disposed. For this reason, even if a turn-on voltage is applied to the remaining gate electrode and the gate voltage becomes higher than the threshold voltage, electrons are not supplied to the drift layer, and the IGBT element is not turned on. That is, the turn-on of the IGBT element can be controlled by a part of the gate electrodes whose gate voltage rise rate is slower than that of the remaining gate electrode. Therefore, the surge voltage at the turn-on time can be reduced while the surge voltage at the turn-off time of the IGBT element is reduced.
- the drawing 1 is a diagram illustrating a circuit configuration of a semiconductor device according to a first embodiment of the present disclosure. It is a figure which shows the cross-sectional structure of the semiconductor chip shown in FIG.
- FIG. 3 is a schematic plan view showing the arrangement of gate electrodes shown in FIG. 2. It is a figure which shows the relationship between gate voltage and time when a turn-on voltage is applied. It is a figure which shows the relationship between gate voltage and time when a turn-off voltage is applied. It is a figure showing circuit composition of a semiconductor device in a 2nd embodiment of this indication. It is a figure showing the section composition of the semiconductor chip in other embodiments of this indication. It is a figure showing the section composition of the semiconductor chip in other embodiments of this indication.
- FIG. 1 A first embodiment of the present disclosure will be described. As shown in FIG. 1, the semiconductor device of the present embodiment is configured by connecting a gate control circuit 30 to a semiconductor chip 10 on which an IGBT element is formed. First, the configuration of the semiconductor chip 10 will be described.
- an N-type field stop layer (hereinafter referred to as FS layer) 12 is formed on a P + -type collector layer 11.
- a ⁇ type drift layer 13 is formed.
- the FS layer 12 is not necessarily required, but is provided to improve the breakdown voltage and steady loss performance by preventing the depletion layer from spreading.
- a P-type base layer 14 is formed on the surface layer portion of the drift layer 13. That is, the base layer 14 is formed at a position separated from the collector layer 11 with the drift layer 13 interposed therebetween.
- a plurality of trenches 15 that penetrates the base layer 14 and reaches the drift layer 13 are formed.
- the plurality of trenches 15 are formed at a predetermined interval (pitch) and have a stripe structure extending in parallel in a predetermined direction (a direction perpendicular to the paper surface in FIG. 1).
- the gate electrodes 17a and 17b are alternately formed in the extending direction of the trench 15 and in the vertical direction (left and right direction in FIG. 1).
- the gate electrode 17 a is connected to the gate pad 19 a through the gate wiring 18, and the gate electrode 17 b is connected to the gate pad 19 b through the gate wiring 18.
- the gate electrode 17a will be described as a normal gate electrode 17a, the gate electrode 17b as a control gate electrode 17b, the gate pad 19a as a normal gate pad 19a, and the gate pad 19b as a control gate pad 19b.
- the normal gate electrode 17a corresponds to a part of the plurality of gate electrodes of the present disclosure
- the control gate electrode 17b is the remaining gate electrode of the plurality of gate electrodes of the present disclosure. It corresponds to.
- the gate wiring 18 is configured by patterning polysilicon when the gate electrodes 17a and 17b are configured, for example.
- an N + -type emitter layer 20 is formed on the surface layer portion of the base layer 14. Specifically, the emitter layer 20 is formed in contact with only the gate insulating film 16 in which the normal gate electrode 17a is disposed in the surface layer portion of the base layer 14, and the gate insulating film in which the control gate electrode 17b is disposed. 16 is not formed in contact with. In other words, the emitter layer 20 is usually formed so as to be in contact with only the side surface of the trench 15 in which the gate electrode 17a is embedded, and is formed in contact with the side surface of the trench 15 in which the control gate electrode 17b is embedded. Not. The emitter layer 20 extends in a bar shape along the longitudinal direction of the trench 15 and has a structure that terminates inside the tip of the trench 15.
- a P + -type body layer 21 is formed at a position spaced from the side surface of each trench 15.
- the body layer 21 is also extended in a rod shape along the longitudinal direction of the trench 15, and has a structure that terminates inside the tip of the trench 15.
- the emitter layer 20 and the body layer 21 are sufficiently higher in concentration than the base layer 14 and are terminated in the base layer 14.
- An interlayer insulating film 22 made of BPSG or the like is formed on the base layer 14.
- a contact hole 22 a is formed in the interlayer insulating film 22, and a part of the emitter layer 20 and the body layer 21 are exposed from the interlayer insulating film 22.
- An emitter electrode 23 is formed on the interlayer insulating film 22, and the emitter electrode 23 is electrically connected to the emitter layer 20 and the body layer 21 through a contact hole 22a.
- a gate wiring 18, a normal gate pad 19a, and a control gate pad 19b are formed on the interlayer insulating film 22 in a cross section different from that in FIG.
- a collector electrode 24 that is electrically connected to the collector layer 11 is formed on the back side of the collector layer 11.
- the N type, the N ⁇ type, and the N + type correspond to the first conductivity type of the present disclosure
- the P type and the P + type correspond to the second conductivity type of the present disclosure.
- the semiconductor chip 10 is connected to a gate control circuit 30 formed on a circuit chip or the like.
- the normal gate electrode 17a is connected to the gate control circuit 30 through the normal gate pad 19a and the first resistor R1
- the control gate electrode 17b has a resistance value smaller than that of the control gate pad 19b and the first resistor R1. It is connected to the gate control circuit 30 through the two resistors R2. That is, in the semiconductor device of this embodiment, the gate voltage change rate (rise rate and fall rate) in the normal gate electrode 17a is slower than the gate voltage change rate (rise rate and fall rate) in the control gate electrode 17b. .
- the gate voltage at the control gate electrode 17b is higher than the threshold voltage faster than the gate voltage at the normal gate electrode 17a, and the N-type inversion occurs in the portion of the base layer 14 that contacts the trench 15 in which the control gate electrode 17b is embedded. A layer is formed.
- the emitter layer 20 is not formed so as to be in contact with the side surface of the trench 15 in which the control gate electrode 17b is embedded. For this reason, no electrons are supplied from the emitter electrode 23 to the drift layer 13 even when the gate voltage of the control gate electrode 17b becomes larger than the threshold voltage. Therefore, even if the gate voltage of the control gate electrode 17b becomes larger than the threshold voltage, the IGBT element is not turned on.
- an N-type inversion layer is formed in a portion of the base layer 14 in contact with the trench 15 in which the normal gate electrode 17a is embedded. Since the emitter layer 20 is usually formed so as to be in contact with the side surface of the trench 15 in which the gate electrode 17a is embedded, electrons are supplied from the emitter layer 20 to the drift layer 13 via the inversion layer and the collector layer. The holes are supplied from 11 to the drift layer 13, and the resistance value of the drift layer 13 is lowered by conductivity modulation, so that the IGBT element is turned on.
- the turn-on of the IGBT element can be controlled by the normal gate electrode 17a. Since the gate voltage rise rate of the normal gate electrode 17a is slower than the gate voltage rise rate of the control gate electrode 17b, the surge voltage can be reduced.
- the gate voltage in the control gate electrode 17b is lower than the threshold voltage faster than the gate voltage in the normal gate electrode 17a.
- the layer disappears first. Then, the hole flow path in the base layer 14 is expanded, and a part of the holes accumulated in the drift layer 13 are extracted from the emitter electrode 23 through the base layer 14 and the body layer 21, and the collector current is reduced. .
- the gate voltage of the normal gate electrode 17a also becomes lower than the threshold voltage, and the inversion layer formed in the portion of the base layer 14 in contact with the trench 15 in which the normal gate electrode 17a is embedded disappears. Then, the hole flow path in the base layer 14 is expanded, and the holes accumulated in the drift layer 13 are extracted from the emitter electrode 23 through the base layer 14 and the body layer 21, and the collector current becomes zero.
- the collector current can be reduced stepwise by providing a time difference so that the gate voltage of each of the gate electrodes 17a and 17b is equal to or lower than the threshold voltage. For this reason, compared with the case where each gate electrode 17a, 17b is made lower than a threshold voltage at once, the magnitude
- the emitter layer 20 is not formed so as to be in contact with the side surface of the trench 15 in which the control gate electrode 17b is embedded. For this reason, even if a turn-on voltage is applied to the control gate electrode 17b and the gate voltage of the control gate electrode 17b becomes higher than the threshold voltage, electrons are not supplied to the drift layer 13 and the IGBT element is not turned on. That is, the turn-on of the IGBT element can be controlled by the normal gate electrode 17a whose gate voltage rise rate is slower than that of the control gate electrode 17b. Therefore, the surge voltage at the turn-on time can be reduced while the surge voltage at the turn-off time of the IGBT element is reduced.
- the gate electrodes 17 a and 17 b are alternately formed in the direction perpendicular to the extending direction of the trench 15. For this reason, electrons can be uniformly supplied to the drift layer 13 at the time of turn-on, and holes can be uniformly discharged from the drift layer 13 at the time of turn-off. That is, it is possible to suppress accumulation of electrons and holes only in a specific region of the drift layer 13, and it is possible to suppress the occurrence of current concentration and the destruction of the IGBT element.
- the first and second resistors R1 and R2 are incorporated in the semiconductor chip 10 with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Omitted.
- the normal gate electrode 17a and the normal gate pad 19a are connected via the first resistor R1, and the control gate electrode 17b and the control gate pad 19b are connected to the second resistor. It is connected via R2. That is, the first and second resistors R1 and R2 are built in the semiconductor chip 10.
- Such first and second resistors R1 and R2 are configured by changing the material constituting the gate wiring 18.
- the gate wiring 18 connecting the normal gate electrode 17a and the normal gate pad 19a is made of polysilicon
- the gate wiring 18 connecting the control gate electrode 17b and the control gate pad 19b is made of a metal such as aluminum, gold, or silver. Consists of wiring.
- the first and second resistors R1 and R2 having a resistance value of the second resistor R2 smaller than the resistance value of the first resistor R1 can be configured.
- the first conductivity type is N type and the second conductivity type is P type.
- the first conductivity type may be P type and the second conductivity type may be N type.
- the trench gate type IGBT element has been described.
- a planar gate type IGBT element may be used.
- the magnitude of the surge voltage at turn-on can be reduced by not forming the emitter layer 20 in contact with the gate insulating film 16 in which the control gate electrode 17b is disposed, as in the above embodiments.
- the vertical IGBT element in which a current flows in the thickness direction of the drift layer 13 has been described.
- a lateral IGBT element in which a current flows in the plane direction of the drift layer 13 may be used.
- the gate electrode 17a and the control gate electrode 17b are described as having a stripe structure. However, after the gate electrodes 17a and 17b are extended in parallel, they are routed at the tip portions thereof. By doing so, it may be a ring structure. That is, in each of the embodiments described above, the trench 15 may be formed in an annular structure by extending in parallel and then being routed at the tip thereof.
- FIG. 6 is a diagram showing a cross-sectional configuration of the semiconductor chip 10 in a modified example.
- control gate electrodes 17b may be arranged every two normal gate electrodes 17a. Further, although not particularly illustrated, the control gate electrodes 17b may be disposed every three or four normal gate electrodes 17a. Further, for example, the normal gate electrodes 17a may be collectively arranged on one side and the control gate electrodes 17b may be collectively arranged on the other side in the extending direction and the vertical direction. That is, by using the IGBT element having the control gate electrode 17b, the surge voltage at turn-off can be reduced. Further, by not forming the emitter layer 20 so as to be in contact with the side surface of the trench 15 in which the control gate electrode 17b is embedded, the surge voltage at turn-on can be reduced.
- an N + -type cathode layer 25 adjacent to the collector layer 11 is provided, and the drift layer 13 is formed on the collector layer 11 and the cathode layer 25.
- the present disclosure can also be applied to a so-called RC (Reverse-Conducting) -IGBT element in which the region where the collector layer 11 is formed is an IGBT region and the region where the cathode layer 25 is formed is a diode region.
- the collector layer 11 and the cathode layer 25 may be formed in a lattice shape, for example.
- the semiconductor chip 10 includes the normal gate pad 19a and the control gate pad 19b.
- the normal gate electrode 17a and the control gate electrode 17b may be connected to a common gate pad. Good. Even in such a configuration, a predetermined voltage is normally applied to the gate electrode 17a via the first resistor R1, and a predetermined voltage is applied to the control gate electrode 17b via the second resistor R2. The same effect as the embodiment can be obtained.
- the normal gate electrode 17a is connected to the gate control circuit 30 via the first resistor R1
- the control gate electrode 17b is connected to the gate control circuit 30 via the second resistor R2.
- the semiconductor device in which the gate voltage change rate in the normal gate electrode 17a is slower than the gate voltage change rate in the control gate electrode 17b has been described.
- the rate of change of the gate voltage at the normal gate electrode 17a may be made slower than the rate of change of the gate voltage at the control gate electrode 17b, for example, by connecting an external capacitor.
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Abstract
Description
(第1実施形態)
本開示の第1実施形態について説明する。図1に示されるように、本実施形態の半導体装置は、IGBT素子が形成された半導体チップ10にゲート制御回路30が接続されて構成されている。まず、半導体チップ10の構成について説明する。
(第2実施形態)
本開示の第2実施形態について説明する。本実施形態は、第1実施形態に対して第1、第2抵抗R1、R2を半導体チップ10内に組み込んだものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
(変形例)
本開示は、実施形態に準拠して記述されたが、当該実施形態や構造に限定されるものではない。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。
Claims (5)
- 第1導電型のドリフト層(13)と、
前記ドリフト層の表層部に形成された第2導電型のベース層(14)と、
前記ドリフト層のうち前記ベース層と離間した位置に形成された第2導電型のコレクタ層(11)と、
前記ベース層の表面に形成された複数のゲート絶縁膜(16)と、
前記ゲート絶縁膜上にそれぞれ形成された複数のゲート電極(17a、17b)と、
前記ベース層の表層部に形成されたエミッタ層(20)と、
前記エミッタ層および前記ベース層と電気的に接続されたエミッタ電極(23)と、
前記コレクタ層と電気的に接続されたコレクタ電極(24)と、を備え、
前記複数のゲート電極のうち、一部のゲート電極(17a)におけるゲート電圧の変化速度が残部のゲート電極(17b)におけるゲート電圧の変化速度より遅くされた半導体装置において、
前記エミッタ層は、前記一部のゲート電極が配置される前記ゲート絶縁膜にのみ接して形成されており、前記残部のゲート電極が配置される前記ゲート絶縁膜に接して形成されていないことを特徴とする半導体装置。 - 前記一部のゲート電極は、第1抵抗(R1)を介して所定電圧が印加され、前記残部のゲート電極は、前記第1抵抗より抵抗値の小さい第2抵抗(R2)を介して所定電圧が印加されることを特徴とする請求項1に記載の半導体装置。
- 前記ベース層を貫通して前記ドリフト層に達し、所定方向に延設された複数のトレンチ(15)を備え、
前記コレクタ層は前記ドリフト層の表層部側と反対側の裏面側に配置されており、
前記ゲート絶縁膜は前記トレンチの壁面にそれぞれ形成されることによって前記ベース層の表面に形成され、
前記エミッタ層は、前記一部のゲート電極が配置される前記トレンチの側面のみに接するように形成されており、前記残部のゲート電極が配置される前記トレンチの側面に接するように形成されていないことを特徴とする請求項1または2に記載の半導体装置。 - 前記複数のゲート電極は、前記所定方向と垂直方向において、前記一部のゲート電極と前記残部のゲート電極とが交互に配列されていることを特徴とする請求項3に記載の半導体装置。
- 前記コレクタ層に隣接する第2導電型のカソード層(25)を備えていることを特徴とする請求項1ないし4のいずれか1つに記載の半導体装置。
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JP7091204B2 (ja) | 2018-09-19 | 2022-06-27 | 株式会社東芝 | 半導体装置 |
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JP7199270B2 (ja) | 2019-03-20 | 2023-01-05 | 株式会社東芝 | 半導体装置及び半導体回路 |
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