WO2013140663A1 - Module à semi-conducteur et son procédé de fabrication - Google Patents

Module à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2013140663A1
WO2013140663A1 PCT/JP2012/079910 JP2012079910W WO2013140663A1 WO 2013140663 A1 WO2013140663 A1 WO 2013140663A1 JP 2012079910 W JP2012079910 W JP 2012079910W WO 2013140663 A1 WO2013140663 A1 WO 2013140663A1
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WO
WIPO (PCT)
Prior art keywords
circuit electrode
semiconductor module
layer
insulating
dielectric layer
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PCT/JP2012/079910
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English (en)
Japanese (ja)
Inventor
厚 山竹
塩田　裕基
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三菱電機株式会社
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Priority to JP2014505966A priority Critical patent/JP5766347B2/ja
Publication of WO2013140663A1 publication Critical patent/WO2013140663A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor module and a manufacturing method thereof, and more particularly to an electric field relaxation structure of a semiconductor module used at a high voltage.
  • Power semiconductor modules widely used in power conversion devices and the like have a high applied voltage among semiconductor modules, and local discharge due to electric field concentration tends to occur at the semiconductor substrate edge or the like. As a result, the power semiconductor element may be destroyed or malfunctioned, so that a structure that reduces electric field concentration and suppresses local discharge is required.
  • Patent Document 1 discloses a circuit board that has been subjected to R processing, C surface processing, or step processing so that a conductor layer end portion of an electric circuit pattern provided on an insulating substrate has a gentle curve. .
  • the end portion of the joint surface between the conductor layer of the electric circuit pattern and the substrate has a cross-sectional structure in which it enters inside the outermost peripheral end portion of the conductor layer of the circuit pattern.
  • an electric field relaxation structure there is a method of obtaining an electric field relaxation effect by adding a conductor so as to protrude from the upper end portion of the circuit electrode. In this method, a high electric field is generated at the protruding end portion of the high potential conductor.
  • an object of the present invention is to obtain a semiconductor module that can alleviate electric field concentration of a circuit electrode and suppress local discharge.
  • a semiconductor module according to the present invention is a semiconductor module provided with a circuit electrode and a semiconductor element provided on an insulating substrate, and an insulating sealing material covering them, and is provided on the insulating substrate along the periphery of the circuit electrode. And an insulating layer whose end is bonded to the end of the circuit electrode, and a dielectric layer provided over the circuit electrode and the insulating layer so as to cover the bonding surface of the circuit electrode and the insulating layer It is equipped with.
  • a semiconductor module including a circuit electrode and a semiconductor element provided on an insulating substrate, and an insulating sealing material covering them, provided on the insulating substrate along a peripheral edge of the circuit electrode, and an end portion thereof An insulating layer bonded to the end of the circuit electrode, and a dielectric layer provided on either the circuit electrode or the insulating layer adjacent to the bonding surface of the circuit electrode and the insulating layer. is there.
  • an insulating resin is applied to an insulating substrate on which circuit electrodes are formed, starting from the ends of the circuit electrodes, and the ends are joined to the ends of the circuit electrodes.
  • the first step of forming the insulating layer, and the dielectric layer straddling the circuit electrode and the insulating layer so as to cover the bonding surface of the circuit electrode and the insulating layer are formed following the first step.
  • a second step is included.
  • the insulating layer provided along the periphery of the circuit electrode on the insulating substrate, and the circuit electrode and the insulating layer so as to cover the bonding surface of the circuit electrode and the insulating layer.
  • an insulating layer provided along the periphery of the circuit electrode on the insulating substrate, and a dielectric provided on one of the circuit electrode and the insulating layer adjacent to the bonding surface of the circuit electrode and the insulating layer.
  • the semiconductor substrate is a substrate in which circuit electrodes are formed on an insulating substrate and one or more semiconductor elements are mounted.
  • the semiconductor module is obtained by attaching a connection terminal, a heat radiating plate, and the like to a semiconductor substrate so as to be an electronic component having a function alone.
  • the power semiconductor module is formed by forming circuit electrodes on an insulating substrate, and further mounting one or more power semiconductor elements to obtain a power semiconductor substrate, and immersing the power semiconductor substrate in a sealing resin, A connection terminal and the like are attached and packaged. Further, one or a plurality of semiconductor modules and power semiconductor modules that can be operated and used independently are referred to as a semiconductor device and a power semiconductor device, respectively.
  • the present invention relates to a semiconductor module using a normal semiconductor element having a lower withstand voltage than the power semiconductor module. Even when applied, the same effect is achieved. That is, even a semiconductor module using a normal semiconductor element may have a high electric field due to downsizing, and the application of the present invention stably suppresses electric field concentration and local discharge near the edge of the substrate. Thus, a highly reliable semiconductor module can be obtained.
  • FIG. 1 is a schematic plan view showing a power semiconductor substrate on which the power semiconductor element according to Embodiment 1 of the present invention is mounted.
  • 2 is a schematic cross-sectional view showing the power semiconductor module according to the first embodiment, and
  • FIG. 3 is an enlarged cross-sectional view showing an end portion of the power semiconductor module according to the first embodiment.
  • symbol is attached
  • the power semiconductor substrate 1 has a circuit electrode 2 a on which a circuit pattern is formed on the surface of the insulating substrate 3.
  • a circuit electrode 2b (not shown in FIG. 1) is formed on the back surface of the insulating substrate 3.
  • four power semiconductor elements 4 are mounted on the circuit electrode 2a.
  • the insulating substrate 3 is made of aluminum nitride, which is an insulating ceramic, and the circuit electrodes 2a and 2b are formed of copper foil.
  • the power semiconductor module 5 is attached to the heat radiating metal base substrate 7 made of aluminum by solder 6 and the power semiconductor substrate 1 is covered with a case 8 made of resin.
  • the power semiconductor substrate 1 is dipped in an insulating sealing material 9 made of silicone gel.
  • connection terminal (not shown) for connecting the power semiconductor substrate 1 to an external circuit is taken out of the case 8 in advance, and this connection terminal is connected to another electronic circuit or the like. Since the power semiconductor element 4 is mounted on the circuit electrode 2 a formed on the surface of the insulating substrate 3, a high voltage is applied according to the operation of the power semiconductor element 4. On the other hand, since the circuit electrode 2b formed on the back surface of the insulating substrate 3 is connected to the metal base substrate 7 via the solder 6, it is electrically connected to the metal base substrate 7 and has the same potential.
  • FIG. 3 is an enlarged cross-sectional view in which the region within the dotted frame indicated by A in FIG. 2 is enlarged.
  • the insulating layer 10 made of silicone rubber is provided on the insulating substrate 3 along the periphery of the circuit electrode 2a.
  • a dielectric layer 11 made of an inorganic material having a dielectric constant higher than that of the insulator layer 10 is provided on the insulator layer 10.
  • ceramic such as aluminum nitride is used as the dielectric layer 11 (note that the insulator layer 10 and the dielectric layer 11 are not shown in FIG. 2).
  • the insulator layer 10 has the same thickness as the end of the circuit electrode 2a, and is joined to the end of the circuit electrode 2a without a step.
  • the dielectric layer 11 is provided across the circuit electrode 2a and the insulator layer 10 so as to cover the joint surface between the circuit electrode 2a and the insulator layer 10.
  • the dielectric layer 11 may be disposed only on one of the circuit electrode 2a and the insulator layer 10 adjacent to the joint surface between the circuit electrode 2a and the insulator layer 10. However, it is desirable to arrange the circuit electrode 2a and the insulator layer 10 so as to obtain a higher electric field relaxation effect.
  • an insulating resin is applied on the insulating substrate 3 on which the circuit electrode 2a is formed, starting from the end of the circuit electrode 2a, and the insulating layer 10 is bonded to the end of the circuit electrode 2a.
  • a silicone resin, a urethane resin, an acrylic resin, an epoxy resin, or the like can be used as the insulating resin constituting the insulator layer 10.
  • the insulator layer 10 is formed so as not to include voids that cause partial discharge deterioration.
  • the dielectric layer 11 is formed after applying the insulating resin on the insulating substrate 3 starting from the end of the circuit electrode 2a, there is no problem in the application of the insulating resin, and there is no void. It is possible to easily form the insulator layer 10 that does not contain.
  • the dielectric layer 11 straddling the circuit electrode 2a and the insulator layer 10 is formed so as to cover the bonding surface between the circuit electrode 2a and the insulator layer 10 (second step).
  • This second step is performed before the insulating resin applied in the first step is cured, and the dielectric layer 11 is bonded and fixed to the insulating layer 10 by curing the insulating resin. .
  • the height of the insulating resin before curing is slightly higher than the height of the circuit electrode 2a so as not to cause a step on the joint surface between the circuit electrode 2a and the insulator layer 10, and further on the circuit electrode 2a.
  • the insulating resin is applied to the extent that the dielectric layer 11 is placed. Subsequently, after the dielectric layer 11 is adhered by pressing from above, the insulating resin, that is, the insulating layer 10 is cured.
  • the circuit electrode 2b on the back surface side of the semiconductor substrate 1 is grounded via the solder 6 and the metal base substrate 7, and a voltage of 1 kV is applied to the circuit electrode 2a.
  • the electric field strength at the circuit electrode end 12 (indicated by white circles in FIGS. 3 and 4), which is the end of the circuit electrode 2a in contact with 10, was obtained by electric field analysis.
  • the circuit electrode end portion 12 is a triple point where the insulating substrate 3, the circuit electrode 2a, and the insulator layer 10 are in contact with each other, and is where the electric field is most concentrated.
  • the insulating substrate 3 aluminum nitride having a thickness of 0.6 mm and a relative dielectric constant of about 9 was used as the insulating substrate 3, and aluminum nitride having a thickness of 0.5 mm and a relative dielectric constant of about 9 was used as the dielectric layer 11.
  • the thickness of the dielectric layer 11 is changed in the third analysis, and the material of the dielectric layer 11 is changed in the fourth analysis.
  • the insulator layer 10 and the insulating sealing material 9 those obtained by curing a silicone resin having a relative dielectric constant of about 3 were used. Two thicknesses of 0.2 mm and 0.4 mm were prepared for the thickness d of the circuit electrode 2 a and the insulator layer 10.
  • the thickness of the circuit electrode 2b on the back surface side is 0.4 mm, the thickness of the solder 6 is 0.1 mm, and the creeping distance from the circuit electrode end 12 of the insulating substrate 3 to the end of the insulating substrate 3 is 2 mm. .
  • the horizontal axis represents the length c (mm) of the dielectric layer 11
  • the electric field relaxation effect is obtained when the dielectric layer 11 approaches the vicinity of the end of the circuit electrode 2a. Moreover, the electric field relaxation effect becomes higher when the dielectric layer 11 is provided not only on the insulator layer 10 but also on the circuit electrode 2a. Accordingly, when the dielectric layer 11 is disposed, it is desirable that the dielectric layer 11 be placed on the circuit electrode 2a even a little.
  • the dielectric layer 11 is not so effective that it is arranged inside the end of the circuit electrode 2a.
  • the dielectric layer 11 When arranged 0.5 mm inside the end of the circuit electrode 2, about 95% of the total relaxation effect was obtained.
  • the thinner the thickness d of the circuit electrode 2a and the insulator layer 10 the larger the electric field relaxation amount.
  • the length b from the end of the circuit electrode 2a to the inner end of the dielectric layer 11 is 0.5 mm, and the dielectric from the end of the circuit electrode 2a.
  • the electric field strength of the circuit electrode end 12 was calculated when the length to the outer end of the body layer 11 was a.
  • a ⁇ 0 indicates a state in which the dielectric layer 11 is entirely disposed on the circuit electrode 2a.
  • Other conditions are the same as those in the first analysis.
  • the horizontal axis represents the length a (mm) of the dielectric layer 11, and the vertical axis represents the electric field strength (kV / mm) of the circuit electrode end portion 12.
  • the dielectric layer 11 (aluminum nitride having a thickness of 0.5 mm) is placed on the circuit electrode 2a under the structure and conditions of the power semiconductor module 5 used in these analyses. It suffices to arrange 0.5 mm and 0.5 mm on the insulator layer 10, respectively, and it is sufficient if the length (width) is 1.0 mm as a whole. Therefore, when the dielectric layer 11 is installed, a rectangular frame shape or four rod-shaped dielectric layers 11 corresponding to the ends of the circuit electrode 2a may be installed.
  • the length a of the dielectric layer 11 may be larger than the optimum length (here, 0.5 mm). However, if the length of the dielectric layer 11 exceeds the end of the insulating substrate 3, the electric field relaxation effect is reduced, and the entire substrate is reduced. Since the size is increased, the dielectric layer 11 is formed in a range not exceeding the end of the insulating substrate 3. Further, the insulating layer 10 does not necessarily have to be formed up to the end of the insulating substrate 3, and may be formed in a range where the dielectric layer 11 is provided.
  • Other conditions are the same as those in the first analysis and the second analysis.
  • the result of the third analysis is shown in FIG. In FIG. 7, the horizontal axis represents the thickness (mm) of the dielectric layer 11, and the vertical axis represents the electric field strength (kV / mm) at the circuit electrode end 12. Since the electric field distribution is affected as the thickness of the dielectric layer 11 increases, a high electric field relaxation effect is obtained.
  • the dielectric constants of the insulating sealing material 9 and the insulating layer 10 are not particularly limited, but from the viewpoint of suppressing the electric field concentration in the vicinity of the semiconductor substrate 1, the dielectric constant of the insulating layer 10 is the insulating sealing. It is preferable that the dielectric constant of the material 9 is higher. Furthermore, the dielectric constant of the dielectric layer 11 needs to be higher than that of the insulator layer 10, and the higher the dielectric constant, the higher the electric field relaxation effect.
  • a ceramic material such as alumina (relative dielectric constant: about 9 to 10) or silicon nitride (relative dielectric constant: about 8) may be used. Since these dielectric constants are close to those of aluminum nitride, the same degree of electric field relaxation effect can be obtained.
  • glass reflative dielectric constant: about 3.5 to 4
  • mica reflative dielectric constant: about 6
  • the electric field relaxation effect is higher than that of glass, but the effect is lower than that of the ceramic material.
  • zirconia (relative permittivity: 30) or titanium oxide (relative permittivity: 83) is used as a material having a high permittivity, a higher effect can be obtained.
  • the fourth analysis the same calculation as in the second analysis was performed when materials having various relative dielectric constants were used as the dielectric layer 11.
  • the conditions other than the dielectric constant of the dielectric layer 11 are the same as in the second analysis.
  • the dielectric layer 11 is disposed at the optimum position, the thickness of the dielectric layer 11 is increased, and the dielectric constant of the dielectric layer 11 is increased. And reducing the thickness of the circuit electrode 2a.
  • the dielectric constant of the dielectric layer 11 is too high, the electric field tends to concentrate on the corners of the end portions of the dielectric layer 11. Since the dielectric layer 11 is not a conductive material, it is difficult for electric discharge to occur. However, in order to suppress electric field concentration, it is desirable to perform processing for rounding corners.
  • the electric field strength at the end of the circuit electrode 2b on the back surface side of the insulating substrate 3 may be higher.
  • the electric field at the end of the circuit electrode 2b on the back surface side of the insulating substrate 3 may be higher.
  • the thickness and length a of the dielectric layer 11 may be adjusted so as not to become too large.
  • the insulating layer 10 in a region where the electric field concentration portion is present is changed into the insulating substrate 3 and the dielectric layer 11 having the same thermal expansion coefficient.
  • the structure is sandwiched.
  • the insulator layer 10 is unlikely to deform due to a difference in thermal expansion coefficient between the insulating substrate 3 and the dielectric layer 11, and defects such as peeling are unlikely to occur.
  • a circuit electrode or a high potential conductor It tends to be a high electric field at the edge.
  • Silicone gel which is the material of the insulating sealing material 9, is liable to cause defects such as peeling at corners where stress increases during high-temperature operation, and the possibility of local discharge occurring at the conductor end exposed by peeling increases.
  • the structure of the first embodiment even when the insulating sealing material 9 is peeled off, the dielectric layer 11 is exposed, so that local discharge can be suppressed.
  • the circuit electrode 2a is provided on the peripheral edge of the circuit electrode 2a on the substrate 3, and the end of the insulator layer 10 is joined to the end of the circuit electrode 2a.
  • a highly reliable semiconductor module that can alleviate electric field concentration at the circuit electrode end 12 and suppress local discharge is easily manufactured. Is possible.
  • the power semiconductor device such as an inverter or a DC / DC converter including the power semiconductor module 5 having the electric field relaxation structure according to the first embodiment can be reduced in size, and the power semiconductor element 4 can be destroyed or malfunctioned. It is possible to suppress.
  • FIG. FIG. 10 is an enlarged cross-sectional view showing an end portion of the semiconductor module according to Embodiment 2 of the present invention.
  • a step portion having a thickness smaller than that of the other portion is provided at the peripheral portion of the circuit electrode 2a, and the step portion is provided on the step portion.
  • a dielectric layer 11 is provided.
  • the surface of the end portion of the circuit electrode 2a is cut to an arbitrary depth by the length b where the dielectric layer 11 is disposed, and the thickness is reduced. is doing. Also, the thickness of the insulator layer 10 joined to the end of the circuit electrode 2a is similarly reduced. Furthermore, the dielectric layer 11 is provided on the step portion having the small thickness so as to cover the bonding surface between the circuit electrode 2a and the insulating layer 10. The dielectric layer 11 may be disposed only on one of the circuit electrode 2a and the insulator layer 10 adjacent to the joint surface between the circuit electrode 2a and the insulator layer 10, but is disposed across both. This is desirable because a higher electric field relaxation effect can be obtained.
  • the electric field relaxation effect can be further increased by reducing the thickness of the portion where the dielectric layer 11 at the end of the circuit electrode 2a is installed.
  • fine adjustment is not required for positioning when the dielectric layer 11 is placed, and the dielectric layer 11 can be easily placed at an accurate position.
  • FIG. 11 shows the arrangement of circuit electrodes on the power semiconductor substrate according to the third embodiment of the present invention (illustration of the power semiconductor element 4 is omitted).
  • FIG. 12 shows an arrangement of the insulator layers and the dielectric layers in the power semiconductor module using the power semiconductor substrate shown in FIG.
  • the first embodiment see FIG. 1
  • the example in which one circuit electrode 2a is formed on the surface of the insulating substrate 3 has been described.
  • a plurality of circuit electrodes are formed on the surface of the insulating substrate 3.
  • 2c and 2d are formed will be described.
  • an insulator layer 10 is provided along the periphery of the circuit electrodes 2c and 2d, and a dielectric is further formed thereon.
  • the body layer 11 an electric field relaxation effect can be obtained.
  • the insulator layer 10 is formed to cover the end of the circuit electrodes 2c and 2d to the end of the insulating substrate 3, and also in the region between the circuit electrode 2c and the circuit electrode 2d.
  • the insulator layer 10 is formed.
  • a dielectric layer 11 is provided over the circuit electrode 2c and the insulator layer 10 or over the circuit electrode 2d and the insulator layer 10 so as to cover the joint surface between the circuit electrodes 2c and 2d and the insulator layer 10.
  • a dielectric layer 11 is provided over the circuit electrode 2c, the insulator layer 10, and the circuit electrode 2d. Thereby, the electric field relaxation effect can be obtained also at the ends of the circuit electrode 2c and the circuit electrode 2d facing each other.
  • the dielectric layer 11 is only on one of the circuit electrode 2c (or circuit electrode 2d) and the insulator layer 10 adjacent to the joint surface between the circuit electrode 2c (or circuit electrode 2d) and the insulator layer 10. Although it may be arranged, it is desirable to arrange it over both because a higher electric field relaxation effect can be obtained.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Une couche isolante (10) constituée, par exemple, de caoutchouc de silicone est prévue sur un substrat isolant (3) le long du bord périphérique d'une électrode de circuit (2a). Une couche diélectrique (11) fabriquée à partir d'un matériau ayant une permittivité supérieure à celle de la couche isolante (10), par exemple, de nitrure d'aluminium, est disposée sur la couche isolante (10). La couche isolante (10) a la même épaisseur que la partie d'extrémité de l'électrode de circuit (2a) et est reliée, sans qu'il y ait une différence de niveau, à la partie d'extrémité de l'électrode de circuit (2a). La couche diélectrique (11) est prévue au-dessus de l'électrode de circuit (2a) et de la couche isolante (10) de manière à recouvrir la face d'assemblage entre l'électrode de circuit (2a) et la couche isolante (10).
PCT/JP2012/079910 2012-03-19 2012-11-19 Module à semi-conducteur et son procédé de fabrication WO2013140663A1 (fr)

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JP2014505966A JP5766347B2 (ja) 2012-03-19 2012-11-19 半導体モジュール及びその製造方法

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JP2012-061498 2012-03-19

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Cited By (1)

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JP2019197816A (ja) * 2018-05-10 2019-11-14 株式会社 日立パワーデバイス パワー半導体モジュール

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AT519492B1 (de) 2016-12-22 2019-03-15 Mat Center Leoben Forschung Gmbh Sensoranordnung zur Bestimmung und gegebenenfalls Messung einer Konzentration von mehreren Gasen und Verfahren zur Herstellung einer Sensoranordnung

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Publication number Priority date Publication date Assignee Title
JPH11340374A (ja) * 1998-05-28 1999-12-10 Hitachi Ltd 半導体装置
JP2000340719A (ja) * 1999-05-26 2000-12-08 Hitachi Ltd パワー半導体装置
JP2002522904A (ja) * 1998-08-05 2002-07-23 インフィネオン テクノロジース アクチエンゲゼルシャフト 高電圧モジュール用の基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340374A (ja) * 1998-05-28 1999-12-10 Hitachi Ltd 半導体装置
JP2002522904A (ja) * 1998-08-05 2002-07-23 インフィネオン テクノロジース アクチエンゲゼルシャフト 高電圧モジュール用の基板
JP2000340719A (ja) * 1999-05-26 2000-12-08 Hitachi Ltd パワー半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019197816A (ja) * 2018-05-10 2019-11-14 株式会社 日立パワーデバイス パワー半導体モジュール
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