WO2012139322A1 - Cmos图像传感器像素及其控制时序 - Google Patents

Cmos图像传感器像素及其控制时序 Download PDF

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WO2012139322A1
WO2012139322A1 PCT/CN2011/075391 CN2011075391W WO2012139322A1 WO 2012139322 A1 WO2012139322 A1 WO 2012139322A1 CN 2011075391 W CN2011075391 W CN 2011075391W WO 2012139322 A1 WO2012139322 A1 WO 2012139322A1
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pixel
column
transistor
pixels
image sensor
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PCT/CN2011/075391
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English (en)
French (fr)
Inventor
郭同辉
旷章曲
陈杰
刘志碧
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北京思比科微电子技术股份有限公司
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Priority to JP2013554778A priority Critical patent/JP5650337B2/ja
Priority to KR1020137020098A priority patent/KR20130133824A/ko
Publication of WO2012139322A1 publication Critical patent/WO2012139322A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/766—Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/779—Circuitry for scanning or addressing the pixel array

Definitions

  • the present invention relates to a CMOS image sensor, and more particularly to a CMOS image sensor pixel and its control timing.
  • CMOS Complementary Metal Oxide Semiconductor
  • the layout of the pixel structure of the CMOS image sensor in the prior art is exemplified by 4T2S. Since the structure of the pixel itself is dependent, the array generally requires a first layer of metal, and the second layer of metal and the third layer of metal serve as device interconnections. A plurality of rows of first metal or second metal wires are required between adjacent rows of pixels, and a plurality of second metal or first metal wires are required between adjacent columns of pixels.
  • the small-sized pixel sensor has a small photosensitive area and low sensitivity, so that the information transmitted under the dark light is not clear enough.
  • the dielectric height on the surface of the photodiode Si is high, affecting the incidence of light into the photodiode.
  • a plurality of metal wires between adjacent rows and adjacent column pixels result in a low metal window aperture ratio.
  • the CMOS image sensor pixel of the present invention comprises a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, and an active region:
  • four pixels are arranged into a 2 ⁇ 2 pixel array as a group of pixel units; wherein two pixels in the first column and the second column respectively share a selection transistor, a source follower transistor, a reset transistor, and an active region in the column, and One column and two columns are arranged in a back-to-back arrangement;
  • a plurality of sets of pixel units are arranged in a vertical and horizontal direction to form a two-dimensional pixel array, and adjacent rows of pixels are interconnected by a second layer of metal wiring, and the same column of pixels is interconnected by a first layer of metal wiring.
  • the arrangement of the devices of the two pixels in the first column is:
  • the selection transistor (SX1) and the source follower transistor (SF1) are located above the photodiode (PD11) of the pixel (11), and the reset transistor (RX1) is located at the photodiode (PD11) of the pixel (11) and the photodiode of the pixel (21) ( Between PD21);
  • the arrangement of the devices of the two pixels in the second column is:
  • the selection transistor (SX2) and the source follower transistor (SF2) are located under the photodiode (PD22) of the pixel (22), and the reset transistor (RX2) is located at the photodiode (PD12) of the pixel (12) and the photodiode of the pixel (22). Between (PD22);
  • the selection transistor (SX1) is located on the left side of the source follower transistor (SF1);
  • the selection transistor (SX2) is located on the right side of the source follower transistor (SF2).
  • the active region (FD1) is located between the photodiode (PD11) of the pixel (11) and the photodiode (PD21) of the pixel (21), resetting the transistor The right side of (RX1);
  • the active region (FD2) is located between the photodiode (PD12) of the pixel (12) and the photodiode (PD22) of the pixel (22), resetting the transistor On the left side of (RX2).
  • the active region (FD1) and the source follower transistor (SF1) gate are connected by a first layer metal connection;
  • the active region (FD2) and the source follower transistor (SF2) gate are connected by a first layer of metal wiring.
  • the CMOS image sensor pixel can include a pixel array composed of a plurality of sets of said pixel units.
  • the control timing of the above-described CMOS image sensor pixel of the present invention includes the CMOS image sensor pixel array row decoder timing and column controller timing.
  • the first layer metal connection is a signal output line and a column controller timing control line and a power control line;
  • the second layer metal connection is a row decoder timing output control line.
  • the CMOS image sensor pixel of the present invention is configured by 4T2S (4 transistors, 2 pixel shared selection transistors, source follower transistors, and reset transistors). 4 pixels are arranged in a 2 ⁇ 2 pixel array as a group; wherein two pixels in the first column and the second column share a selection transistor, a source follower transistor, and a reset transistor, respectively, and the first column and the second column are back to back Arrangement.
  • the CMOS image sensor pixel array of the present invention uses only the first layer of metal and the second layer of metal as interconnects for the device. Without using a third layer of metal as the device interconnect, the dielectric height on the surface of the photodiode Si (silicon) can be reduced, allowing more light to be incident on the photodiode.
  • the CMOS image sensor pixel structure and the arrangement of the transistors of the present invention are such that only two rows of the second layer of metal wires are arranged between adjacent rows of pixels, and only two columns of the first layer of metal wires are arranged between adjacent columns of pixels to realize the function. . This metal wiring structure effectively increases the metal window aperture ratio.
  • CMOS image sensor pixel array row decoder timing CMOS image sensor pixel array row decoder timing
  • column controller timing CMOS image sensor pixel array row decoder timing
  • the CMOS image sensor pixel structure of the present invention can improve the light efficiency of the small-area pixel sensor, thereby improving the sensitivity, so that the image quality of the small-area pixel image sensor can be effectively improved.
  • FIG. 1 is a schematic diagram of a 4T2S back-back structure layout composed of 4 pixels in a specific embodiment of a CMOS image sensor pixel provided by the present invention
  • FIG. 2 is a schematic diagram of a 4T2S back-to-back structure circuit composed of 4 pixels in a specific embodiment of a CMOS image sensor pixel provided by the present invention
  • FIG. 3 is a schematic diagram of a layout of a 6 x 4 pixel array in a specific embodiment of a CMOS image sensor pixel provided by the present invention
  • FIG. 4 is a schematic diagram of a 6 x 4 pixel array circuit in a specific embodiment of a CMOS image sensor pixel provided by the present invention
  • FIG. 5 is a schematic diagram of a pixel array with a row decoder and a column controller in a specific embodiment of a CMOS image sensor pixel provided by the present invention
  • FIG. 6 is a timing diagram of a row decoder timing and a column controller of a pixel array in a specific embodiment of a CMOS image sensor pixel provided by the present invention.
  • FIGS. 1 to 6 The preferred embodiment of the CMOS image sensor pixel and its control timing according to the present invention is shown in FIGS. 1 to 6 :
  • the invention includes a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, an active region, a first metal wiring and a second metal wiring.
  • the pixel 11 and the pixel 21 located in the pixel array column 1 share the selection transistor SX1, the source follower transistor SF1, the reset transistor RX1 and the active region FD1; the pixel 12 and the pixel 22 located in the pixel array column 2 share the selection transistor SX2, the source follower transistor SF2, reset transistor RX2 and active region FD2.
  • the selection transistor SX1 and the source follower transistor SF1 are located above the photodiode PD11 of the pixel 11, the reset transistor RX1 is located between the photodiode PD11 of the pixel 11 and the photodiode PD21 of the pixel 21; the selection transistor SX2 and the source follower transistor SF2 are located at the pixel 22.
  • the reset transistor RX2 is located between the photodiode PD11 of the pixel 12 and the photodiode PD11 of the pixel 22; the pixel 11 and the pixel 21 and the pixel 12 and the pixel 22 form a back-to-back structure in the horizontal direction.
  • the selection transistor SX1 is located on the left side of the source follower transistor SF1; the selection transistor SX2 is located on the right side of the source follower transistor SF2.
  • the active region FD1 is located between the photodiode PD11 of the pixel 11 and the photodiode PD21 of the pixel 21, resetting the right side of the transistor RX1; the active region FD2 is located at the photodiode PD12 of the pixel 12 and the photodiode PD22 of the pixel 22. Between the reset transistors RX2 on the left side.
  • the active region FD1 is connected to the gate of the source follower transistor SF1 with a first layer of metal lines; the active region FD2 is connected to the gate of the source follower transistor SF2 by a first layer of metal lines.
  • the first metal connection Vdd of the power supply connects the drains of SF1 and SF2.
  • the first metal connection SC1 is connected to the source of the selection transistor SX1, and the gate and the source of the reset transistor RX1; the first metal connection SC2 is connected to the source of the selection transistor SX2 and the reset transistor RX2.
  • a gate and a source; the first layer metal line SC1 and the first layer metal line SC2 are signal output lines and column controller timing control lines.
  • the second metal wiring SX is connected to the gates of the selection transistor SX1 and the selection transistor SX2.
  • the second metal wiring TX1 is connected to the gates of the charge transfer transistor TX11 and the charge transfer transistor TX12; the second metal wiring TX2 is connected to the gates of the charge transfer transistor TX21 and the charge transfer transistor TX22.
  • the second layer metal connection SX, the second layer metal connection TX1 and the second layer metal connection TX2 are row decoder timing output control lines.
  • the invention solves the problem that the sensitivity of the small area pixel of the existing image sensor is low.
  • the CMOS image sensor pixel adopts a 4T2S structure, including four pixels, and the photodiodes of the pixel 11, the pixel 12, the pixel 21, and the pixel 22 are PD11, PD12, PD21, and PD22, respectively; and TX11 and TX12 are pixels 11 respectively.
  • TX21 and TX22 are charge transfer transistors of the pixel 21 and the pixel 22, respectively;
  • SX1, SF1 and RX1 are a selection transistor of the pixel 11 and the pixel 21, a source follower transistor and a reset transistor, respectively;
  • SX2, SF2 and RX2 is a selection transistor of pixel 12 and pixel 22, a source follower transistor, and a reset transistor, respectively.
  • the pixel 11 and the pixel 21 share the transistors SX1, SF1, RX1 and the active area FD1 (Floating Diffusion), pixel 12 and pixel 22 share transistors SX2, SF2, RX2 and active region FD2; shared pixel 11 and pixel 21 and shared pixel 12 and pixel 22 form a back-to-back configuration in the horizontal direction.
  • the metal interconnect lines used by the CMOS image sensor pixels are as follows.
  • the active regions FD1 and SF1 are connected by a first layer of metal lines; the active regions FD2 and SF2 are connected by a first layer of metal lines.
  • the first metal connection of the power supply, Vdd connects the drains of SF1 and SF2.
  • the SC1 line is the first layer of metal wiring, connected to the source of SX1, connected to the gate and source of RX1, and the first metal connection of SC1 is the signal output line and also the column controller timing control line.
  • the SC2 line is the first layer of metal wiring, connected to the source of SX2, connected to the gate and source of RX2, and the first metal connection of SC2 is the signal output line and also the column controller timing control line.
  • the SX line is the second layer of metal wiring connecting the gates of SX1 and SX2;
  • the TX1 line is the second layer of metal wiring connecting the gates of TX11 and TX12;
  • the TX2 line is the second layer of metal wiring connecting TX21 and TX22 The gate.
  • the SX second layer metal connection, the TX1 second layer metal connection and the TX2 second layer metal connection are the row decoder timing output control lines.
  • the above description is a schematic diagram of four pixels forming a back-to-back layout structure.
  • the four pixels described above are recorded as a group, and the plurality of sets of back-to-back pixels are arranged in a vertical and horizontal direction to form a two-dimensional pixel array. .
  • FIG. 3 it is a schematic diagram of a 6 ⁇ 4 pixel array layout
  • FIG. 3 is a schematic diagram of a circuit corresponding to the schematic diagram of the pixel array layout shown in FIG.
  • the FD area of each pixel is connected to the gate of each corresponding source follower transistor by a first layer of metal wiring, and the power supply Vdd line uses a first layer of metal wiring; the SC1 to SC6 lines are first.
  • Layer metal wiring as a signal output line and column controller timing control line.
  • the second metal connection SX1 is connected to the gates of SX11 to SX16, the second metal connection TX1 is connected to the gates of TX11 to TX16, and the second metal connection TX2 is connected to the gates of TX21 to TX26;
  • the line SX2 is connected to the gates of the SX21 to SX26, the second metal wiring TX3 is connected to the gates of the TX31 to TX36, and the second metal wiring TX4 is connected to the gates of the TX41 to TX46.
  • this two-dimensional pixel array only two layers of metal interconnect lines are used, and there are only two rows of second layer metal lines between adjacent rows of pixels, and there are only two columns of first layer metal lines between adjacent columns of pixels.
  • the invention uses only two layers of metal and a high metal window aperture ratio, which effectively improves the sensitivity of the small area pixel sensor.
  • FIG. 5 it is a schematic diagram of a pixel array with a row decoder and a column controller.
  • the row decoder is placed on the left side of the pixel array (or on the right side of the array), the column controller is placed on top of the pixel array, and the signal readout device is placed on the bottom of the pixel array; the decoder, controller, and The position of the signal sensing device is not the only way of the present invention, and may be adjusted depending on the specific layout of the chip.
  • the schematic diagram shown in FIG. 5 details the specific positions of the array pixels, and also details the specific numbers of the decoder timing output control lines and the column controller timing control lines.
  • m and n are non-negative integers, respectively representing the pixel row and column position of the pixel array, for example, the pixel (2m+1, 2n+1) indicates that the position of the pixel is in the 2m+1th row, the 2n+1th column;
  • the connection Vdd is the power line. When the sensor is working normally, Vdd is the power supply voltage; the metal connection SC is the signal output connection and the column controller timing control line, and the metal connection SX and TX are the row decoder timing output control line. .
  • a row decoder output timing and a column controller timing diagram used in a CMOS image sensor pixel array As shown in Figure 6, A row decoder output timing and a column controller timing diagram used in a CMOS image sensor pixel array.
  • the N-type transistor gate is set to a high level, that is, the gate of the transistor is controlled.
  • the signal is set to a high level, indicating that the transistor is turned on; the gate of the N-type transistor is set to a low level, that is, the signal controlling the gate of the transistor is set to a low level, indicating that the transistor is turned off; the length of the N-type transistor is turned on, that is, the control
  • the signal of the gate of the transistor is set to a high level for a long period of time, depending on the specific operation of the sensor; when the signal reading device at the bottom of the pixel array reads the signal, the SC line is converted into a signal output line by the column controller timing control line.
  • the signal reading device reads the signal through the signal output line, and the operation of reading the pixel signal by the signal reading device is indicated by a rectangle with a diagonal line in FIG. 6. After the pixel signal is read by the signal reading device, the signal is output. The line is converted to a column controller timing control line.
  • the line rolling exposure mode is adopted, and the pixel of the 2m+1th row starts to be exposed first, then the pixel of the 2m+2 line starts to be exposed, and then the 2m+3 line, the 2m+ 4 lines; the order of the end of exposure is the same as the order in which the exposure starts; the order of reading the signals of each line of pixels is also the same as the order in which the line pixels are exposed.
  • the exposure time of each row of pixels is equal.
  • the exposure time of the line pixel starts from the first high-level falling edge of the TX signal and ends at the next high-level falling edge of the TX signal.
  • the charge stored in the pixel photodiode potential well needs to be cleared, that is, the SX signal is at a low level, and the TX signal and the SC signal are set to a high level from a low level to turn on the charge transfer transistor and the reset transistor;
  • the charge transfer transistor is turned off, and then the reset transistor is turned off, that is, the SX signal is at a low level, and the TX signal and the SC signal are successively set to a low level by the high level, at this time, the pixel photodiode Start exposure.
  • the TX signal is always low during pixel exposure. Before the end of the exposure time, it is necessary to collect the reset signal of the pixel. First, the SX signal and the TX signal are at a low level, and the SC signal is set to a high level by the low level, and the corresponding FD area of the pixel is reset to a high level, and the FD area is set. After reset to high level, the SC signal is set to low level by high level to turn off the reset transistor; then, the SC line is converted to the signal output line by the column controller control line, the TX signal is kept low, and the SX signal is low.
  • the leveling is high to turn on the selection transistor, and the signal reading device reads the signal of each pixel of the corresponding whole line through the signal output line, and stores it as signal 1; after reading signal 1, the SX signal remains High level, the signal readout device stops reading the pixel signal, and the SC line is converted from the signal output line to the column controller control line, and the SC signal is placed at a low level.
  • the SC signal is at a low level, the SX signal is at a high level, and the TX signal is set to a high level by a low level to turn on the charge transfer tube, and the photocharge in the photodiode potential well is transferred to the corresponding FD region of the pixel.
  • the charge transfer transistor is turned off, that is, the SC timing is at a low level, the SX timing is at a high level, and the TX timing is set to a low level by a high level.
  • the SC line is converted into a signal output line by the column controller control line, and the signal reading device reads the signal of each pixel of the corresponding whole line through the signal output line, and records it as signal 2; after reading signal 2
  • the signal readout device stops reading the pixel signal, the SX timing is set to a low level by the high level, and the SC line is converted from the signal output line to the column controller control line.
  • the timing control method adopted by the pixel array of the CMOS image sensor of the present invention is not the only way; for example, the signal reading device reads the same pixel signal 1 and signal 2 in the same frame through the signal output line, and can read the signal 1 first.
  • the SX timing is set to a low level to turn off the selection transistor. Before the signal 2 is read, the SX timing is set to a high level to turn on the selection transistor, and then the signal reading device reads the signal 2.
  • the photoelectric signal collected by the sensor pixel is read and recorded by the signal reading device, and the real photoelectric signal is the difference signal between the signal 1 and the signal 2.

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Description

CMOS图像传感器像素及其控制时序
本申请要求于2011年4月15日提交中国专利局、申请号为201110095448.2、发明名称为“CMOS图像传感器像素及其控制时序”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及一种CMOS图像传感器，尤其涉及一种CMOS图像传感器像素及其控制时序。
发明背景
目前，图像传感器已经广泛应用于数码相机、移动手机、医疗器械、汽车和其他应用场合。特别是CMOS（互补型金属氧化物半导体）图像传感器的快速发展，使人们对低功耗小尺寸高分辨率图像传感器有了更高的要求。
现有技术中的CMOS图像传感器像素结构的排布方式以4T2S为例，由于依赖于像素本身的结构特性，其阵列一般需要第一层金属，第二层金属和第三层金属作为器件互连线，相邻行像素间需要多行第一层金属或第二层金属连线，相邻列像素间需要多列第二层金属或第一层金属连线。
上述现有技术至少包含以下缺点：
小尺寸像素传感器的感光面积小、灵敏度低，使得传递暗光下的信息不够清晰。尤其在使用第一层金属，第二层金属和第三层金属作为器件互连线时，光电二极管Si（硅）表面上的介质高度较高，影响光线入射到光电二极管中。而相邻行和相邻列像素间的多条金属连线导致金属窗口开口率低。
发明内容
本发明的目的是提供一种较大金属窗口开口率、灵敏度高的小尺寸CMOS图像传感器像素及其控制时序。
本发明的目的是通过以下技术方案实现的：
本发明的CMOS图像传感器像素，包括光电二极管、电荷传输晶体管、选择晶体管、源跟随晶体管、复位晶体管、有源区：
具体由4个像素排列成2X2像素阵列作为一组像素单元；其中第一列和第二列中的两个像素分别在列内共享选择晶体管、源跟随晶体管、复位晶体管和有源区，并且第一列和第二列以背靠背式排列；
多组像素单元在垂直和水平方向上排列成为二维像素阵列中，同邻行像素通过第二层金属连线实现器件互连，同列像素通过第一层金属连线实现器件互连。
所述第一列中的两个像素的器件的布置方式是：
选择晶体管（SX1）和源跟随晶体管（SF1）位于像素（11）的光电二极管（PD11）上方，复位晶体管（RX1）位于像素（11）的光电二极管（PD11）和像素（21）的光电二极管（PD21）之间；
所述第二列中的两个像素的器件的布置方式是：
选择晶体管（SX2）和源跟随晶体管（SF2）位于像素（22）的光电二极管（PD22）的下方，复位晶体管（RX2）位于像素（12）的光电二极管（PD12）和像素（22）的光电二极管（PD22）之间；
所述第一列中的两个像素的器件的布置方式中，选择晶体管（SX1）位于源跟随晶体管（SF1）的左侧；
所述第二列中的两个像素的器件的布置方式中，选择晶体管（SX2）位于源跟随晶体管（SF2）的右侧。
所述第一列中的两个像素的器件的布置方式中，有源区（FD1）位于像素（11）的光电二极管（PD11）和像素（21）的光电二极管（PD21）之间，复位晶体管（RX1）的右侧；
所述第二列中的两个像素的器件的布置方式中，有源区（FD2）位于像素（12）的光电二极管（PD12）和像素（22）的光电二极管（PD22）之间，复位晶体管（RX2）的左侧。
所述第一列中的两个像素的器件的布置方式中，有源区（FD1）与源跟随晶体管（SF1）栅极用第一层金属连线连接；
所述第二列中的两个像素的器件的布置方式中，有源区（FD2）与源跟随晶体管（SF2）栅极用第一层金属连线连接。
该CMOS图像传感器像素可以包括由多组所述的像素单元构成的像素阵列。
本发明的上述的CMOS图像传感器像素的控制时序，所述控制时序包括CMOS图像传感器像素阵列行译码器时序和列控制器时序。
所述第一层金属连线为信号输出线和列控制器时序控制线及电源控制线；
所述第二层金属连线为行译码器时序输出控制线。
由以上所述可以得知，本发明中CMOS图像传感器像素采用4T2S（4个晶体管，2个像素共享选择晶体管、源跟随晶体管和复位晶体管）结构。4个像素排列成2X2像素阵列作为一组；其中第一列和第二列中的两个像素分别在列内共享选择晶体管、源跟随晶体管和复位晶体管，并且第一列和第二列以背靠背式排列。
本发明CMOS图像传感器像素阵列仅使用第一层金属和第二层金属作为器件的互连线。不使用第三层金属作为器件互连线，可降低光电二极管Si（硅）表面上的介质高度，使得更多的光入射到光电二极管。本发明的CMOS图像传感器像素结构和各晶体管排布方式使得相邻行像素间仅布置两行第二层金属连线，相邻列像素间仅布置两列第一层金属连线即可实现功能。这种金属连线结构，有效提高了金属窗口开口率。
此外基于本发明的像素结构，可使用两种控制时序：CMOS图像传感器像素阵列行译码器时序和列控制器时序。
本发明的CMOS图像传感器像素结构能够提高小面积像素传感器的用光效率，从而提高灵敏度，所以可以有效提高小面积像素图像传感器的图像品质。
附图简要说明
图1是本发明提供的CMOS图像传感器像素的具体实施例中4个像素组成的4T2S背靠背结构版图示意图；
图2是本发明提供的CMOS图像传感器像素的具体实施例中4个像素组成的4T2S背靠背结构电路示意图；
图3是本发明提供的CMOS图像传感器像素的具体实施例中6 x 4像素阵列版图示意图；
图4是本发明提供的CMOS图像传感器像素的具体实施例中6 x 4像素阵列电路示意图；
图5是本发明提供的CMOS图像传感器像素的具体实施例中附有行译码器和列控制器的像素阵列示意图；
图6是本发明提供的CMOS图像传感器像素的具体实施例中像素阵列的行译码器时序和列控制器时序示意图。
实施本发明的方式
本发明所述的CMOS图像传感器像素及其控制时序，其较佳的具体实施方式如图1至图6所示：
包括光电二极管，电荷传输晶体管，选择晶体管，源跟随晶体管，复位晶体管，有源区，第一层金属连线和第二层金属连线。其中位于像素阵列列1的像素11和像素21共用选择晶体管SX1，源跟随晶体管SF1，复位晶体管RX1和有源区FD1；位于像素阵列列2的像素12和像素22共用选择晶体管SX2，源跟随晶体管SF2，复位晶体管RX2和有源区FD2。其中选择晶体管SX1和源跟随晶体管SF1位于像素11的光电二极管PD11上方，复位晶体管RX1位于像素11的光电二极管PD11和像素21的光电二极管PD21之间；选择晶体管SX2和源跟随晶体管SF2位于像素22的光电二极管PD22下方，复位晶体管RX2位于像素12的光电二极管PD11和像素22的光电二极管PD11之间；像素11和像素21与像素12和像素22在水平方向上形成背靠背式结构。
所述选择晶体管SX1位于源跟随晶体管SF1的左侧；所述选择晶体管SX2位于源跟随晶体管SF2的右侧。
所述有源区FD1位于像素11的光电二极管PD11和像素21的光电二极管PD21之间，复位晶体管RX1右侧；所述有源区FD2位于像素12的光电二极管PD12和像素22的光电二极管PD22之间，复位晶体管RX2左侧。
所述有源区FD1与源跟随晶体管SF1栅极用第一层金属线连接；所述有源区FD2与源跟随晶体管SF2栅极用第一层金属线连接。
所述电源第一层金属连线Vdd，连接SF1和SF2的漏极。
所述第一层金属连线SC1，连接选择晶体管SX1的源极，复位晶体管RX1的栅极和源极；所述第一层金属连线SC2，连接选择晶体管SX2的源极和复位晶体管RX2的栅极和源极；所述第一层金属连线SC1和第一层金属连线SC2为信号输出线和列控制器时序控制线。
所述第二层金属连线SX，连接选择晶体管SX1和选择晶体管SX2的栅极。
所述第二层金属连线TX1,连接电荷传输晶体管TX11和电荷传输晶体管TX12的栅极；所述第二层金属连线TX2，连接电荷传输晶体管TX21和电荷传输晶体管TX22的栅极。
所述第二层金属连线SX，第二层金属连线TX1和第二层金属连线TX2为行译码器时序输出控制线。
本发明解决现有图像传感器小面积像素灵敏度低的问题。
具体实施例一：
如图1所示，CMOS图像传感器像素采用4T2S结构，包括四个像素，像素11、像素12、像素21和像素22的光电二极管分别为PD11、PD12、PD21、PD22；TX11和TX12分别是像素11和像素12的电荷传输晶体管，TX21和TX22分别是像素21和像素22的电荷传输晶体管；SX1、SF1和RX1分别是像素11和像素21的选择晶体管、源跟随晶体管和复位晶体管；SX2、SF2和RX2分别是像素12和像素22的选择晶体管、源跟随晶体管和复位晶体管。像素11和像素21共享晶体管SX1、SF1、RX1和有源区FD1（Floating Diffusion），像素12和像素22共享晶体管SX2、SF2、RX2和有源区FD2；共享的像素11和像素21与共享的像素12和像素22在水平方向上形成背靠背式结构。
CMOS图像传感器像素使用的金属互连线表述如下。有源区FD1与SF1栅极用第一层金属线连接；有源区FD2与SF2栅极用第一层金属线连接。电源第一层金属连线Vdd，连接SF1和SF2的漏极。SC1线为第一层金属连线，连接SX1的源极，连接RX1的栅极和源极，SC1第一层金属连线即为信号输出线也为列控制器时序控制线。SC2线为第一层金属连线，连接SX2的源极，连接RX2的栅极和源极，SC2第一层金属连线即为信号输出线也为列控制器时序控制线。SX线为第二层金属连线，连接SX1和SX2的栅极；TX1线为第二层金属连线，连接TX11和TX12的栅极；TX2线为第二层金属连线，连接TX21和TX22的栅极。SX第二层金属连线、TX1第二层金属连线和TX2第二层金属连线都为行译码器时序输出控制线。
如图2所示，上面所述的是四个像素组成背靠背式版图结构示意图，上面所述的四个像素记为一组，多组背靠背式像素在垂直和水平方向上排列成为二维像素阵列。
具体实施例二：
如图3所示，为6 X 4像素阵列版图示意图；图3所示像素阵列版图示意图所对应的电路示意图如图4所示。
图3和图4所示像素阵列中，各像素FD区与各相应源跟随晶体管栅极用第一层金属连线相连，电源Vdd线使用第一层金属连线；SC1～SC6线为第一层金属连线，作为信号输出线和列控制器时序控制线。第二层金属连线SX1连接SX11～SX16的栅极，第二层金属连线TX1连接TX11～TX16的栅极，第二层金属连线TX2连接TX21～TX26的栅极；第二层金属连线SX2连接SX21～SX26的栅极，第二层金属连线TX3连接TX31～TX36的栅极，第二层金属连线TX4连接TX41～TX46的栅极。此二维像素阵列中，仅使用了两层金属互连线，相邻行像素间仅有两行第二层金属连线，相邻列像素间仅有两列第一层金属连线。本发明仅两层金属的使用及高金属窗口开口率，有效提高了小面积像素传感器的灵敏度。
具体实施例三：
CMOS图像传感器像素阵列信号采集细节表述如下：
如图5所示，为附有行译码器和列控制器的像素阵列示意图。行译码器放在像素阵列的左侧（也可以放到阵列的右侧），列控制器放于像素阵列的顶部，信号读出器件放于像素阵列的底部；译码器、控制器和信号读出器件的位置并非本发明唯一方式，也可以根据芯片的具体设计布局情况而有所调整。图5所示的示意图，详细标注了阵列像素的具***置，也详细标注了译码器时序输出控制线和列控制器时序控制线的具体编号。m和n为非负整数，分别表征像素阵列的像素行和列位置，例如像素（2m+1,2n+1）表示此像素的位置是处于第2m+1行，第2n+1列；金属连线Vdd为电源线，传感器正常工作时，Vdd为电源电压；金属连线SC为信号输出连线也为列控制器时序控制线，金属连线SX和TX为行译码器时序输出控制线。
如图6所示，为 CMOS图像传感器像素阵列所采用的行译码器输出时序和列控制器时序示意图，本发明像素阵列中，全部采用N型晶体管，N型晶体管栅极置为高电平，即控制此晶体管栅极的信号置为高电平，表示开启晶体管；N型晶体管栅极置为低电平，即控制此晶体管栅极的信号置为低电平，表明关闭晶体管；N型晶体管开启时间长短，即控制此晶体管栅极的信号置为高电平时间长短，由传感器工作具体情况而定；像素阵列底部的信号读出器件读取信号时，SC线由列控制器时序控制线转换为信号输出线，信号读出器件通过信号输出线读取信号，在图6中以带有对角线的矩形表示信号读出器件读取像素信号的操作，像素信号被信号读出器件读取完毕后，信号输出线转换为列控制器时序控制线。
本发明CMOS图像传感器像素阵列正常工作时，采用行滚动式曝光方式，第2m+1行像素首先开始曝光，然后第2m+2行像素开始曝光，再然后是第2m+3行，第2m+4行；曝光结束的顺序与曝光开始的顺序相同；每行像素的信号读取顺序也与行像素曝光开始的顺序相同。传感器采集同一帧像素阵列信号时，每行像素的曝光时间相等。
下面针对一行像素的时序控制做详细说明。行像素的曝光时间是从TX信号第一个高电平下降沿开始，至TX信号下一个高电平下降沿结束。曝光时间开始前，在像素光电二极管势井中存放的电荷需要被清除，即SX信号处于低电平，TX信号和SC信号由低电平置为高电平开启电荷传输晶体管和复位晶体管；像素光电二极管势井中存放的电荷清除后，先关闭电荷传输晶体管，然后关闭复位晶体管，即SX信号处于低电平，将TX信号和SC信号由高电平先后置为低电平，此时像素光电二极管开始曝光。像素曝光过程中，TX信号始终处于低电平。曝光时间结束前，需要采集像素的复位信号，首先，SX信号和TX信号处于低电平，SC信号由低电平置为高电平，把像素相应FD区复位为高电平，把FD区复位为高电平后SC信号由高电平置为低电平，关闭复位晶体管；然后，SC线由列控制器控制线转换为信号输出线，TX信号保持低电平，SX信号由低电平置为高电平开启选择晶体管，并通过信号输出线，由信号读出器件读取相应整行每个像素的信号，并储存下来，记为信号1；读取信号1后，SX信号保持高电平，信号读出器件停止读取像素信号，SC线由信号输出线转换为列控制器控制线，并将SC信号置于低电平。SC信号处于低电平，SX信号处于高电平，TX信号由低电平置为高电平开启电荷传输管，光电二极管势井中的光电电荷转移到像素相应FD区。像素光电二极管势井中的光电电荷转移到像素相应FD区完毕后，关闭电荷传输晶体管，即SC时序处于低电平，SX时序处于高电平，TX时序由高电平置为低电平，曝光时间结束；然后，SC线由列控制器控制线转换为信号输出线，通过信号输出线，由信号读出器件读取相应整行每个像素的信号，记为信号2；读取信号2后，信号读出器件停止读取像素信号，SX时序由高电平置为低电平，SC线由信号输出线转换为列控制器控制线。
本发明CMOS图像传感器像素阵列所采用的时序控制方式，并非唯一方式；例如，信号读出器件通过信号输出线先后读取同一帧同一像素信号1和信号2过程中，可以读取信号1后先将SX时序由高电平置为低电平关闭选择晶体管，在读取信号2前再将SX时序由低电平置为高电平打开选择晶体管，而后由信号读出器件读取信号2。由传感器像素所搜集的光电信号，被信号读出器件读取并记录下来，真实的光电信号为信号1与信号2的差值信号。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明披露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求书的保护范围为准。

Claims (10)

  1. 一种CMOS图像传感器像素，包括光电二极管、电荷传输晶体管、选择晶体管、源跟随晶体管、复位晶体管、有源区，其特征在于：
    由4个像素排列成2X2像素阵列作为一组像素单元，其中第一列和第二列中的两个像素分别在列内共享选择晶体管、源跟随晶体管、复位晶体管和有源区，并且第一列和第二列以背靠背式排列；
    多组像素单元在垂直和水平方向上排列成为二维像素阵列中，同行像素通过第二层金属连线实现器件互连，同列像素通过第一层金属连线实现器件互连。
  2. 根据权利要求1所述的CMOS图像传感器像素，其特征在于：
    所述第一列中的两个像素的器件的布置方式是：
    选择晶体管（SX1）和源跟随晶体管（SF1）位于像素（11）的光电二极管（PD11）上方，复位晶体管（RX1）位于像素（11）的光电二极管（PD11）和像素（21）的光电二极管（PD21）之间；
    所述第二列中的两个像素的器件的布置方式是：
    选择晶体管（SX2）和源跟随晶体管（SF2）位于像素（22）的光电二极管（PD22）的下方，复位晶体管（RX2）位于像素（12）的光电二极管（PD12）和像素（22）的光电二极管（PD22）之间。
  3. 根据权利要求2所述的CMOS图像传感器像素，其特征在于：
    所述第一列中的两个像素的器件的布置方式中，选择晶体管（SX1）位于源跟随晶体管（SF1）的左侧；
    所述第二列中的两个像素的器件的布置方式中，选择晶体管（SX2）位于源跟随晶体管（SF2）的右侧。
  4. 根据权利要求3所述的CMOS图像传感器像素，其特征在于：
    所述第一列中的两个像素的器件的布置方式中，有源区（FD1）位于像素（11）的光电二极管（PD11）和像素（21）的光电二极管（PD21）之间，复位晶体管（RX1）的右侧；
    所述第二列中的两个像素的器件的布置方式中，有源区（FD2）位于像素（12）的光电二极管（PD12）和像素（22）的光电二极管（PD22）之间，复位晶体管（RX2）的左侧。
  5. 根据权利要求4所述的CMOS图像传感器像素，其特征在于：
    所述第一列中的两个像素的器件的布置方式中，有源区（FD1）与源跟随晶体管（SF1）栅极用第一层金属连线连接；
    所述第二列中的两个像素的器件的布置方式中，有源区（FD2）与源跟随晶体管（SF2）栅极用第一层金属连线连接。
  6. 根据权利要求1至5任一项所述的CMOS图像传感器像素，其特征在于：
    该CMOS图像传感器像素包括由多组所述的像素单元构成的像素阵列。
  7. 一种权利要求1至5任一项所述的CMOS图像传感器像素的控制时序，其特征在于：
    所述控制时序包括CMOS图像传感器像素阵列行译码器时序和列控制器时序。
  8. 根据权利要求7所述的CMOS图像传感器像素的控制时序，其特征在于：
    所述第一层金属连线为信号输出线和列控制器时序控制线；
    所述第二层金属连线为行译码器时序输出控制线。
  9. 一种权利要求6所述的CMOS图像传感器像素的控制时序，其特征在于：
    所述控制时序包括CMOS图像传感器像素阵列行译码器时序和列控制器时序。
  10. 根据权利要求9所述的CMOS图像传感器像素的控制时序，其特征在于：
    所述第一层金属连线为信号输出线和列控制器时序控制线；
    所述第二层金属连线为行译码器时序输出控制线。
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