WO2012139322A1 - Cmos图像传感器像素及其控制时序 - Google Patents
Cmos图像传感器像素及其控制时序 Download PDFInfo
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- WO2012139322A1 WO2012139322A1 PCT/CN2011/075391 CN2011075391W WO2012139322A1 WO 2012139322 A1 WO2012139322 A1 WO 2012139322A1 CN 2011075391 W CN2011075391 W CN 2011075391W WO 2012139322 A1 WO2012139322 A1 WO 2012139322A1
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- 239000002184 metal Substances 0.000 claims abstract description 82
- 230000035945 sensitivity Effects 0.000 abstract description 6
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- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
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- 230000001419 dependent effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/766—Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/779—Circuitry for scanning or addressing the pixel array
Definitions
- the present invention relates to a CMOS image sensor, and more particularly to a CMOS image sensor pixel and its control timing.
- CMOS Complementary Metal Oxide Semiconductor
- the layout of the pixel structure of the CMOS image sensor in the prior art is exemplified by 4T2S. Since the structure of the pixel itself is dependent, the array generally requires a first layer of metal, and the second layer of metal and the third layer of metal serve as device interconnections. A plurality of rows of first metal or second metal wires are required between adjacent rows of pixels, and a plurality of second metal or first metal wires are required between adjacent columns of pixels.
- the small-sized pixel sensor has a small photosensitive area and low sensitivity, so that the information transmitted under the dark light is not clear enough.
- the dielectric height on the surface of the photodiode Si is high, affecting the incidence of light into the photodiode.
- a plurality of metal wires between adjacent rows and adjacent column pixels result in a low metal window aperture ratio.
- the CMOS image sensor pixel of the present invention comprises a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, and an active region:
- four pixels are arranged into a 2 ⁇ 2 pixel array as a group of pixel units; wherein two pixels in the first column and the second column respectively share a selection transistor, a source follower transistor, a reset transistor, and an active region in the column, and One column and two columns are arranged in a back-to-back arrangement;
- a plurality of sets of pixel units are arranged in a vertical and horizontal direction to form a two-dimensional pixel array, and adjacent rows of pixels are interconnected by a second layer of metal wiring, and the same column of pixels is interconnected by a first layer of metal wiring.
- the arrangement of the devices of the two pixels in the first column is:
- the selection transistor (SX1) and the source follower transistor (SF1) are located above the photodiode (PD11) of the pixel (11), and the reset transistor (RX1) is located at the photodiode (PD11) of the pixel (11) and the photodiode of the pixel (21) ( Between PD21);
- the arrangement of the devices of the two pixels in the second column is:
- the selection transistor (SX2) and the source follower transistor (SF2) are located under the photodiode (PD22) of the pixel (22), and the reset transistor (RX2) is located at the photodiode (PD12) of the pixel (12) and the photodiode of the pixel (22). Between (PD22);
- the selection transistor (SX1) is located on the left side of the source follower transistor (SF1);
- the selection transistor (SX2) is located on the right side of the source follower transistor (SF2).
- the active region (FD1) is located between the photodiode (PD11) of the pixel (11) and the photodiode (PD21) of the pixel (21), resetting the transistor The right side of (RX1);
- the active region (FD2) is located between the photodiode (PD12) of the pixel (12) and the photodiode (PD22) of the pixel (22), resetting the transistor On the left side of (RX2).
- the active region (FD1) and the source follower transistor (SF1) gate are connected by a first layer metal connection;
- the active region (FD2) and the source follower transistor (SF2) gate are connected by a first layer of metal wiring.
- the CMOS image sensor pixel can include a pixel array composed of a plurality of sets of said pixel units.
- the control timing of the above-described CMOS image sensor pixel of the present invention includes the CMOS image sensor pixel array row decoder timing and column controller timing.
- the first layer metal connection is a signal output line and a column controller timing control line and a power control line;
- the second layer metal connection is a row decoder timing output control line.
- the CMOS image sensor pixel of the present invention is configured by 4T2S (4 transistors, 2 pixel shared selection transistors, source follower transistors, and reset transistors). 4 pixels are arranged in a 2 ⁇ 2 pixel array as a group; wherein two pixels in the first column and the second column share a selection transistor, a source follower transistor, and a reset transistor, respectively, and the first column and the second column are back to back Arrangement.
- the CMOS image sensor pixel array of the present invention uses only the first layer of metal and the second layer of metal as interconnects for the device. Without using a third layer of metal as the device interconnect, the dielectric height on the surface of the photodiode Si (silicon) can be reduced, allowing more light to be incident on the photodiode.
- the CMOS image sensor pixel structure and the arrangement of the transistors of the present invention are such that only two rows of the second layer of metal wires are arranged between adjacent rows of pixels, and only two columns of the first layer of metal wires are arranged between adjacent columns of pixels to realize the function. . This metal wiring structure effectively increases the metal window aperture ratio.
- CMOS image sensor pixel array row decoder timing CMOS image sensor pixel array row decoder timing
- column controller timing CMOS image sensor pixel array row decoder timing
- the CMOS image sensor pixel structure of the present invention can improve the light efficiency of the small-area pixel sensor, thereby improving the sensitivity, so that the image quality of the small-area pixel image sensor can be effectively improved.
- FIG. 1 is a schematic diagram of a 4T2S back-back structure layout composed of 4 pixels in a specific embodiment of a CMOS image sensor pixel provided by the present invention
- FIG. 2 is a schematic diagram of a 4T2S back-to-back structure circuit composed of 4 pixels in a specific embodiment of a CMOS image sensor pixel provided by the present invention
- FIG. 3 is a schematic diagram of a layout of a 6 x 4 pixel array in a specific embodiment of a CMOS image sensor pixel provided by the present invention
- FIG. 4 is a schematic diagram of a 6 x 4 pixel array circuit in a specific embodiment of a CMOS image sensor pixel provided by the present invention
- FIG. 5 is a schematic diagram of a pixel array with a row decoder and a column controller in a specific embodiment of a CMOS image sensor pixel provided by the present invention
- FIG. 6 is a timing diagram of a row decoder timing and a column controller of a pixel array in a specific embodiment of a CMOS image sensor pixel provided by the present invention.
- FIGS. 1 to 6 The preferred embodiment of the CMOS image sensor pixel and its control timing according to the present invention is shown in FIGS. 1 to 6 :
- the invention includes a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, an active region, a first metal wiring and a second metal wiring.
- the pixel 11 and the pixel 21 located in the pixel array column 1 share the selection transistor SX1, the source follower transistor SF1, the reset transistor RX1 and the active region FD1; the pixel 12 and the pixel 22 located in the pixel array column 2 share the selection transistor SX2, the source follower transistor SF2, reset transistor RX2 and active region FD2.
- the selection transistor SX1 and the source follower transistor SF1 are located above the photodiode PD11 of the pixel 11, the reset transistor RX1 is located between the photodiode PD11 of the pixel 11 and the photodiode PD21 of the pixel 21; the selection transistor SX2 and the source follower transistor SF2 are located at the pixel 22.
- the reset transistor RX2 is located between the photodiode PD11 of the pixel 12 and the photodiode PD11 of the pixel 22; the pixel 11 and the pixel 21 and the pixel 12 and the pixel 22 form a back-to-back structure in the horizontal direction.
- the selection transistor SX1 is located on the left side of the source follower transistor SF1; the selection transistor SX2 is located on the right side of the source follower transistor SF2.
- the active region FD1 is located between the photodiode PD11 of the pixel 11 and the photodiode PD21 of the pixel 21, resetting the right side of the transistor RX1; the active region FD2 is located at the photodiode PD12 of the pixel 12 and the photodiode PD22 of the pixel 22. Between the reset transistors RX2 on the left side.
- the active region FD1 is connected to the gate of the source follower transistor SF1 with a first layer of metal lines; the active region FD2 is connected to the gate of the source follower transistor SF2 by a first layer of metal lines.
- the first metal connection Vdd of the power supply connects the drains of SF1 and SF2.
- the first metal connection SC1 is connected to the source of the selection transistor SX1, and the gate and the source of the reset transistor RX1; the first metal connection SC2 is connected to the source of the selection transistor SX2 and the reset transistor RX2.
- a gate and a source; the first layer metal line SC1 and the first layer metal line SC2 are signal output lines and column controller timing control lines.
- the second metal wiring SX is connected to the gates of the selection transistor SX1 and the selection transistor SX2.
- the second metal wiring TX1 is connected to the gates of the charge transfer transistor TX11 and the charge transfer transistor TX12; the second metal wiring TX2 is connected to the gates of the charge transfer transistor TX21 and the charge transfer transistor TX22.
- the second layer metal connection SX, the second layer metal connection TX1 and the second layer metal connection TX2 are row decoder timing output control lines.
- the invention solves the problem that the sensitivity of the small area pixel of the existing image sensor is low.
- the CMOS image sensor pixel adopts a 4T2S structure, including four pixels, and the photodiodes of the pixel 11, the pixel 12, the pixel 21, and the pixel 22 are PD11, PD12, PD21, and PD22, respectively; and TX11 and TX12 are pixels 11 respectively.
- TX21 and TX22 are charge transfer transistors of the pixel 21 and the pixel 22, respectively;
- SX1, SF1 and RX1 are a selection transistor of the pixel 11 and the pixel 21, a source follower transistor and a reset transistor, respectively;
- SX2, SF2 and RX2 is a selection transistor of pixel 12 and pixel 22, a source follower transistor, and a reset transistor, respectively.
- the pixel 11 and the pixel 21 share the transistors SX1, SF1, RX1 and the active area FD1 (Floating Diffusion), pixel 12 and pixel 22 share transistors SX2, SF2, RX2 and active region FD2; shared pixel 11 and pixel 21 and shared pixel 12 and pixel 22 form a back-to-back configuration in the horizontal direction.
- the metal interconnect lines used by the CMOS image sensor pixels are as follows.
- the active regions FD1 and SF1 are connected by a first layer of metal lines; the active regions FD2 and SF2 are connected by a first layer of metal lines.
- the first metal connection of the power supply, Vdd connects the drains of SF1 and SF2.
- the SC1 line is the first layer of metal wiring, connected to the source of SX1, connected to the gate and source of RX1, and the first metal connection of SC1 is the signal output line and also the column controller timing control line.
- the SC2 line is the first layer of metal wiring, connected to the source of SX2, connected to the gate and source of RX2, and the first metal connection of SC2 is the signal output line and also the column controller timing control line.
- the SX line is the second layer of metal wiring connecting the gates of SX1 and SX2;
- the TX1 line is the second layer of metal wiring connecting the gates of TX11 and TX12;
- the TX2 line is the second layer of metal wiring connecting TX21 and TX22 The gate.
- the SX second layer metal connection, the TX1 second layer metal connection and the TX2 second layer metal connection are the row decoder timing output control lines.
- the above description is a schematic diagram of four pixels forming a back-to-back layout structure.
- the four pixels described above are recorded as a group, and the plurality of sets of back-to-back pixels are arranged in a vertical and horizontal direction to form a two-dimensional pixel array. .
- FIG. 3 it is a schematic diagram of a 6 ⁇ 4 pixel array layout
- FIG. 3 is a schematic diagram of a circuit corresponding to the schematic diagram of the pixel array layout shown in FIG.
- the FD area of each pixel is connected to the gate of each corresponding source follower transistor by a first layer of metal wiring, and the power supply Vdd line uses a first layer of metal wiring; the SC1 to SC6 lines are first.
- Layer metal wiring as a signal output line and column controller timing control line.
- the second metal connection SX1 is connected to the gates of SX11 to SX16, the second metal connection TX1 is connected to the gates of TX11 to TX16, and the second metal connection TX2 is connected to the gates of TX21 to TX26;
- the line SX2 is connected to the gates of the SX21 to SX26, the second metal wiring TX3 is connected to the gates of the TX31 to TX36, and the second metal wiring TX4 is connected to the gates of the TX41 to TX46.
- this two-dimensional pixel array only two layers of metal interconnect lines are used, and there are only two rows of second layer metal lines between adjacent rows of pixels, and there are only two columns of first layer metal lines between adjacent columns of pixels.
- the invention uses only two layers of metal and a high metal window aperture ratio, which effectively improves the sensitivity of the small area pixel sensor.
- FIG. 5 it is a schematic diagram of a pixel array with a row decoder and a column controller.
- the row decoder is placed on the left side of the pixel array (or on the right side of the array), the column controller is placed on top of the pixel array, and the signal readout device is placed on the bottom of the pixel array; the decoder, controller, and The position of the signal sensing device is not the only way of the present invention, and may be adjusted depending on the specific layout of the chip.
- the schematic diagram shown in FIG. 5 details the specific positions of the array pixels, and also details the specific numbers of the decoder timing output control lines and the column controller timing control lines.
- m and n are non-negative integers, respectively representing the pixel row and column position of the pixel array, for example, the pixel (2m+1, 2n+1) indicates that the position of the pixel is in the 2m+1th row, the 2n+1th column;
- the connection Vdd is the power line. When the sensor is working normally, Vdd is the power supply voltage; the metal connection SC is the signal output connection and the column controller timing control line, and the metal connection SX and TX are the row decoder timing output control line. .
- a row decoder output timing and a column controller timing diagram used in a CMOS image sensor pixel array As shown in Figure 6, A row decoder output timing and a column controller timing diagram used in a CMOS image sensor pixel array.
- the N-type transistor gate is set to a high level, that is, the gate of the transistor is controlled.
- the signal is set to a high level, indicating that the transistor is turned on; the gate of the N-type transistor is set to a low level, that is, the signal controlling the gate of the transistor is set to a low level, indicating that the transistor is turned off; the length of the N-type transistor is turned on, that is, the control
- the signal of the gate of the transistor is set to a high level for a long period of time, depending on the specific operation of the sensor; when the signal reading device at the bottom of the pixel array reads the signal, the SC line is converted into a signal output line by the column controller timing control line.
- the signal reading device reads the signal through the signal output line, and the operation of reading the pixel signal by the signal reading device is indicated by a rectangle with a diagonal line in FIG. 6. After the pixel signal is read by the signal reading device, the signal is output. The line is converted to a column controller timing control line.
- the line rolling exposure mode is adopted, and the pixel of the 2m+1th row starts to be exposed first, then the pixel of the 2m+2 line starts to be exposed, and then the 2m+3 line, the 2m+ 4 lines; the order of the end of exposure is the same as the order in which the exposure starts; the order of reading the signals of each line of pixels is also the same as the order in which the line pixels are exposed.
- the exposure time of each row of pixels is equal.
- the exposure time of the line pixel starts from the first high-level falling edge of the TX signal and ends at the next high-level falling edge of the TX signal.
- the charge stored in the pixel photodiode potential well needs to be cleared, that is, the SX signal is at a low level, and the TX signal and the SC signal are set to a high level from a low level to turn on the charge transfer transistor and the reset transistor;
- the charge transfer transistor is turned off, and then the reset transistor is turned off, that is, the SX signal is at a low level, and the TX signal and the SC signal are successively set to a low level by the high level, at this time, the pixel photodiode Start exposure.
- the TX signal is always low during pixel exposure. Before the end of the exposure time, it is necessary to collect the reset signal of the pixel. First, the SX signal and the TX signal are at a low level, and the SC signal is set to a high level by the low level, and the corresponding FD area of the pixel is reset to a high level, and the FD area is set. After reset to high level, the SC signal is set to low level by high level to turn off the reset transistor; then, the SC line is converted to the signal output line by the column controller control line, the TX signal is kept low, and the SX signal is low.
- the leveling is high to turn on the selection transistor, and the signal reading device reads the signal of each pixel of the corresponding whole line through the signal output line, and stores it as signal 1; after reading signal 1, the SX signal remains High level, the signal readout device stops reading the pixel signal, and the SC line is converted from the signal output line to the column controller control line, and the SC signal is placed at a low level.
- the SC signal is at a low level, the SX signal is at a high level, and the TX signal is set to a high level by a low level to turn on the charge transfer tube, and the photocharge in the photodiode potential well is transferred to the corresponding FD region of the pixel.
- the charge transfer transistor is turned off, that is, the SC timing is at a low level, the SX timing is at a high level, and the TX timing is set to a low level by a high level.
- the SC line is converted into a signal output line by the column controller control line, and the signal reading device reads the signal of each pixel of the corresponding whole line through the signal output line, and records it as signal 2; after reading signal 2
- the signal readout device stops reading the pixel signal, the SX timing is set to a low level by the high level, and the SC line is converted from the signal output line to the column controller control line.
- the timing control method adopted by the pixel array of the CMOS image sensor of the present invention is not the only way; for example, the signal reading device reads the same pixel signal 1 and signal 2 in the same frame through the signal output line, and can read the signal 1 first.
- the SX timing is set to a low level to turn off the selection transistor. Before the signal 2 is read, the SX timing is set to a high level to turn on the selection transistor, and then the signal reading device reads the signal 2.
- the photoelectric signal collected by the sensor pixel is read and recorded by the signal reading device, and the real photoelectric signal is the difference signal between the signal 1 and the signal 2.
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Description
Claims (10)
- 一种CMOS图像传感器像素,包括光电二极管、电荷传输晶体管、选择晶体管、源跟随晶体管、复位晶体管、有源区,其特征在于:由4个像素排列成2X2像素阵列作为一组像素单元,其中第一列和第二列中的两个像素分别在列内共享选择晶体管、源跟随晶体管、复位晶体管和有源区,并且第一列和第二列以背靠背式排列;多组像素单元在垂直和水平方向上排列成为二维像素阵列中,同行像素通过第二层金属连线实现器件互连,同列像素通过第一层金属连线实现器件互连。
- 根据权利要求1所述的CMOS图像传感器像素,其特征在于:所述第一列中的两个像素的器件的布置方式是:选择晶体管(SX1)和源跟随晶体管(SF1)位于像素(11)的光电二极管(PD11)上方,复位晶体管(RX1)位于像素(11)的光电二极管(PD11)和像素(21)的光电二极管(PD21)之间;所述第二列中的两个像素的器件的布置方式是:选择晶体管(SX2)和源跟随晶体管(SF2)位于像素(22)的光电二极管(PD22)的下方,复位晶体管(RX2)位于像素(12)的光电二极管(PD12)和像素(22)的光电二极管(PD22)之间。
- 根据权利要求2所述的CMOS图像传感器像素,其特征在于:所述第一列中的两个像素的器件的布置方式中,选择晶体管(SX1)位于源跟随晶体管(SF1)的左侧;所述第二列中的两个像素的器件的布置方式中,选择晶体管(SX2)位于源跟随晶体管(SF2)的右侧。
- 根据权利要求3所述的CMOS图像传感器像素,其特征在于:所述第一列中的两个像素的器件的布置方式中,有源区(FD1)位于像素(11)的光电二极管(PD11)和像素(21)的光电二极管(PD21)之间,复位晶体管(RX1)的右侧;所述第二列中的两个像素的器件的布置方式中,有源区(FD2)位于像素(12)的光电二极管(PD12)和像素(22)的光电二极管(PD22)之间,复位晶体管(RX2)的左侧。
- 根据权利要求4所述的CMOS图像传感器像素,其特征在于:所述第一列中的两个像素的器件的布置方式中,有源区(FD1)与源跟随晶体管(SF1)栅极用第一层金属连线连接;所述第二列中的两个像素的器件的布置方式中,有源区(FD2)与源跟随晶体管(SF2)栅极用第一层金属连线连接。
- 根据权利要求1至5任一项所述的CMOS图像传感器像素,其特征在于:该CMOS图像传感器像素包括由多组所述的像素单元构成的像素阵列。
- 一种权利要求1至5任一项所述的CMOS图像传感器像素的控制时序,其特征在于:所述控制时序包括CMOS图像传感器像素阵列行译码器时序和列控制器时序。
- 根据权利要求7所述的CMOS图像传感器像素的控制时序,其特征在于:所述第一层金属连线为信号输出线和列控制器时序控制线;所述第二层金属连线为行译码器时序输出控制线。
- 一种权利要求6所述的CMOS图像传感器像素的控制时序,其特征在于:所述控制时序包括CMOS图像传感器像素阵列行译码器时序和列控制器时序。
- 根据权利要求9所述的CMOS图像传感器像素的控制时序,其特征在于:所述第一层金属连线为信号输出线和列控制器时序控制线;所述第二层金属连线为行译码器时序输出控制线。
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JP2013554778A JP5650337B2 (ja) | 2011-04-15 | 2011-06-07 | Cmosイメージセンサ画素およびその制御シーケンス |
KR1020137020098A KR20130133824A (ko) | 2011-04-15 | 2011-06-07 | Cmos 이미지 센서 화소 및 그의 제어 타이밍시퀀스 |
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CN102572320A (zh) * | 2011-11-28 | 2012-07-11 | 北京思比科微电子技术股份有限公司 | 降低cmos图像传感器模组高度的方法及cmos图像传感器模组 |
CN102447851B (zh) * | 2011-12-26 | 2014-07-30 | 深港产学研基地 | 高填充系数的双cmos图像传感器像素单元及工作方法 |
CN102595057B (zh) * | 2012-02-27 | 2014-09-24 | 北京思比科微电子技术股份有限公司 | Cmos图像传感器像素及其控制时序 |
CN102856339B (zh) * | 2012-09-24 | 2015-09-02 | 北京思比科微电子技术股份有限公司 | Cmos图像传感器列共享像素单元及像素阵列 |
CN102868866B (zh) * | 2012-09-24 | 2015-09-16 | 北京思比科微电子技术股份有限公司 | Cmos图像传感器列共享2×2像素单元及像素阵列 |
CN103165636B (zh) * | 2013-03-21 | 2015-10-21 | 北京思比科微电子技术股份有限公司 | Cmos图像传感器的像素单元组及cmos图像传感器 |
CN103391407B (zh) * | 2013-07-31 | 2016-08-17 | 北京思比科微电子技术股份有限公司 | 一种cmos图像传感器的像素结构及该图像传感器 |
CN103391408B (zh) * | 2013-07-31 | 2017-02-15 | 北京思比科微电子技术股份有限公司 | 一种cmos图像传感器的像素结构及该图像传感器 |
CN104465690B (zh) * | 2014-12-26 | 2018-01-26 | 上海集成电路研发中心有限公司 | 版图、像素单元结构及其制备方法 |
KR102398025B1 (ko) * | 2017-03-15 | 2022-05-17 | 에스케이하이닉스 주식회사 | 이미지 센서 |
CN112563293A (zh) * | 2019-09-10 | 2021-03-26 | 格科微电子(上海)有限公司 | Cmos图像传感器的像素结构 |
CN115308757A (zh) * | 2021-05-08 | 2022-11-08 | 宁波飞芯电子科技有限公司 | 一种图像传感器及其驱动方法 |
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JP2014507905A (ja) | 2014-03-27 |
CN102158663B (zh) | 2013-09-11 |
JP5650337B2 (ja) | 2015-01-07 |
CN102158663A (zh) | 2011-08-17 |
KR20130133824A (ko) | 2013-12-09 |
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