WO2012035888A1 - シリコンエッチング液及びそれを用いたトランジスタの製造方法 - Google Patents
シリコンエッチング液及びそれを用いたトランジスタの製造方法 Download PDFInfo
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- WO2012035888A1 WO2012035888A1 PCT/JP2011/066998 JP2011066998W WO2012035888A1 WO 2012035888 A1 WO2012035888 A1 WO 2012035888A1 JP 2011066998 W JP2011066998 W JP 2011066998W WO 2012035888 A1 WO2012035888 A1 WO 2012035888A1
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- Prior art keywords
- silicon
- etching
- dummy gate
- polyhydric alcohol
- transistor
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Definitions
- the present invention uses a structure having a dummy gate laminated body formed by laminating at least a high dielectric material film and a dummy gate made of silicon, and the dummy gate includes a metal that is hafnium, zirconium, titanium, tantalum, or tungsten.
- semiconductors have improved performance, cost, and power consumption by so-called miniaturization that reduces the gate length and gate thickness of transistors.
- the gate thickness becomes too thin in the conventional gate insulating film using silicon oxide, the leakage current due to the tunnel current increases, and the power consumption increases.
- devices that use semiconductor elements have been increasingly carried around, such as mobile phones, notebook computers, and portable music players. In this case, since electric power is often supplied from a rechargeable battery, low power consumption is required for the semiconductor element aiming at long-term use.
- Non-Patent Document 1 a technique using a high dielectric material and a metal gate as a combination of an insulating material and a gate electrode constituting a transistor instead of the conventionally used silicon oxide and polycrystalline silicon has been proposed. Invented (Non-Patent Document 1).
- FIG. 1 is a schematic cross-sectional view of a part of a transistor before removing polycrystalline silicon in a semiconductor element using a high dielectric material.
- a single wafer cleaning apparatus for cleaning silicon wafers one by one is often used to suppress particles.
- etching rate the etching amount per unit time of polycrystalline silicon
- the time required for etching becomes long and the manufacturing amount per apparatus is reduced. Therefore, a technique for etching the polycrystalline silicon in a short time without corroding the high dielectric material, metal, sidewalls and interlayer insulating film in the process of removing the polycrystalline silicon is required.
- Dry etching is known as a method for etching polycrystalline silicon (Patent Document 1).
- dry etching etches not only polycrystalline silicon but also sidewalls and interlayer insulating films.
- a protective film such as a photoresist on the sidewall and the interlayer insulating film.
- Providing the protective film complicates the manufacturing process, leading to a decrease in yield and an increase in manufacturing cost.
- the ashing process performed to remove the photoresist alters the interlayer insulating film, there is a concern that the performance of the transistor may be degraded.
- overetching is usually performed for a longer time than the time required for the etching process calculated from the etching rate in order to prevent a minute silicon residue.
- dry etching the high dielectric material exposed after silicon etching is etched or deteriorated during overetching, so that the transistor performance may be deteriorated.
- Non-patent Document 2 Various alkaline cleaning liquids are known as cleaning liquids for etching silicon by a wet etching method (Non-patent Document 2). However, since these cleaning liquids have a low silicon etch rate, the time required for etching becomes long, and the production amount per apparatus is reduced.
- Patent Document 2 As a technique for obtaining a high silicon etching rate, an etching composition containing an inorganic alkali compound and hydroxylamines has been proposed (Patent Document 2).
- alkali metal ions contained in an inorganic alkali cannot be used because they greatly deteriorate the performance of the transistor.
- etching rate of silicon As a technique for obtaining a high etching rate of silicon, it comprises at least one selected from organic alkali compounds and hydroxylamines, hypophosphites, reducing sugars, ascorbic acid, glyoxylic acid, and brentzcatechin, and their derivatives.
- An etching composition containing a reducing compound has been proposed (see Patent Document 3 and Comparative Example 3).
- Patent Document 4 proposes an alkaline stripping solution that prevents the etching of aluminum from the viewpoint of not hindering the ability to weaken the adhesive strength of the adhesive film, and mentions the polycrystalline silicon etching ability of the alkaline stripping solution. Absent. Therefore, Patent Document 4 is a technique different from the present invention aimed at obtaining a large polycrystalline silicon etch rate. Furthermore, the stripping solution that can be used in Patent Document 4 is not particularly limited as long as it is an alkaline solution. However, the compounds that exhibit alkalinity that can be used for etching polycrystalline silicon are limited. That is, it is not easy to analogize a compound suitable for the present invention based on Patent Document 4 (see Comparative Example 4).
- a material for the metal gate zirconium, titanium, tantalum, tungsten or the like is adopted in addition to the above-described aluminum.
- an etching solution suitable for these materials is not found. Accordingly, a method of manufacturing a transistor having a laminate composed of at least a high dielectric material film and the metal gate by removing a dummy gate made of silicon and replacing it with a metal gate containing hafnium, zirconium, titanium, tantalum or tungsten. Therefore, there is a strong demand for an etching solution for selectively removing the dummy gate and a method for manufacturing the transistor.
- the present invention is a method of removing a dummy gate made of silicon and replacing it with a metal gate containing hafnium, zirconium, titanium, tantalum or tungsten, and manufacturing a transistor having a laminate composed of at least a high dielectric material film and the metal gate It is an object of the present invention to provide an etching solution used for etching a dummy gate made of silicon and selectively etching the dummy gate made of silicon, and a method of manufacturing a transistor using the same. is there.
- the present inventors have found that the object can be achieved by using a specific silicon etchant for etching a dummy gate made of silicon. .
- the present invention has been completed based on such findings. That is, the gist of the present invention is as follows.
- a dummy gate laminated body formed by laminating at least a high dielectric material film and a silicon dummy gate on a substrate, a sidewall provided to cover the side surface of the laminated body, and a sidewall provided to cover the sidewall
- a dummy gate laminated body formed by laminating at least a high dielectric material film and a silicon dummy gate on a substrate, a sidewall provided to cover the side surface of the laminated body, and a sidewall provided to cover the sidewall
- 0.1 to 40% by weight of at least one alkali compound selected from ammonia, diamine, and polyamine represented by the general formula (1), a polyhydric alcohol represented by the general formula (2), Polyhydric alcohol represented by general formula (3), cyclic polyhydric alcohol represented by general formula (4) Lumpur, and reducing 0.01-40 wt% polyhydric alcohol is at least one selected from the no saccharides, and silicon etching solution containing from 40 to 99.89% by weight of water.
- the polyhydric alcohol represented by the general formulas (2) to (4) is at least one selected from ethylene glycol, glycerin, meso-erythritol, xylitol, sorbitol, propylene glycol, pentaerythritol, and inositol.
- the silicon etching liquid as described. 4). 2.
- the silicon etching solution according to 1 above, wherein the saccharide having no reducing property is sucrose, trehalose, or raffinose. 5. 2.
- the silicon etching solution according to 1 above, wherein the high dielectric material forming the high dielectric material film is HfO 2 , HfSiO, HfSiON, HfLaO, HfLaON, HfTiSiON, HfAlSiON, HfZrO, or Al 2 O 3 . 6).
- Step (I) The silicon is represented by 0.1 to 40% by weight of an alkali compound that is at least one selected from ammonia, diamine, and polyamine represented by the general formula (1), represented by the general formula (2)
- K is an integer of 2 to 5)
- L is an integer of 2 to 6, and R is hydrogen or an alkyl group.
- M is 1 or 2)
- N is an integer of 3 to 8.) 7.
- the diamine and the polyamine represented by the general formula (1) are at least one selected from ethylenediamine, 1,2-propanediamine, 1,3-propanediamine, diethylenetriamine, and triethylenetetramine.
- the polyhydric alcohol represented by the general formulas (2) to (4) is at least one selected from ethylene glycol, glycerin, meso-erythritol, xylitol, sorbitol, propylene glycol, pentaerythritol, and inositol.
- a transistor having a laminate composed of at least a high dielectric material film and the metal gate is obtained by removing a dummy gate made of silicon and replacing it with a metal gate containing hafnium, zirconium, titanium, tantalum or tungsten.
- silicon can be selectively removed, and high-precision and high-quality transistors can be manufactured with high yield.
- the silicon etchant of the present invention comprises a dummy gate laminate in which at least a high dielectric material film and a dummy gate made of silicon are laminated on a substrate, a sidewall provided so as to cover a side surface of the laminate, and the In a method for manufacturing a transistor, wherein a structure including an interlayer insulating film provided to cover a sidewall is used, and the dummy gate is replaced with a metal gate containing hafnium, zirconium, titanium, tantalum, or tungsten.
- Used for etching a dummy gate made of silicon 0.1 to 40% by weight of an alkali compound that is at least one selected from ammonia, diamine, and polyamine represented by the general formula (1),
- the polyhydric alcohol represented by (2), the polyhydric alcohol represented by the general formula (3) 0.01 to 40% by weight of at least one polyhydric alcohol selected from coal, cyclic polyhydric alcohol represented by the general formula (4), and non-reducing sugars, and water 40 to 99.89 It is a liquid containing% by weight.
- the alkali compound used in the present invention is for etching silicon, and is at least one compound selected from ammonia, diamine, and polyamine represented by the general formula (1).
- Preferred examples of the diamine include ethylenediamine, 1,2-propanediamine, and 1,3-propanediamine.
- Preferred examples of the polyamine represented by the general formula (1) include diethylenetriamine and triethylenetetramine.
- the concentration of the alkali compound in the etching solution is usually 0.1 to 40% by weight, preferably 0.2 to 40% by weight, more preferably 0.3 to 30% by weight. When the alkali compound concentration is less than 0.1% by weight or exceeds 40% by weight, an effective etch rate cannot be obtained.
- the polyhydric alcohol used in the present invention has a polyhydric alcohol represented by the general formula (2), a polyhydric alcohol represented by the general formula (3), a cyclic polyhydric alcohol represented by the general formula (4), and a reducing property. It is at least one selected from sugars that do not have.
- Specific examples of the polyhydric alcohol represented by the general formula (2) include ethylene glycol, glycerin, meso-erythritol, xylitol, sorbitol, propylene glycol and the like.
- the polyhydric alcohol represented by the general formula (3) Pentaerythritol is preferably exemplified as the alcohol, and inositol is preferably exemplified as the cyclic polyhydric alcohol represented by the general formula (4).
- Specific examples of saccharides having no reducing ability are sucrose, trehalose and raffinose. These polyhydric alcohols can be blended alone or in combination of two or more.
- the concentration of the polyhydric alcohol in the etching solution is usually 0.001 to 50% by weight, preferably 0.005 to 40% by weight, and more preferably 0.01 to 40% by weight.
- concentration of the polyhydric alcohol is less than 0.001% by weight, the silicon etch rate is not sufficiently increased.
- concentration of the polyhydric alcohol exceeds 50% by weight, the silicon etch rate decreases.
- the silicon etchant of the present invention may be blended with additives such as surfactants and anticorrosives that have been conventionally used in etchants as long as they do not impair the purpose of the present invention.
- the silicon etching solution of the present invention covers a dummy gate stack including a high dielectric material film and a dummy gate made of silicon, a sidewall provided to cover a side surface of the stack, and the sidewall on the substrate.
- the structure having the interlayer insulating film thus provided is used for etching a dummy gate made of silicon.
- FIG. 1 shows a cross-sectional view of a structure having a dummy gate etched with the etching solution of the present invention. The structure shown in FIG.
- FIG. 1 shows a silicon natural oxide film 6. As shown in FIG.
- the structure may already have a place where the dummy gate 1 is replaced with a metal gate 2 containing hafnium, zirconium, titanium, tantalum, or tungsten.
- 1 shows the source / drain 8 and the isolation 7 that can be formed by a method such as ion implantation.
- the high dielectric material film 3 is a substrate so as to cover the space between the source / drain 8. 9 is provided on the surface.
- the structure may already have a place where the dummy gate 1 is replaced with the metal gate 2.
- the metal gate 2 is a metal gate containing hafnium, zirconium, titanium, tantalum, or tungsten, and the metal gate is not formed of 100% hafnium, zirconium, titanium, tantalum, or tungsten.
- the content of these metals is preferably 50% or more.
- all the dummy gates may be replaced with metal gates of these metals, or a part of them may be replaced.
- the effect of the present invention can be obtained in that the silicon forming the dummy gate is selectively etched without etching the part.
- the high dielectric material film 2 is a substrate so as to cover the space between the source / drain 8. 9 is provided on the surface.
- the substrate material used for the substrate 7 is preferably silicon, amorphous silicon, polysilicon, glass or the like, and the wiring material is copper, tungsten, titanium- Wiring materials such as tungsten, aluminum, aluminum alloy, chromium, and chromium alloy may be used.
- a silicon oxide film (HDP), tetraethoxysilane (TEOS), Boron Phosphorate Silicate Glass (BPSG) or the like by a high density plasma chemical vapor deposition method is preferably used as a material used for the interlayer insulating film 4.
- high dielectric materials include HfO 2 , Al 2 O 3 , or silicon atoms and / or nitrogen atoms and / or La, Ti, A material containing a metal such as Zr is preferably used.
- the materials used for the interlayer insulating film 4, the sidewall 3, and the high dielectric material film 2 are not limited to these.
- the silicon etching solution of the present invention first touches the metal gate 2, the interlayer insulating film 5 and the sidewall 4 of the structure. Become. Further, when the dummy gate 1 is etched, the high dielectric material film 3 is exposed from the bottom of the dummy gate 1, so that the high dielectric material film 3 is touched. Under such circumstances, the silicon etchant of the present invention selectively etches the dummy gate 1 made of silicon without etching the metal gate 2, the interlayer insulating film 5, the sidewall 4, and the high dielectric material film 3. Since it has characteristics, damage to each part of the transistor can be prevented, and a high-precision and high-quality transistor can be manufactured with high yield.
- the use temperature of the silicon etching solution of the present invention that is, the temperature at the time of etching the dummy gate is usually in the range of about 20 to 80 ° C., preferably 20 to 70 ° C., more preferably 20 to 60 ° C. What is necessary is just to select suitably by these conditions and the board
- the processing time with the silicon etching solution of the present invention is usually in the range of about 0.1 to 10 minutes, preferably 0.2 to 8 minutes, more preferably 0.3 to 5 minutes. Therefore, it may be selected as appropriate depending on the etching conditions and the substrate material used.
- the method of manufacturing a transistor of the present invention includes a dummy gate stacked body in which at least a high dielectric material film and a dummy gate made of silicon are stacked on a substrate, a sidewall provided so as to cover a side surface of the stacked body, and Using a structure having an interlayer insulating film provided so as to cover the sidewall, the dummy gate is made of an alkali compound that is at least one selected from ammonia, diamine, and polyamine represented by the general formula (1) 0.1 to 40% by weight, polyhydric alcohol represented by general formula (2), polyhydric alcohol represented by general formula (3), cyclic polyhydric alcohol represented by general formula (4), and reduction Silicone containing 0.01 to 40% by weight of polyhydric alcohol, which is at least one selected from non-saccharides, and 40 to 99.89% by weight of water And a step of etching (I) with a quenching fluid, and is characterized in that to replace the dummy gate hafnium
- the structure and the etching solution used in step (I) are as described above.
- the use temperature and processing time when using the etching solution of the present invention are also as described above.
- ultrasonic waves can be used together as necessary.
- the method for producing a transistor of the present invention is not particularly limited as long as it has the etching step (I) using the above-described etching solution of the present invention.
- Step (C) forming a sidewall so as to cover the side surface of the laminate, step (D) forming an interlayer insulating film so as to cover the sidewall, and step (E) a silicon natural oxide film Etching step, step (I) dummy gate etching step using the above-described etching solution of the present invention, and step (F) a metal gate is formed on the high dielectric material film, and the high dielectric material film Manufacturing method having a step of laminating body comprises fine metal gate in order and the like.
- the steps (A) to (F) are not particularly limited, and may be in accordance with a method generally employed in each step in the transistor manufacturing method.
- a conventionally used etching solution containing a fluorine compound such as hydrofluoric acid can be used for etching the silicon natural oxide film.
- a fluorine compound such as hydrofluoric acid
- the metal gate 2, the interlayer insulating film 5 and the sidewall 4 of the structure are touched, so that these portions are not damaged, that is, the silicon natural oxide film is selectively etched.
- an etching solution having As such an etching solution it is preferable to use an etching solution containing 0.01 to 8% by weight of a fluorine compound, 20 to 90% by weight of a water-soluble organic solvent, and water.
- fluorine compound Preferable specific examples of the fluorine compound are hydrofluoric acid, ammonium fluoride, and acidic ammonium fluoride. More preferred are ammonium fluoride and acidic ammonium fluoride. In this invention, these fluorine compounds can be mix
- the water-soluble organic solvent is preferably an alcohol such as ethanol, 2-propanol, ethylene glycol or diethylene glycol; a glycol ether such as diethylene glycol monomethyl ether, diethylene glycol monobutyl ether, dipropylene glycol monomethyl ether or dipropylene glycol monopropyl ether; Preferred examples include amides such as N, N-dimethylformamide, N, N-dimethylacetamide and N-methyl-2-pyrrolidone; dimethyl sulfoxide and the like. These water-soluble organic solvents may be used alone or in combination of two or more.
- the etching solution used in this step (E) includes inorganic acids such as hydrochloric acid, nitric acid, sulfuric acid, and phosphoric acid; organic acids such as acetic acid, propionic acid, oxalic acid, and methanesulfonic acid. You may add in the range. These acids may be used alone or in combination of two or more.
- the transistor obtained by the manufacturing method of the present invention includes a stacked body in which at least a high dielectric material film 3 and a metal gate 2 are stacked on a substrate 9, a side wall 4 provided so as to cover a side surface of the stacked body,
- the dummy gate 1 is made of hafnium, zirconium
- the metal gate 2 is replaced with titanium, tantalum, or tungsten.
- the transistor obtained by the manufacturing method of the present invention has a source / drain 8 and an isolation 7, and the high dielectric material film 3 is interposed between the source / drain 8. Is provided on the surface of the substrate 9.
- the substrate material used for the substrate 9, the material used for the interlayer insulating film 5, and the material used for the sidewall 4 are the substrates used for the substrate 9 in the above structure.
- the same materials, materials used for the interlayer insulating film 5 and materials used for the sidewalls 4 are used.
- the transistor obtained by the manufacturing method of the present invention may have a portion that the transistor normally has, for example, a barrier layer or an insulating film.
- the barrier material for forming the barrier layer preferable examples of the barrier material include titanium, titanium nitride, tantalum, and tantalum nitride.
- the insulating material for forming the insulating film silicon oxide, silicon nitride, silicon carbide, and the like. Preferred are the derivatives of In the laminate formed by laminating the high dielectric material film 3 and the metal gate 2 containing hafnium, zirconium, titanium, tantalum, or tungsten, the metal gate 2 made of a metal material other than the metal forming the metal gate 2 is further provided.
- a layer having a function such as a characteristic control film may be stacked.
- the semiconductor material a compound semiconductor such as gallium-arsenic, gallium-phosphorus, indium-phosphorus, or an oxide semiconductor such as chromium oxide is preferable.
- the transistor obtained by the manufacturing method of the present invention is a high-precision and high-quality transistor.
- Evaluation method Measuring equipment SEM observation: Observation was performed using an ultrahigh resolution field emission scanning electron microscope S-5500 manufactured by Hitachi High-Technologies Corporation.
- FIB processing Processing was performed using a focused ion beam processing apparatus FB-2100 manufactured by Hitachi High-Technologies Corporation.
- Examples 1 to 66 A silicon wafer was employed as the substrate, and a structure having a cross-sectional view as shown in FIG. 1 having a transistor structure on the silicon wafer and having the transistor structure of 1A to 1I shown in Table 1 was prepared.
- a structure having a cross-sectional view as shown in FIG. 1 having a transistor structure on the silicon wafer and having the transistor structure of 1A to 1I shown in Table 1 was prepared.
- 0.05 wt% hydrofluoric acid etching solution was used. It was immersed for 2 minutes at 25 ° C., rinsed with ultrapure water, and dried by spraying dry nitrogen gas.
- the substrate was immersed in the etching solution shown in Table 3 (see Table 2 for the composition of each etching solution) at a predetermined temperature and time, rinsed with ultrapure water, and dried by spraying dry nitrogen gas.
- the state of the dummy gate 1, the metal gate 2, the sidewall 4, and the interlayer insulating film 5 made of silicon was determined by observing the cross section of the transistor after etching with an SEM.
- the high dielectric material film 3 is covered with a dummy gate 1 made of silicon. Therefore, when the dummy gate 1 made of silicon is removed by the etching solution, the etching solution comes into contact with the high dielectric material film 3, and by observing the state of the high dielectric material film 3, the high dielectric material by the etching solution is used. Damage to the material film can be determined. Therefore, only when the dummy gate 1 made of silicon is etched, the high-dielectric material film 3 is obtained by thinning the transistor after etching to a thickness of 200 nm or less using an FIB and observing with a STEM. Judged the state of.
- Tables 3 and 5 show the evaluation results of the state of the dummy gate 1 made of silicon.
- Comparative Example 1 After using the structure having the transistor structure 1D and performing the hydrofluoric acid treatment shown in Example 1, 2 of tetramethylammonium hydroxide, which is a component described in Non-Patent Document 2, instead of the etching solution 2A. As a result of etching using a weight% aqueous solution (Table 4, etching solution 4A), the etching capability of the dummy gate 1 made of silicon was insufficient as shown in Table 5. From this, it can be seen that the etching solution described in Non-Patent Document 2 cannot be used for silicon etching in a transistor forming process including a metal gate containing a high dielectric material and aluminum, which is the subject of the present invention.
- Comparative Example 2 After the hydrofluoric acid treatment shown in Example 1 was performed using the structure having the transistor structure 1B, 58% by weight of ethylenediamine, which is a component described in Non-Patent Document 2, instead of the etching solution 2A, catechol 21 As shown in Table 5, the dummy gate 1 made of silicon was obtained as a result of etching using wt%, pyrazine 0.4 wt%, and water 20.6 wt% (Table 4, etching solution 4B). The etching ability of was insufficient. From this, it can be seen that the etching solution described in Non-Patent Document 2 cannot be used for silicon etching in a transistor forming process including a high dielectric material and a metal gate, which is an object of the present invention.
- Comparative Example 3 After using the structure having the transistor structure 1C and performing the hydrofluoric acid treatment shown in Example 1, 10% by weight of tetramethylammonium hydroxide described in Patent Document 3 and hydroxylamine instead of the etching solution 2A As a result of etching using an aqueous solution of 10% by weight and 5% by weight of sorbitol (Table 4, etching solution 4C), as shown in Table 5, the etching capability of the dummy gate 1 made of silicon is insufficient. It was. From this, the aqueous solution described in Patent Document 3 had an excessively low silicon etch rate. Furthermore, since the reducing compound reacts with oxygen in the air to reduce the etching ability of the composition, special consideration is required for storage. Thus, it can be seen that the etching solution described in Patent Document 2 cannot be used for silicon etching in the process of forming a transistor containing a high dielectric material and a metal, which is the subject of the present invention.
- Comparative Example 4 After using the structure having the transistor structure 1G and performing the hydrofluoric acid treatment shown in Example 1, hexamethylenediamine (1,6-hexanediamine) described in Patent Document 4 instead of the etching solution 2A As a result of etching using an aqueous solution of 5% by weight and 1% by weight of sorbitol (Table 4, etching solution 4D), as shown in Table 5, the etching capability of the dummy gate 1 made of silicon is insufficient. It was. From this, it can be seen that the aqueous solution described in Patent Document 4 cannot be used for silicon etching in a transistor forming process including a high dielectric material and a metal gate, which is the subject of the present invention.
- Comparative Example 5 After the hydrofluoric acid treatment shown in Example 1 was performed using the structure having the transistor structure 1E, an alkaline aqueous solution (Table 4, Etching 9% by weight of ammonia and 91% by weight of water instead of the etching solution 2A) was used. As a result of etching using the liquid 4E), as shown in Table 5, the etching capability of the dummy gate 1 made of silicon was insufficient. From this, it can be seen that the alkaline aqueous solution described in Patent Document 5 cannot be used for silicon etching in a transistor formation process including a high dielectric material and a metal gate, which is the subject of the present invention.
- Comparative Example 7 After the hydrofluoric acid treatment shown in Example 1 was performed using the structure having the transistor structure 1F, 1,3-propanediamine 5% by weight, catechol 1% by weight, water 94% by weight instead of the etching solution 2A As a result of performing an etching process using a 30% aqueous solution (Table 4, etching solution 4G), as shown in Table 5, the etching capability of the dummy gate 1 made of silicon was insufficient. Thus, an aqueous solution containing an alkali compound and a polyhydric alcohol using an aromatic polyhydric alcohol as a polyhydric alcohol is not suitable for silicon etching in a transistor forming process including a high dielectric material and a metal gate, which is the object of the present invention. It turns out that it cannot be used.
- Comparative Example 8 After using the structure having the transistor structure 1H and performing the hydrofluoric acid treatment shown in Example 1, 0.5% by weight of 1,3-propanediamine and 99.5% by weight of water instead of the etching solution 2A As a result of performing an etching process using an aqueous solution (Table 4, etching solution 4H), as shown in Table 5, the etching capability of the dummy gate 1 made of silicon was insufficient. Therefore, the aqueous solution obtained by removing polyhydric alcohol from the etching solution 2D shown in Table 2 cannot be used for silicon etching in a transistor forming process including a high dielectric material and a metal gate, which is the object of the present invention. Recognize.
- Comparative Example 9 After the hydrofluoric acid treatment shown in Example 1 was performed using the structure having the transistor structure 1A, an aqueous solution (first solution of 30% by weight of 1,3-propanediamine and 70% by weight of water was used instead of the etching solution 2A. As a result of etching using Table 4 and etching solution 4I), as shown in Table 5, the dummy gate 1 made of silicon was insufficiently etched. Therefore, the aqueous solution obtained by removing polyhydric alcohol from the etching solution 2E shown in Table 2 cannot be used for silicon etching in a transistor forming process including a high dielectric material and a metal gate, which is the subject of the present invention. Recognize.
- a metal gate containing hafnium, zirconium, titanium, tantalum or tungsten, an interlayer insulating film, a sidewall, and a dummy gate made of silicon are selectively etched without etching. Since it can be etched, it can be used in the process of forming a transistor including a high dielectric material film and the metal gate, which is industrially useful.
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Abstract
Description
2:金属ゲート
3:高誘電材料膜
4:サイドウォール
5:層間絶縁膜
6:シリコン自然酸化膜
7:アイソレーション
8:ソース/ドレイン
9:基板
H2N-(CH2CH2NH)k-H ・・・(1)
(kは2~5の整数である。)
H-(CH(OH))l-R ・・・(2)
(lは2~6の整数、Rは水素又はアルキル基である。)
C-((CH2)mOH)4 ・・・(3)
(mは1又は2である。)
(CH(OH))n ・・・(4)
(nは3~8の整数である。)
2.ジアミン及び一般式(1)で表されるポリアミンが、エチレンジアミン、1,2-プロパンジアミン、1,3-プロパンジアミン、ジエチレントリアミン、及びトリエチレンテトラミンから選ばれる少なくとも1種である上記1に記載のシリコンエッチング液。
3.一般式(2)~(4)で表される多価アルコールが、エチレングリコール、グリセリン、meso-エリトリトール、キシリトール、ソルビトール、プロピレングリコール、ペンタエリトリトール、及びイノシトールから選ばれる少なくとも1種である上記1に記載のシリコンエッチング液。
4.還元性を有しない糖類が、スクロース、トレハロース、又はラフィノースである上記1に記載のシリコンエッチング液。
5.高誘電材料膜を形成する高誘電材料が、HfO2、HfSiO、HfSiON、HfLaO、HfLaON、HfTiSiON、HfAlSiON、HfZrO、又はAl2O3である上記1に記載のシリコンエッチング液。
6.基板上に、少なくとも高誘電材料膜とシリコンからなるダミーゲートとが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体を用い、以下の工程(I)を有し、かつ該ダミーゲートをハフニウム、ジルコニウム、チタン、タンタル、又はタングステンを含む金属ゲートに入れ替えることを特徴とするトランジスタの製造方法。
工程(I)シリコンを、アンモニア、ジアミン、及び一般式(1)で表されるポリアミンから選ばれる少なくとも1種であるアルカリ化合物を0.1~40重量%、一般式(2)で表される多価アルコール、一般式(3)で表される多価アルコール、一般式(4)で表される環状多価アルコール、及び還元性を有しない糖類から選ばれる少なくとも1種である多価アルコールを0.01~40重量%、ならびに水40~99.89重量%を含有するシリコンエッチング液を用いてエッチングする工程
H2N-(CH2CH2NH)k-H ・・・(1)
(kは2~5の整数である。)
H-(CH(OH))l-R ・・・(2)
(lは2~6の整数、Rは水素又はアルキル基である。)
C-((CH2)mOH)4 ・・・(3)
(mは1又は2である。)
(CH(OH))n ・・・(4)
(nは3~8の整数である。)
7.ジアミン及び一般式(1)で表されるポリアミンが、エチレンジアミン、1,2-プロパンジアミン、1,3-プロパンジアミン、ジエチレントリアミン、及びトリエチレンテトラミンから選ばれる少なくとも1種である上記6に記載のトランジスタの製造方法。
8.一般式(2)~(4)で表される多価アルコールが、エチレングリコール、グリセリン、meso-エリトリトール、キシリトール、ソルビトール、プロピレングリコール、ペンタエリトリトール、及びイノシトールから選ばれる少なくとも1種である上記6に記載のトランジスタの製造方法。
9.還元性を有しない糖類が、スクロース、トレハロース、又はラフィノースである上記6に記載のトランジスタの製造方法。
10.高誘電材料膜を形成する高誘電材料が、HfO2、HfSiO、HfSiON、HfLaO、HfLaON、HfTiSiON、HfAlSiON、HfZrO、又はAl2O3である上記6に記載のトランジスタの製造方法。
本発明のシリコンエッチング液は、基板上に、少なくとも高誘電材料膜とシリコンからなるダミーゲートとが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体を用い、該ダミーゲートをハフニウム、ジルコニウム、チタン、タンタル、又はタングステンを含む金属ゲートに入れ替えることを特徴とするトランジスタの製造方法における、該シリコンからなるダミーゲートのエッチングに用いられるものであり、アンモニア、ジアミン、及び一般式(1)で表されるポリアミンから選ばれる少なくとも1種であるアルカリ化合物を0.1~40重量%、一般式(2)で表される多価アルコール、一般式(3)で表される多価アルコール、一般式(4)で表される環状多価アルコール、及び還元性を有しない糖類から選ばれる少なくとも1種である多価アルコールを0.01~40重量%、ならびに水40~99.89重量%を含有する液である。
H2N-(CH2CH2NH)k-H ・・・(1)
(kは2~5の整数である。)
H-(CH(OH))l-R ・・・(2)
(lは2~6の整数、Rは水素又はアルキル基である。)
C-((CH2)mOH)4 ・・・(3)
(mは1又は2である。)
(CH(OH))n ・・・(4)
(nは3~8の整数である。)
エッチング液中のアルカリ化合物の濃度は、通常0.1~40重量%であり、好ましくは0.2~40重量%で、より好ましくは0.3~30重量%である。アルカリ化合物濃度が0.1重量%未満、あるいは40重量%を超えると、有効なエッチレートが得られない。
一般式(2)で表される多価アルコールの具体例としては、エチレングリコール、グリセリン、meso-エリトリトール、キシリトール、ソルビトール、プロピレングリコールなどが好ましく挙げられ、一般式(3)で表される多価アルコールとしてはペンタエリトリトールが好ましく挙げられ、一般式(4)で表される環状多価アルコールとしてはイノシトールが好ましく挙げられる。また、還元性を持たない糖類の具体例は、スクロース、トレハロースおよびラフィノースである。これらの多価アルコールは単独、又は2種以上を組み合わせて配合できる。
本発明のシリコンエッチング液は、基板上に、高誘電材料膜、及びシリコンからなるダミーゲートを含むダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体の、シリコンからなるダミーゲートのエッチングに用いられる。ここで、図1に、本発明のエッチング液によりエッチングするダミーゲートを有する構造体の断面図を示す。図1に示される構造体は、基板9上に、高誘電材料膜3とシリコンからなるダミーゲート1とが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール4、及び該サイドウォール4を覆うように設けられる層間絶縁膜5を有する構造体である。また、ダミーゲート1の材料として用いられる多結晶シリコンなどのシリコン材料は、トランジスタの製造過程において空気と接触するため、その表面が自然酸化し、シリコン自然酸化膜6が形成する場合があるので、図1にシリコン自然酸化膜6を示した。
図1に示されるように、構造体は、既にダミーゲート1がハフニウム、ジルコニウム、チタン、タンタル、又はタングステンを含む金属ゲート2に入れ替えられた箇所があってもよい。また、図1にはイオン注入などの方法により形成しうるソース/ドレイン8、アイソレーション7が示されているが、通常高誘電材料膜3は、ソース/ドレイン8の間を覆うように、基板9の表面上に設けられる。
また、図1にはイオン注入などの方法により形成しうるソース/ドレイン8、アイソレーション7が示されているが、通常高誘電材料膜2は、ソース/ドレイン8の間を覆うように、基板9の表面上に設けられる。
また、層間絶縁膜4に用いられる材料としては、高密度プラズマ化学気相法による酸化シリコン膜(HDP)、テトラエトキシシラン(TEOS)、Boron Phosphor Silicate Glass(BPSG)などが好ましく使用され、サイドウォール3に用いられる材料としては、窒化シリコン(SiN)などが好ましく使用され、高誘電材料としては、HfO2、Al2O3、あるいはこれらにケイ素原子及び/又は窒素原子及び/又はLa、Ti、Zrなどの金属を含む材料が好ましく使用される。層間絶縁膜4、サイドウォール3、高誘電材料膜2に使用される材料は、これらに限定されるものではない。
本発明のシリコンエッチング液の使用温度、すなわちダミーゲートのエッチングの際の温度は、通常20~80℃程度の範囲であり、好ましくは20~70℃で、より好ましくは20~60℃で、エッチングの条件や使用される基板材料により適宜選択すればよい。
本発明のトランジスタの製造方法は、基板上に、少なくとも高誘電材料膜とシリコンからなるダミーゲートとが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体を用い、該ダミーゲートを、アンモニア、ジアミン、及び一般式(1)で表されるポリアミンから選ばれる少なくとも1種であるアルカリ化合物を0.1~40重量%、一般式(2)で表される多価アルコール、一般式(3)で表される多価アルコール、一般式(4)で表される環状多価アルコール、及び還元性を有しない糖類から選ばれる少なくとも1種である多価アルコールを0.01~40重量%、ならびに水40~99.89重量%を含有するシリコンエッチング液を用いてエッチングする工程(I)を有し、かつ該ダミーゲートをハフニウム、ジルコニウム、チタン、タンタル、又はタングステンを含む金属ゲートに入れ替えることを特徴とするものである。
H2N-(CH2CH2NH)k-H ・・・(1)
(kは2~5の整数である。)
H-(CH(OH))l-R ・・・(2)
(lは2~6の整数、Rは水素又はアルキル基である。)
C-((CH2)mOH)4 ・・・(3)
(mは1又は2である。)
(CH(OH))n ・・・(4)
(nは3~8の整数である。)
本発明のエッチング液を用いたエッチング工程(I)においては、必要に応じて超音波を併用することができる。また、本発明の製造方法により、基板上のエッチング残渣を除去した後のリンス液としては、アルコールのような有機溶剤を使用する必要はなく、水でリンスするだけで十分である。
本発明のトランジスタの製造方法は、上記した本発明のエッチング液を用いたエッチング工程(I)を有していれば特に制限はなく、本発明の好ましいトランジスタの製造方法の一態様としては、工程(A)基板上に高誘電材料膜を形成する工程、工程(B)該高誘電材料膜上に多結晶シリコンからなるダミーゲートを形成し、高誘電材料膜及びダミーゲートを含む積層体を形成する工程、工程(C)該積層体の側面を覆うようにサイドウォールを形成する工程、工程(D)該サイドウォールを覆うように層間絶縁膜を形成する工程、工程(E)シリコン自然酸化膜のエッチング工程、工程(I)上記した本発明のエッチング液を用いたダミーゲートのエッチング工程、及び工程(F)該高誘電材料膜上に金属ゲートを形成し、高誘電材料膜及び金属ゲートを含む積層体する工程を順に有する製造方法が挙げられる。上記の工程(A)~(F)については、特に制限はなく、トランジスタの製造方法における各工程で一般的に採用される方法に準じればよい。
図1に示されるように、シリコンからなるダミーゲート1は、トランジスタの製造過程において空気と接触するため、その表面が自然酸化し、シリコン自然酸化膜が形成する場合がある。そこで、本発明の製造方法においては、本発明のエッチング液を用いたダミーゲート1をエッチングする工程(工程(I))の前に、シリコン自然酸化膜6を予めエッチングすることが好ましい。このような工程を有することで、本発明のエッチング液を用いたダミーゲートのエッチング工程が効率的に行うことが可能となるので、高精度、高品質のトランジスタを歩留まりよく製造することが可能となる。
水溶性有機溶媒としては、好ましくはエタノール、2-プロパノール、エチレングリコール、ジエチレングリコールなどのアルコール類;ジエチレングリコールモノメチルエーテル、ジエチレングリコールモノブチルエーテル、ジプロピレングリコールモノメチルエーテル、ジプロピレングリコールモノプロピルエーテルなどのグリコールエーテル類;N,N-ジメチルホルムアミド、N,N-ジメチルアセトアミド、N-メチル-2-ピロリドンなどのアミド類;ジメチルスルホキシドなどが好ましく挙げられる。これらの水溶性有機溶媒は、単独でも2種類以上組み合わせて用いてもよい。
また、本工程(E)に用いられるエッチング液には、塩酸、硝酸、硫酸、リン酸などの無機酸;酢酸、プロピオン酸、シュウ酸、メタンスルホン酸などの有機酸を、5重量%以下程度の範囲で加えてもよい。これらの酸は、単独でも2種類以上組み合わせて用いてもよい。
本発明の製造方法により得られるトランジスタは、基板9上に、少なくとも高誘電材料膜3と金属ゲート2とが積層してなる積層体、該積層体の側面を覆うように設けられるサイドウォール4、該サイドウォール4を覆うように設けられる層間絶縁膜5を有するもの、すなわち、本発明のエッチング液によりエッチングする工程に供される図1に示される構造体において、ダミーゲート1をハフニウム、ジルコニウム、チタン、タンタル、又はタングステンを含む金属ゲート2に入れ替えたものである。また、図1に示されるように、本発明の製造方法により得られるトランジスタは、ソース/ドレイン8、及びアイソレーション7を有しており、高誘電材料膜3は、該ソース/ドレイン8の間を覆うように、基板9の表面上に設けられている。
高誘電材料膜3とハフニウム、ジルコニウム、チタン、タンタル、又はタングステンを含む金属ゲート2とが積層してなる積層体において、該金属ゲート2を形成する金属以外の金属材料からなる金属ゲート2がさらに積層したり、例えば特性制御膜といった機能を有する層が積層されていてもよい。また、半導体材料としては、ガリウム-砒素、ガリウム-リン、インジウム-リンなどの化合物半導体や、クロム酸化物などの酸化物半導体などが好ましく挙げられる。
本発明の製造方法により得られるトランジスタは、高精度、高品質のトランジスタである。
測定機器;
SEM観察:株式会社日立ハイテクノロジーズ社製、超高分解能電界放出形走査電子顕微鏡S-5500を用いて観察した。
FIB加工:株式会社日立ハイテクノロジーズ社製、集束イオンビーム加工装置FB-2100を用いて加工した。
STEM観察:株式会社日立ハイテクノロジーズ社製、走査透過電子顕微鏡HD-2300を用いて観察した。
判定;
(シリコンからなるダミーゲート1のエッチング状態)
○:ダミーゲート1が完全にエッチングされた。
×:ダミーゲート1のエッチングが不十分であった。
基板としてシリコンウェハを採用し、該シリコンウェハ上にトランジスタ構造を有し、該トランジスタ構造が第1表に示される1A~1Iである、図1に示すような断面図の構造体を用意した。各実施例について、第3表に示される構造体を用い、シリコンからなるダミーゲート1の表面に存在するシリコン自然酸化膜を除去するため、0.05重量%フッ化水素酸のエッチング液に、25℃、2分間浸漬し、超純水によるリンス、乾燥窒素ガス噴射による乾燥を行った。その後、第3表に示したエッチング液(各エッチング液の組成は第2表を参照)に所定の温度、時間で浸漬し、超純水によるリンス、乾燥窒素ガス噴射による乾燥を行った。
エッチング後のトランジスタ断面をSEMで観察することにより、シリコンからなるダミーゲート1、金属ゲート2、サイドウォール4、及び層間絶縁膜5の状態を判断した。
トランジスタ構造1Dを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Aのかわりに非特許文献2に記された成分である水酸化テトラメチルアンモニウムの2重量%水溶液(第4表、エッチング液4A)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、非特許文献2記載のエッチング液は、本発明の対象である高誘電材料とアルミニウムを含有する金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Bを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Aのかわりに非特許文献2に記された成分であるエチレンジアミン58重量%、カテコール21重量%、ピラジン0.4重量%、水20.6重量%(第4表、エッチング液4B)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、非特許文献2に記載のエッチング液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Cを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Aのかわりに特許文献3に記された水酸化テトラメチルアンモニウム10重量%とヒドロキシルアミン10重量%とソルビトール5重量%の水溶液(第4表、エッチング液4C)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、特許文献3記載の水溶液は、シリコンのエッチレートが小さすぎた。さらに、還元性化合物は空気中の酸素と反応して組成物のエッチング能力を低下させるため、保存に特段の配慮が必要であった。このように、特許卯文献2記載のエッチング液は、本発明の対象である高誘電材料と金属を含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Gを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Aのかわりに特許文献4に記されたヘキサメチレンジアミン(1、6-ヘキサンジアミン)5重量%とソルビトール1重量%の水溶液(第4表、エッチング液4D)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、特許文献4記載の水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Eを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Aのかわりにアンモニア9重量%、水91重量%のアルカリ水溶液(第4表、エッチング液4E)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、特許文献5記載のアルカリ水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Iを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Aのかわりにソルビトール5重量%、水95重量%の多価アルコールを含む水溶液(第4表、エッチング液4F)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、単に多価アルコールを含む水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Fを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Aのかわりに1,3-プロパンジアミン5重量%、カテコール1重量%、水94重量%の水溶液(第4表、エッチング液4G)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、多価アルコールとして芳香族多価アルコールを用いたアルカリ化合物と多価アルコールを含む水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Hを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Aのかわりに1,3-プロパンジアミン0.5重量%、水99.5重量%の水溶液(第4表、エッチング液4H)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1のエッチング能力が不足していた。このことより、第2表に示したエッチング液2Dから多価アルコールを除いた水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
トランジスタ構造1Aを有する構造体を用い、実施例1で示したフッ化水素酸処理を行った後、エッチング液2Aのかわりに1,3-プロパンジアミン30重量%と水70重量%の水溶液(第4表、エッチング液4I)を用いてエッチング処理を行った結果、第5表に示されるように、シリコンからなるダミーゲート1はエッチングが不足していた。このことより、第2表に示したエッチング液2Eから多価アルコールを除いた水溶液は、本発明の対象である高誘電材料と金属ゲートを含んだトランジスタ形成工程におけるシリコンエッチングには使用できないことがわかる。
Claims (10)
- 基板上に、少なくとも高誘電材料膜とシリコンからなるダミーゲートとが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体を用い、該ダミーゲートをハフニウム、ジルコニウム、チタン、タンタル、又はタングステンを含む金属ゲートに入れ替えることを特徴とするトランジスタの製造方法における、該シリコンからなるダミーゲートのエッチングに用いられ、アンモニア、ジアミン、及び一般式(1)で表されるポリアミンから選ばれる少なくとも1種であるアルカリ化合物を0.1~40重量%、一般式(2)で表される多価アルコール、一般式(3)で表される多価アルコール、一般式(4)で表される環状多価アルコール、及び還元性を有しない糖類から選ばれる少なくとも1種である多価アルコールを0.01~40重量%、ならびに水40~99.89重量%を含有するシリコンエッチング液。
H2N-(CH2CH2NH)k-H ・・・(1)
(kは2~5の整数である。)
H-(CH(OH))l-R ・・・(2)
(lは2~6の整数、Rは水素又はアルキル基である。)
C-((CH2)mOH)4 ・・・(3)
(mは1又は2である。)
(CH(OH))n ・・・(4)
(nは3~8の整数である。) - ジアミン及び一般式(1)で表されるポリアミンが、エチレンジアミン、1,2-プロパンジアミン、1,3-プロパンジアミン、ジエチレントリアミン、及びトリエチレンテトラミンから選ばれる少なくとも1種である請求項1に記載のシリコンエッチング液。
- 一般式(2)~(4)で表される多価アルコールが、エチレングリコール、グリセリン、meso-エリトリトール、キシリトール、ソルビトール、プロピレングリコール、ペンタエリトリトール、及びイノシトールから選ばれる少なくとも1種である請求項1に記載のシリコンエッチング液。
- 還元性を有しない糖類が、スクロース、トレハロース、又はラフィノースである請求項1に記載のシリコンエッチング液。
- 高誘電材料膜を形成する高誘電材料が、HfO2、HfSiO、HfSiON、HfLaO、HfLaON、HfTiSiON、HfAlSiON、HfZrO、又はAl2O3である請求項1に記載のシリコンエッチング液。
- 基板上に、少なくとも高誘電材料膜とシリコンからなるダミーゲートとが積層してなるダミーゲート積層体、該積層体の側面を覆うように設けられるサイドウォール、及び該サイドウォールを覆うように設けられる層間絶縁膜を有する構造体を用い、以下の工程(I)を有し、かつ該ダミーゲートをハフニウム、ジルコニウム、チタン、タンタル、又はタングステンを含む金属ゲートに入れ替えることを特徴とするトランジスタの製造方法。
工程(I)シリコンを、アンモニア、ジアミン、及び一般式(1)で表されるポリアミンから選ばれる少なくとも1種であるアルカリ化合物を0.1~40重量%、一般式(2)で表される多価アルコール、一般式(3)で表される多価アルコール、一般式(4)で表される環状多価アルコール、及び還元性を有しない糖類から選ばれる少なくとも1種である多価アルコールを0.01~40重量%、ならびに水40~99.89重量%を含有するシリコンエッチング液を用いてエッチングする工程
H2N-(CH2CH2NH)k-H ・・・(1)
(kは2~5の整数である。)
H-(CH(OH))l-R ・・・(2)
(lは2~6の整数、Rは水素又はアルキル基である。)
C-((CH2)mOH)4 ・・・(3)
(mは1又は2である。)
(CH(OH))n ・・・(4)
(nは3~8の整数である。) - ジアミン及び一般式(1)で表されるポリアミンが、エチレンジアミン、1,2-プロパンジアミン、1,3-プロパンジアミン、ジエチレントリアミン、及びトリエチレンテトラミンから選ばれる少なくとも1種である請求項6に記載のトランジスタの製造方法。
- 一般式(2)~(4)で表される多価アルコールが、エチレングリコール、グリセリン、meso-エリトリトール、キシリトール、ソルビトール、プロピレングリコール、ペンタエリトリトール、及びイノシトールから選ばれる少なくとも1種である請求項6に記載のトランジスタの製造方法。
- 還元性を有しない糖類が、スクロース、トレハロース、又はラフィノースである請求項6に記載のトランジスタの製造方法。
- 高誘電材料膜を形成する高誘電材料が、HfO2、HfSiO、HfSiON、HfLaO、HfLaON、HfTiSiON、HfAlSiON、HfZrO、又はAl2O3である請求項6に記載のトランジスタの製造方法。
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- 2011-07-26 JP JP2012533910A patent/JPWO2012035888A1/ja not_active Withdrawn
- 2011-07-26 CN CN2011800445391A patent/CN103109356A/zh active Pending
- 2011-09-01 TW TW100131520A patent/TWI504726B/zh active
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JP2002359369A (ja) * | 2001-06-01 | 2002-12-13 | Sony Corp | 半導体装置の製造方法 |
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JP2005229053A (ja) | 2004-02-16 | 2005-08-25 | Mitsubishi Gas Chem Co Inc | 薄葉化半導体ウェーハの製造法 |
JP3994992B2 (ja) | 2004-08-13 | 2007-10-24 | 三菱瓦斯化学株式会社 | シリコン微細加工に用いる異方性エッチング剤組成物及びエッチング方法 |
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See also references of EP2618367A4 |
Also Published As
Publication number | Publication date |
---|---|
KR101797162B1 (ko) | 2017-11-13 |
US8852451B2 (en) | 2014-10-07 |
JPWO2012035888A1 (ja) | 2014-02-03 |
TW201219545A (en) | 2012-05-16 |
EP2618367A4 (en) | 2015-02-25 |
EP2618367B1 (en) | 2016-10-19 |
CN103109356A (zh) | 2013-05-15 |
US20130178069A1 (en) | 2013-07-11 |
TWI504726B (zh) | 2015-10-21 |
EP2618367A1 (en) | 2013-07-24 |
KR20140017483A (ko) | 2014-02-11 |
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