WO2010087362A1 - Procédé de formation de film, et appareil de formation de film par plasma - Google Patents

Procédé de formation de film, et appareil de formation de film par plasma Download PDF

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Publication number
WO2010087362A1
WO2010087362A1 PCT/JP2010/051025 JP2010051025W WO2010087362A1 WO 2010087362 A1 WO2010087362 A1 WO 2010087362A1 JP 2010051025 W JP2010051025 W JP 2010051025W WO 2010087362 A1 WO2010087362 A1 WO 2010087362A1
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Prior art keywords
gas
film forming
plasma
film
nitriding
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PCT/JP2010/051025
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English (en)
Japanese (ja)
Inventor
山▲崎▼　英亮
正人 小堆
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東京エレクトロン株式会社
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Priority to CN2010800059397A priority Critical patent/CN102301454A/zh
Publication of WO2010087362A1 publication Critical patent/WO2010087362A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the shower head 40 is formed in a circular shape, and is provided so as to face the entire upper surface of the mounting table 36 so as to cover the mounting table 36, and a processing space S is formed between the shower head 40 and the mounting table 36.
  • This shower head 40 introduces various gases into the processing space S in a shower shape, and a plurality of injection holes 46 for injecting gas are formed on the injection surface on the lower surface of the shower head 40.
  • a gate valve 80 that is airtightly opened and closed when the semiconductor wafer W is loaded and unloaded is provided on the side wall of the processing chamber 22.
  • ⁇ Plasma TiN film formation (thin film formation process)> After the Ti film 8 is formed as described above, a thin film forming process for forming a thin film made of a TiN film (titanium nitride film) using plasma is performed (S2). This thin film forming process is continuously performed in the same processing vessel 22 following the above process.
  • a thin film made of the film 10 is formed by a plasma CVD method.
  • the semiconductor wafer W is heated and maintained at a predetermined temperature by the heating means 38 including a resistance heater.
  • the TiN film 10 is deposited not only on the top surface of the semiconductor wafer W but also on the bottom surface and side surfaces in the recess 6.
  • the TiN film 10 is formed by the plasma CVD method having a higher directivity of film formation than the normal thermal CVD method, it is compared with the case of film formation by the conventional thermal CVD method.
  • a very thin TiN film 10 is formed on the side surface of the recess 6, which is difficult to deposit.
  • the applied high frequency power is, for example, in the range of 400 to 1000 W (watts).
  • the process time is set so that the thickness of the TiN film 10 deposited on the bottom of the recess 6 falls within a range of 2 to 10 nm, for example.
  • the nitriding of the TiN film 10 is appropriately performed, and the film quality is improved and stabilized.
  • the barrier property is improved and the specific resistance is also reduced.
  • the process pressure is in the range of 400 to 667 Pa as described later, and the process temperature is in the range of 400 to 700 ° C., for example.
  • the flow rate of each gas is Ar gas in the range of 500 to 2000 sccm, H 2 gas in the range of 500 to 5000 sccm, and NH 3 gas in the range of 100 to 2000 sccm, for example.
  • the partial pressure of NH 3 gas is in the range of 44 to 308 Pa, for example.
  • the applied high frequency power is, for example, in the range of 400 to 1000 W (watts).
  • the process time of this nitriding treatment is in the range of 5 to 60 sec, preferably in the range of 10 to 40 sec, more preferably in the range of 15 to 30 sec, as will be described later. If this process time is shorter than 5 seconds, the effect of the nitriding treatment is insufficient, and not only the barrier property becomes insufficient but also the specific resistance becomes high, which is not preferable. On the other hand, when the process time is longer than 60 sec, nitriding is excessively performed, which is not preferable because not only the barrier property is insufficient but also the specific resistance is increased.
  • the film quality characteristics composed of the Ti film 8 and the plasma nitriding TiN film 10 are suitable as a good barrier layer 12.
  • the recess 6 is filled with the conductive film 9.
  • a tungsten film is embedded as the conductive material by a thermal CVD process, or copper is embedded as the conductive material by a plating process.
  • this conductive material is not limited to tungsten or copper.
  • the unnecessary conductive film 9 on the upper surface of the semiconductor wafer W is scraped off and removed.
  • the removal method for example, an etching process or CMP (Chemical Mechanical Polishing) or the like is used.
  • the Ti film 8 is formed in the lower layer of the TiN film 10, but an embodiment in which only the TiN film 10 is formed without forming the Ti film 8 may be employed.
  • the barrier layer 12 has a single layer structure consisting of only the TiN film 10.
  • FIG. 4 is a table illustrating the evaluation of barrier properties between a TiN film that has not been subjected to plasma nitriding and a TiN film that has been subjected to plasma nitriding.
  • FIG. 5 is a table for explaining the evaluation of barrier properties when a plasmaless annealing process is performed on a TiN film formed by a thermal CVD method or an SFD method, which is a conventional film forming method.
  • FIG. 6 is a graph showing the relationship between the plasma nitriding time and the increasing point rate of the sheet resistance (Rs) before and after the plasma nitriding treatment.
  • the barrier property in the evaluation is approximately the same as the barrier property of the two-layered barrier layer composed of the Ti film and the TiN film. It can be said.
  • a TiN film was formed on a silicon substrate by a plasma CVD method to form a barrier layer, and a Cu film was formed without plasma nitriding treatment.
  • a plasma CVD method to form a barrier layer
  • a Cu film was formed without plasma nitriding treatment.
  • three samples of Comparative Examples 1 to 3 were prepared by changing the flow rate of the TiCl 4 gas as the source gas or changing the process pressure. These samples were annealed for 30 minutes in an Ar atmosphere at 400 ° C. and 10 Torr (1333 Pa).
  • the method of evaluation is the same as in Examples 1 to 4. That is, the barrier property was evaluated by measuring the sheet resistance before and after the annealing treatment.
  • the thickness of the TiN film was all set to 10 nm except for Example 4.
  • Example 1 Same as Example 3 During film formation: Example 1 except that the process pressure was lowered to 400 Pa Same as in plasma nitriding: same as Example 1 [Example 4] During film formation: Same as Example 1 except that the film thickness was set to 2 nm. Plasma nitridation: Same as Example 1
  • Process conditions of Comparative Examples 1 to 3 that is, process temperature, process pressure, gas flow rate, applied high frequency power, and film thickness are as follows (see FIG. 4).
  • FIG. 4 shows the Rs increase point rate after 30 min annealing and its evaluation in Comparative Examples 1 to 3 and Examples 1 to 4.
  • “x” indicates NG (defective), and “ ⁇ ” indicates good.
  • the Rs increase point rates of Comparative Examples 1 to 3 were 15.7%, 94.2%, and 32.2%, respectively, and the barrier properties of the TiN film were not so good.
  • they are 3.3%, 8.3%, 4.1%, and 0.0%, which are all lower than the standard value of 10%, and the barrier property is greatly increased. It was found that it was improved.
  • Each Rs increase point rate (excluding Comparative Example 2) is also represented as a graph in FIG. From the above, it can be seen that in order to improve the barrier property of the TiN film, it is necessary to perform plasma nitriding after the formation of the TiN film by plasma. Further, according to FIG. 6, it can be recognized that the longer the plasma nitriding treatment, the lower the Rs increase point rate and the higher the barrier property. As will be described later, this Rs increase point rate is It is considered that the time is about 30 seconds and the bottom starts and then rises.
  • the barrier property can be improved by subjecting the TiN film to plasma nitriding.
  • the improvement of the barrier property by the method of the present invention is effective when the thickness of the TiN film is 2 to 10 nm. In other words, it has been found that sufficient barrier properties can be obtained even if the barrier layer is thinned to 2 nm.
  • a plasma is not used to form a TiN film on a silicon substrate, a TiN film is formed by a thermal CVD method or SFD method as a barrier layer, and plasma is not used for this.
  • the sample was subjected to NH 3 nitridation treatment according to, and a Cu film was further formed on the TiN film by sputtering.
  • four samples of Comparative Examples 4 to 7 were made by changing the process temperature and film thickness. These samples were annealed for 30 minutes in an Ar atmosphere at 400 ° C. and 10 Torr (1333 Pa). Then, the sheet resistance before and after the annealing treatment was measured as in the previous evaluation experiment, and the barrier property was evaluated. The result at this time is shown in FIG.
  • the SFD film formation is a film formation method in which deposition (deposition) and nitridation are alternately repeated while flowing each gas flow rate, and a thin film is laminated over a plurality of layers. And one cycle.
  • the plasma nitriding time in the nitriding step is preferably in the range of 5 to 60 seconds. If this time is shorter than 5 sec, not only the Rs value is large, but also the barrier property cannot be sufficiently exhibited. On the other hand, if this time is longer than 60 sec, the Rs value becomes excessively large, which is not preferable. In this case, as shown below, the graph shown in FIG. 6 is also expected to draw a downward characteristic curve, that is, it is presumed that the barrier property is also deteriorated.
  • a more preferable range of the plasma nitriding time is in the range of 10 to 40 sec.
  • a more preferable range is within the range of 15 to 30 sec which is the bottom portion of the curve.
  • Ar gas is used as the plasma gas, but the present invention is not limited to this.
  • Other noble gases such as He and Ne may be used.
  • NH 3 gas is used as the nitriding gas in the plasma nitriding step, the present invention is not limited to this.
  • N 2 gas, hydrazine (H 2 N—NH 2 ) gas, monomethyl hydrazine (CH 3 —NH—NH 2 ) gas, or the like may be used.
  • TiCl 4 gas is used as the source gas, but the present invention is not limited to this.
  • TDMAT (Ti [N (CH 3 ) 2 ] 4 : tetrakisdimethylaminotitanium) gas, TDEAT (Ti [N (C 2 H 5 ) 2 ] 4 : tetrakisdiethylaminotitanium) gas, or the like may be used.
  • a semiconductor wafer has been described as an example of the object to be processed, but the semiconductor wafer includes a silicon substrate or a compound semiconductor substrate such as GaAs, SiC, GaN. Furthermore, the present invention is not limited to these substrates, and the present invention can also be applied to glass substrates, ceramic substrates, and the like used in liquid crystal display devices.

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Abstract

La présente invention porte sur un procédé de formation de film qui peut former un film mince sur un objet à la surface duquel est formée une couche isolante présentant une partie enfoncée. Le procédé est caractérisé en ce qu'il comprend les étapes suivantes : une étape de formation de film mince consistant à former un film de nitrure de titane mince sur la surface de l'objet comprenant la surface au niveau de la partie enfoncée par une technique de dépôt chimique en phase vapeur par plasma ; et une étape de nitruration consistant à soumettre le film mince à un traitement de nitruration à l'aide d'un plasma en présence d'azote gazeux pour nitrurer le film mince.
PCT/JP2010/051025 2009-01-28 2010-01-27 Procédé de formation de film, et appareil de formation de film par plasma WO2010087362A1 (fr)

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CN2010800059397A CN102301454A (zh) 2009-01-28 2010-01-27 成膜方法和等离子体成膜装置

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JP2009017320A JP2010177382A (ja) 2009-01-28 2009-01-28 成膜方法及びプラズマ成膜装置
JP2009-017320 2009-01-28

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Cited By (4)

* Cited by examiner, † Cited by third party
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CN105097646A (zh) * 2014-04-22 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN107644813A (zh) * 2017-09-14 2018-01-30 中国电子科技集团公司第十三研究所 氮化镓外延片的钝化方法
CN108807385A (zh) * 2017-04-28 2018-11-13 三星电子株式会社 用于制造半导体器件的方法
CN112391607A (zh) * 2019-08-19 2021-02-23 东京毅力科创株式会社 成膜方法和成膜装置

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JP2012174988A (ja) * 2011-02-23 2012-09-10 Sony Corp 接合電極、接合電極の製造方法、半導体装置、及び、半導体装置の製造方法
JP5808623B2 (ja) * 2011-09-07 2015-11-10 株式会社アルバック バリアメタル層の形成方法
CN104213097A (zh) * 2014-09-16 2014-12-17 朱忠良 铝合金的表面合金化工艺
CN110875181A (zh) * 2018-08-30 2020-03-10 长鑫存储技术有限公司 介电材料层及其形成方法、应用其的半导体结构
KR20220167017A (ko) * 2021-06-11 2022-12-20 주성엔지니어링(주) 배리어층의 형성 방법

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JPH08246152A (ja) * 1994-11-14 1996-09-24 Applied Materials Inc 化学気相堆積により堆積された改良窒化チタン層および製造法
JP2001507514A (ja) * 1995-06-05 2001-06-05 マテリアルズ リサーチ コーポレーション 窒化チタンのプラズマエンハンスアニール処理
JP2001508497A (ja) * 1997-01-31 2001-06-26 東京エレクトロン株式会社 バイアレベル用途に用いるための、チタン上にＴｉＮ膜を低温プラズマ増速化学蒸着する方法
JP2001319894A (ja) * 2000-01-26 2001-11-16 Applied Materials Inc 金属窒化物層のプラズマｃｖｄ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08246152A (ja) * 1994-11-14 1996-09-24 Applied Materials Inc 化学気相堆積により堆積された改良窒化チタン層および製造法
JP2001507514A (ja) * 1995-06-05 2001-06-05 マテリアルズ リサーチ コーポレーション 窒化チタンのプラズマエンハンスアニール処理
JP2001508497A (ja) * 1997-01-31 2001-06-26 東京エレクトロン株式会社 バイアレベル用途に用いるための、チタン上にＴｉＮ膜を低温プラズマ増速化学蒸着する方法
JP2001319894A (ja) * 2000-01-26 2001-11-16 Applied Materials Inc 金属窒化物層のプラズマｃｖｄ

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097646A (zh) * 2014-04-22 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN108807385A (zh) * 2017-04-28 2018-11-13 三星电子株式会社 用于制造半导体器件的方法
CN108807385B (zh) * 2017-04-28 2024-04-30 三星电子株式会社 用于制造半导体器件的方法
CN107644813A (zh) * 2017-09-14 2018-01-30 中国电子科技集团公司第十三研究所 氮化镓外延片的钝化方法
CN112391607A (zh) * 2019-08-19 2021-02-23 东京毅力科创株式会社 成膜方法和成膜装置

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JP2010177382A (ja) 2010-08-12
CN102301454A (zh) 2011-12-28

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