WO2009139210A1 - 高周波収納ケースおよび高周波モジュール - Google Patents

高周波収納ケースおよび高周波モジュール Download PDF

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Publication number
WO2009139210A1
WO2009139210A1 PCT/JP2009/053593 JP2009053593W WO2009139210A1 WO 2009139210 A1 WO2009139210 A1 WO 2009139210A1 JP 2009053593 W JP2009053593 W JP 2009053593W WO 2009139210 A1 WO2009139210 A1 WO 2009139210A1
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Prior art keywords
frequency
circuit
ground conductor
cavity
circuits
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PCT/JP2009/053593
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English (en)
French (fr)
Inventor
鈴木　拓也
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to EP09746417.6A priority Critical patent/EP2284881B1/en
Priority to JP2010511912A priority patent/JP5047357B2/ja
Priority to US12/918,239 priority patent/US8035994B2/en
Priority to CN2009801183562A priority patent/CN102027590B/zh
Publication of WO2009139210A1 publication Critical patent/WO2009139210A1/ja

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    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
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Definitions

  • the present invention relates to a high-frequency storage case and a high-frequency module that constitute a cavity that is a space electromagnetically shielded by a multilayer dielectric substrate on which a plurality of high-frequency circuits are mounted, and a shield cover material covering the multilayer dielectric substrate. Is.
  • a high-frequency package equipped with a high-frequency circuit that operates in a high-frequency band such as a microwave band or a millimeter-wave band, it is electrically shielded by a metal frame or the like in consideration of its operation stability, EMI (radioactive spurious) standard, etc. Often mounted in a cavity.
  • EMI radioactive spurious
  • the package assembly in order to avoid spatial interference between semiconductor chips having different functions, is divided into a plurality of compartments (cavities) by a seal ring or individual lid members, and the semiconductor chips function in the divided compartments. It is mounted separately and the semiconductor chips between the compartments are electrically connected using a feedthrough.
  • this conventional package structure has many problems related to cost and reliability, such as an increase in the number of members such as a seal ring and a lid, and complicated manufacturing processes such as solder joining to the package and welding of the lid.
  • the chip size is on the order of wavelengths (up to about 1 mm), so shielding and partitioning with cavity physical dimensions that are substantially cut-off cannot be realized.
  • An expensive absorber such as a magnetic material has to be used.
  • a simple package structure and module configuration capable of ensuring isolation even in a high frequency band such as a microwave band and a millimeter wave band have been desired.
  • the present invention has been made in view of the above, and provides a high-frequency storage case and a high-frequency module that can ensure spatial isolation between a plurality of high-frequency circuits with an inexpensive and simple configuration using a single cavity. Objective.
  • the present invention provides a high-frequency storage case for storing a plurality of high-frequency circuits mounted on a multilayer dielectric substrate, and is formed on at least the multilayer dielectric substrate.
  • a plurality of high-frequency circuits arranged in the signal propagation direction and a grounding conductor, and a shield cover material that spatially covers the plurality of high-frequency circuits, and an electromagnetic shield formed by electrically connecting the plurality of the high-frequency circuits.
  • a cavity having a length in a direction perpendicular to the direction in which the high-frequency circuit is disposed is shorter than 1 ⁇ 2 of the effective wavelength in the substrate of the first signal wave generated from the high-frequency circuit, and the high-frequency circuit are mounted
  • the waveguide opening and the short-circuited dielectric waveguide are provided, and the waveguide opening and the short-circuited dielectric waveguide operate as a reflection circuit for a signal propagating through the cavity.
  • spatial isolation between a plurality of high-frequency circuits can be ensured with an inexpensive and simple configuration using a single cavity.
  • FIG. 1 is a perspective view showing a high-frequency module according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing the high-frequency module according to the embodiment of the present invention.
  • FIG. 3 is a plan view showing the high-frequency module according to the embodiment of the present invention.
  • FIG. 4 is a diagram illustrating propagation characteristics in the cavity of the high-frequency module according to the embodiment.
  • FIG. 5 is a diagram illustrating propagation characteristics of the surface signal line of the high-frequency module according to the embodiment.
  • the high-frequency module 1 is equipped with a plurality of high-frequency circuits that operate in a high-frequency band such as a microwave band and a millimeter wave band.
  • the high-frequency module 1 is preferably applied to, for example, an FM-CW radar.
  • an oscillation circuit 10 that generates a high frequency signal having a frequency f0
  • an amplification circuit 11 that amplifies the output of the oscillation circuit 10
  • an output of the amplification circuit 11 are multiplied by N (N ⁇ 2).
  • a multiplication / amplification circuit 12 for amplifying and outputting a multiplication signal of frequency N ⁇ f0.
  • the high-frequency circuit is composed of a semiconductor element such as a field effect transistor or a high electron mobility transistor, or an MIC (microwave integrated circuit) or MMIC (monolithic microwave integrated circuit) configured by a semiconductor element and an external substrate such as a ceramic substrate. .
  • the shield cover material 3 spatially covers the high-frequency circuit and may be made of metal, or a metal layer may be formed on the inner wall surface.
  • a plurality of recesses (hereinafter referred to as IC mounting recesses) 6 for mounting a plurality of high-frequency circuits are formed on the multilayer dielectric substrate 2.
  • the IC mounting recess 6 is formed by forming a penetrating portion in the upper layer (first layer in the illustrated example) 2 a of the multilayer dielectric substrate 2.
  • the ground conductor 4 is formed on the bottom surface of the IC mounting recess 6.
  • the ground conductor 4 is a solid ground formed between the upper dielectric layer 2a and the lower dielectric layer 2b in the multilayer dielectric substrate 2, as shown in FIG.
  • high-frequency circuits such as an oscillation circuit 10, an amplification circuit 11, and a multiplication / amplification circuit 12 are mounted.
  • high-frequency circuits such as the oscillation circuit 10, the amplification circuit 11, and the multiplication / amplification circuit 12 are mounted on the ground conductor 4 formed on the bottom surface of the IC mounting recess 6, so that the shield cover
  • a surface layer ground conductor 7 is formed at a position where the shield cover material 3 contacts at least the surface of the multilayer dielectric substrate 2, and the surface layer ground conductor 7 and the ground conductor are formed.
  • 4 are connected by a plurality of through holes 8. That is, in this embodiment, the cavity 5 is also formed as a shielding space by the shield cover member 3, the surface layer ground conductor 7, the plurality of through holes 8, and the ground conductor 4.
  • the high frequency circuits are connected by wire bonding with wires 20 made of gold or the like. Instead of wires, other conductive connection members such as gold ribbons and solder balls may be used. Between the amplifying circuit 11 and the multiplying / amplifying circuit 12, as shown in FIG. 3, a wire 20 and further a microstrip line or a coplanar line formed on the surface dielectric layer 2a are not used. An electrical input / output connection is made by the signal line 21. On the surface layer of the multilayer dielectric substrate 2, conductor pads 22 for supplying a DC bias voltage or inputting / outputting a control signal between high frequency circuits are formed. In addition, although the conductor pad 22 and each high frequency circuit are connected by the wire, the illustration is abbreviate
  • the waveguide opening 30 as a pattern for removing the ground conductor 4 on which the high-frequency circuit is mounted. Is forming. Further, at the tip of the waveguide opening 30, a short-circuited dielectric that extends in the stacking direction of the multilayer dielectric substrate 2 and has a length of about 1 ⁇ 4 (an odd multiple of the effective wavelength ⁇ g in the substrate) of the signal wave. A body waveguide 40 is formed.
  • the dielectric waveguide 40 includes an inner-layer ground conductor 41 formed at a depth position of approximately ⁇ g / 4 (an odd multiple thereof) from the waveguide opening 30, a ground conductor 4 on which a high-frequency circuit is mounted, and an inner-layer ground conductor. And a dielectric waveguide having a short-circuited surface at the tip thereof.
  • the dielectric waveguide includes a through-hole (ground via) 42 that connects to the inner-layer grounding conductor 41 and a dielectric disposed in a portion surrounded by the inner-layer ground conductor 41 and the plurality of through-holes 42. Function as.
  • the oscillation circuit 10, the amplification circuit 11, the multiplication / amplification circuit 12 and the like are provided in the high-frequency storage case in which the single cavity 5 is formed by the multilayer dielectric substrate 2 and the shield cover member 3.
  • a plurality of high-frequency circuits that operate in a plurality of operating frequency bands are arranged in a signal transmission direction (one-dimensionally in a column) across the waveguide opening 30 and the dielectric waveguide 40 to form a high-frequency module. .
  • the oscillator 10 and the amplifier 11 that operate at the frequency f0 before the multiplication and the multiplication / amplification circuit 12 that operates at the frequency N ⁇ f0 after the multiplication are sandwiched between the waveguide opening 30 and the dielectric waveguide 40. , Separated.
  • other high-frequency circuits may be arranged around the high-frequency circuits arranged in a column (lateral direction), and the high-frequency circuits may be arranged two-dimensionally while being vertically long.
  • the cavity width L is not sufficiently smaller than about half of the wavelength corresponding to the operating frequency of the high frequency circuit (cutoff dimension).
  • the signal propagates spatially and causes malfunction (unnecessary oscillation, frequency fluctuation) of the high frequency circuit due to feedback and coupling.
  • the higher the frequency of the high-frequency signal to be handled the closer the above-mentioned cut-off dimension is to the physical size of the high-frequency circuit to be accommodated, so that spatial feedback and coupling are more likely to occur.
  • the cavity width L is the length of the cavity 5 along the direction perpendicular to the arrangement direction of the plurality of high frequency circuits.
  • the cavity width L is shorter than the dimension that is cut off with respect to the oscillator 10 and the amplifier 11 operating at the frequency f0 before multiplication, that is, the effective wavelength in the substrate of the signal wave of the frequency f0.
  • a dimension smaller than approximately 1 ⁇ 2 of ⁇ (for example, 70 to 80% of 1 ⁇ 2 of wavelength ⁇ ) is selected. Since such a dimension selection has a frequency of 1 / N or less as compared with the case of selecting a dimension to be cut off for the multiplication / amplification circuit 12 that operates at a frequency of N ⁇ f0 after multiplication, the cut-off dimension. Can be realized physically easily.
  • the frequency f0 and a signal in a frequency band lower than the frequency f0 cannot be propagated in the cavity 5, and thus the oscillator 10 and the amplifier 11 before multiplication are spatially isolated. Is ensured, and it is possible to prevent malfunction due to feedback and coupling of signals in the frequency f0 and a frequency band lower than the frequency f0.
  • ⁇ g / 4 of the dielectric waveguide 40 is also set so as to function as a reflective reactance circuit for the high frequency signal of the multiplied frequency N ⁇ f0 output from the multiplication / amplification circuit 12. That is, ⁇ g is a wavelength corresponding to a high-frequency signal having a frequency N ⁇ f0.
  • the waveguide opening 30 and the dielectric waveguide 40 function as a dielectric reflection stub for signals propagating through the cavity.
  • the space is fed back from the multiplication / amplification circuit 12 in the cavity 5, and the N-th harmonic signal coupled to the oscillator 10 and the amplifier 11 before multiplication can be suppressed, and malfunction of the oscillator and the amplifier can be prevented.
  • the dimensions of the waveguide opening 30 and the length of the short-circuited dielectric waveguide 40 are such that the higher-order mode resonance of the N-th harmonic signal occurs in the dielectric waveguide 40. It is desirable to select a dimension that does not occur (for example, less than ⁇ / 4 of the effective wavelength in the tube of the N harmonic signal). Further, it is desirable to arrange the waveguide opening 30 at a position where resonance does not occur in the target (multiplied) signal frequency band with the cavity wall.
  • the cavity width L is set to a dimension that is cut off with respect to the frequency f0 before multiplication, signals in the frequency f0 and a frequency band lower than the frequency f0 propagate in the cavity 5.
  • the waveguide opening 30 and the dielectric waveguide 40 that function as a reflective reactance circuit are provided for the high frequency signal of frequency 2 ⁇ f0 after multiplication, the high frequency of frequency 2 ⁇ f0 is provided. The signal is totally reflected and the pass characteristic is attenuated by 25 dB or more.
  • FIG. 5 shows the propagation characteristics of the surface signal line 21 in the high-frequency module shown in FIGS. 1 to 3, where x indicates reflection characteristics and ⁇ indicates pass characteristics.
  • the multiplier / amplifier circuit 12 is a circuit that inputs the signal of the frequency f0 output from the amplifier circuit 11 via the surface layer signal line 21 and amplifies the signal by multiplying it by N. Therefore, the surface layer signal line 21 has at least a frequency. Although it is necessary to have good pass characteristics with respect to the signal of f0, as shown in FIG. 5, as the propagation characteristics of the surface layer signal line 21, good pass characteristics are obtained over each frequency range.
  • the high-frequency storage case according to the present embodiment includes the waveguide opening 30 and the short-circuited dielectric waveguide 40, and the waveguide opening 30 and the short-circuited dielectric waveguide 40. Is operated as a reflection circuit for signals propagating through the cavity, so that a plurality of low-cost and simple configurations using a single cavity can be used without using expensive seal rings, lids, and feedthroughs. Spatial isolation between high-frequency circuits can be ensured.
  • the source oscillation chip and the multiplication chip are divided and laid out with the reflection circuit including the waveguide opening 30 and the short-circuited dielectric waveguide 40 interposed therebetween. Since isolation between chips can be ensured, spatial feedback of the transmission wave (multiplied wave) to the source oscillation chip can be suppressed. That is, an oscillator or the like can be expected to operate stably without being affected by the space load because its fundamental wave is cut off and the multiplied wave is cut off by the reflection circuit.
  • the oscillation circuit and the multiplication circuit are employed as the plurality of high-frequency circuits housed in the single cavity 5.
  • the operating frequency between the high-frequency circuits is a natural number multiple.
  • the first and second high-frequency circuits having different operating frequency bands are not limited to this, and are configured to be separated from each other with the reflection circuit including the waveguide opening 30 and the short-circuited dielectric waveguide 40 interposed therebetween. Also good.
  • the present invention is applied to the high frequency module configured to accommodate the high frequency circuit in the IC mounting recess 6 formed in the multilayer dielectric substrate 2.
  • the present invention can also be applied to a high-frequency module having a configuration in which a high-frequency circuit is mounted on the surface layer of a flat multilayer dielectric substrate 2 that does not have 6.
  • the cavity 5 is formed by the ground conductor formed on the surface layer of the multilayer dielectric substrate 2 on which the high-frequency circuit is mounted and the shield cover 3. Can do.
  • the high-frequency storage case of this embodiment is effective in securing isolation between stages of a multistage amplifier chip where spatial feedback becomes a problem due to cascade connection. That is, in this case, two or more amplifier circuits operating in the same frequency band are sandwiched in a single cavity 5 with a reflection circuit composed of a waveguide opening 30 and a short-circuited dielectric waveguide 40 interposed therebetween. By arranging them separately, it is possible to easily secure isolation between the amplifier circuits in which spatial feedback is a problem due to cascade connection, and anti-oscillation can be expected.
  • the high-frequency storage case and the high-frequency module according to the present invention are useful when a plurality of high-frequency circuits operating in different frequency bands are mounted.

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Abstract

　多層誘電体基板２に形成されて複数の高周波回路１０、１１，１２を搭載する接地導体４と、シールド蓋材３とを電気的に接続して構成したキャビティ５と、高周波回路１０、１１，１２を搭載する接地導体４上に形成され、キャビティ５に電気的に結合する導波管開口３０と、多層誘電体基板２の積層方向に形成され、導波管開口３０に接続された、信号波の基板内実効波長の略１／４の長さを有する先端短絡の誘電体導波管４０とを備え、単一キャビティを用いた安価かつ簡単な構成によって、複数の高周波回路間の空間アイソレーションを確保する。

Description

高周波収納ケースおよび高周波モジュール
　本発明は、複数の高周波回路が搭載される多層誘電体基板と、この多層誘電体基板を覆うシールド蓋材とによって電磁的にシールドされた空間であるキャビティを構成した高周波収納ケースおよび高周波モジュールに関するものである。
　マイクロ波帯、ミリ波帯などの高周波帯で動作する高周波回路が搭載される高周波パッケージにおいては、その動作安定性、ＥＭＩ（放射性スプリアス）規格などを考慮し、金属フレームなどにより電気的にシールドされたキャビティ内に搭載されることが多い。
　特許文献１においては、異なる機能の半導体チップ間の空間干渉を避けるために、パッケージアセンブリをシールリングや個別の蓋材によって複数の区画（キャビティ）に分割し、分割した各区画に半導体チップを機能別に搭載し、フィードスルーを用いて区画間の半導体チップを電気接続している。
特開平１０－４１４２１号公報
　しかしながら、この従来のパッケージ構造では、シールリング、蓋等の部材点数の増加や、パッケージへの半田接合、蓋の溶接等の製造工程が複雑化するなど、コスト、信頼性に関する問題が多い。また、ミリ波帯等の高周波帯では、チップサイズが波長オーダ（～1mm程度）になってくるため、実質的にカットオフとなるキャビティ物理寸法での遮蔽、区画が実現できなくなるため、抵抗体／磁性体等の高価な吸収材を用いざるを得なかった。このように、マイクロ波帯、ミリ波帯などの高周波帯でもアイソレーションが確保可能な単純な構造のパッケージ構造、モジュール構成が望まれていた。
　本発明は、上記に鑑みてなされたものであって、単一キャビティを用いた安価かつ簡単な構成によって、複数の高周波回路間の空間アイソレーションを確保できる高周波収納ケースおよび高周波モジュールを得ることを目的とする。
　上述した課題を解決し、目的を達成するために、本発明は、多層誘電体基板上に搭載する複数の高周波回路を収納する高周波収納ケースにおいて、少なくとも、多層誘電体基板に形成されて前記複数の高周波回路を信号伝搬方向に配列して搭載する接地導体と、前記複数の高周波回路を空間的に覆うシールド蓋材と、を電気的に接続して構成した電磁シールドによって形成され、かつ前記複数の高周波回路の配置方向と垂直となる方向の長さが、前記高周波回路から発生される第１の信号波の基板内実効波長の１／２より短い寸法を有するキャビティと、高周波回路を搭載する前記接地導体上に形成され、前記キャビティに電気的に結合する導波管開口と、前記導波管開口に接続され、多層誘電体基板の積層方向に形成された、前記高周波回路から発生される前記第１の信号波の周波数のＮ倍（Ｎ≧２）である第２の信号波の基板内実効波長の略１／４の長さを有する先端短絡の誘電体導波管とを備えることを特徴とする。
　この発明によれば、導波管開口および先端短絡の誘電体導波管を備え、この導波管開口および先端短絡の誘電体導波管をキャビティを伝搬する信号に対して、反射回路として動作させるようにしたので、単一キャビティを用いた安価かつ簡単な構成によって、複数の高周波回路間の空間アイソレーションを確保することができる。
図１は、この発明の実施の形態にかかる高周波モジュールを示す斜視図である。 図２は、この発明の実施の形態にかかる高周波モジュールを示す断面図である。 図３は、この発明の実施の形態にかかる高周波モジュール示す平面図である。 図４は、実施の形態の高周波モジュールのキャビティ内の伝搬特性を示す図である。 図５は、実施の形態の高周波モジュールの表層信号線路の伝搬特性を示す図である。
符号の説明
　１　高周波モジュール
　２　多層誘電体基板
　３　シールド蓋材
　４　接地導体
　５　キャビティ
　６　ＩＣ搭載凹部
　７　表層接地導体
　８　スルーホール
　１０　発振回路
　１１　増幅回路
　１２　逓倍・増幅回路
　２０　ワイヤ
　２１　表層信号線路
　２２　導体パッド
　３０　導波管開口
　４０　先端短絡誘電体導波管
　４１　内層接地導体
　４２　スルーホール
　以下に、本発明にかかる高周波収納ケース（或いは高周波パッケージ）および高周波モジュールの実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。
　図１～図３は、本発明にかかる高周波モジュールの実施の形態の構成を示す図である。高周波モジュール１には、マイクロ波帯、ミリ波帯などの高周波帯で動作する複数の高周波回路が搭載されており、この高周波モジュール１は、例えば、ＦＭ－ＣＷレーダに適用すると好適である。なお、通信用機器や、マイクロ波レーダ等に利用されても良い。
　この実施の形態においては、高周波回路として、周波数ｆ０の高周波信号を発生する発振回路１０と、発振回路１０の出力を増幅する増幅回路１１と、増幅回路１１の出力をＮ逓倍し（Ｎ≧２）、周波数Ｎ・ｆ０の逓倍信号を増幅して出力する逓倍・増幅回路１２などを搭載している。高周波回路は、電界効果トランジスタや高電子移動度トランジスタ等の半導体素子、或いは半導体素子およびセラミック基板等の外部基板により構成されたＭＩＣ（マイクロ波集積回路）やＭＭＩＣ（モノリシックマイクロ波集積回路）から成る。
　これらの高周波回路は、シールド蓋材３（図中では、蓋材の内壁のみを図示）、多層誘電体基板２などによって形成された気密でかつ電磁的に遮蔽された空間であるキャビティ５内に実装される。シールド蓋材３は、高周波回路を空間的に覆うものであり、金属によって構成してもよいし、内壁面に金属層を形成するようにしてもよい。多層誘電体基板２上には、複数の高周波回路を搭載するための複数の凹部（以下、ＩＣ搭載凹部という）６が形成されている。ＩＣ搭載凹部６は多層誘電体基板２の上位層（図の例では第１層）２ａに刳り貫き部を形成することによって形成される。ＩＣ搭載凹部６の底面には、その表面に接地導体４が形成されている。この実施の形態では、接地導体４は、図２に示すように、多層誘電体基板２における上位層の誘電体層２ａとその下層の誘電体層２ｂとの間に形成されたベタグランドであり、この接地導体４上に発振回路１０、増幅回路１１、逓倍・増幅回路１２などの高周波回路が搭載される。
　この実施の形態においては、ＩＣ搭載凹部６の底面に形成した接地導体４上に、発振回路１０、増幅回路１１、逓倍・増幅回路１２などの高周波回路を搭載するようにしているので、シールド蓋材３と接地導体４とを電気的に接続するために、シールド蓋材３が少なくとも多層誘電体基板２の表面と当接する箇所に表層接地導体７を形成し、この表層接地導体７と接地導体４とを複数のスルーホール８によって接続している。すなわち、この実施の形態においては、シールド蓋材３、表層接地導体７、複数のスルーホール８、接地導体４によって、遮蔽空間としてもキャビティ５を形成している。
　高周波回路間は、金などで構成されるワイヤ２０によって、ワイヤボンディング接続されている。ワイヤの代わりに、金リボンやはんだボールのような他の導電性接続部材を用いても良い。増幅回路１１と逓倍・増幅回路１２との間は、フィードスルーではなく、図３に示すように、ワイヤ２０、さらには表層の誘電体層２ａ上に形成されたマイクロストリップ線路やコプレーナ線路などの信号線路２１によって電気的な入出力接続がなされている。多層誘電体基板２の表層には、ＤＣバイアス電圧を供給したり、あるいは高周波回路間で制御信号を入出力するための導体パッド２２が形成されている。なお、導体パッド２２と各高周波回路との間はワイヤによって接続されるが、図１ではその図示を略している。
　ここで、周波数ｆ０で動作する増幅回路１１と、周波数Ｎ・ｆ０で動作する逓倍・増幅回路１２との間には、高周波回路が搭載される接地導体４の抜きパターンとしての導波管開口３０を形成している。さらに、導波管開口３０の先には、多層誘電体基板２の積層方向に延び、信号波の基板内実効波長λｇの略１／４（の奇数倍）の長さを有する先端短絡の誘電体導波管４０が形成されている。誘電体導波管４０は、導波管開口３０から略λｇ／４（の奇数倍）の深さ位置に形成された内層接地導体４１と、高周波回路が搭載される接地導体４と内層接地導体４１とを接続するスルーホール（グランドビア）４２と、これら内層接地導体４１および複数のスルーホール４２で囲まれた部分に配される誘電体によって構成され、先端に短絡面を有する誘電体導波路として機能する。
　このように本実施の形態においては、多層誘電体基板２とシールド蓋材３により単一のキャビティ５が形成された高周波収納ケース内に、発振回路１０、増幅回路１１、逓倍・増幅回路１２等の複数の動作周波数帯で動作する複数の高周波回路を導波管開口３０および誘電体導波管４０を挟んで信号伝送方向に（縦列一次元的に）配置し、高周波モジュールを形成している。また、逓倍前の周波数ｆ０で動作する発振器１０、増幅器１１と、逓倍後の周波数Ｎ・ｆ０で動作する逓倍・増幅回路１２とを、導波管開口３０および誘電体導波管４０を挟んで、分離配置している。なお、縦列に配列された高周波回路の周囲（横方向）に、他の高周波回路を配置して、縦長でありつつも、２次元的に高周波回路を配置しても良い。
　このように、キャビティ５内に高周波回路を信号伝送方向に配置する場合、高周波回路の動作周波数に対応する波長の略１／２（カットオフ寸法）よりも、キャビティ幅Ｌが十分に小さくないと、空間的に信号が伝搬してしまい、帰還・結合により高周波回路の誤動作（不要発振、周波数変動）を引き起こす。特に扱う高周波信号の周波数が高いほど、上記のカットオフ寸法は、収納する高周波回路の物理サイズに近接してくるため、空間帰還、結合が起こりやすくなる。なお、キャビティ幅Ｌとは、複数の高周波回路の配置方向に垂直な方向に沿ったキャビティ５の長さである。
　そこで、本実施の形態では、キャビティ幅Ｌは、逓倍前の周波数ｆ０で動作する発振器１０、増幅器１１等に対してカットオフとなる寸法より短い寸法、すなわち周波数ｆ０の信号波の基板内実効波長λの略１／２より小さい寸法（例えば波長λの１／２の７０～８０％）を選ぶ。このような寸法選択は、逓倍後のＮ・ｆ０の周波数で動作する逓倍・増幅回路１２に対してカットオフとなる寸法を選ぶ場合に比べ、周波数が1／Ｎ以下となるため、カットオフ寸法を物理的に容易に実現することができる。
　このようなキャビティ幅Ｌの選択により、周波数ｆ０および周波数ｆ０よりも低い周波数帯域の信号はキャビティ５内を伝搬することはできなくなり、これにより逓倍前の発振器１０、増幅器１１は空間的にアイソレーションが確保され、周波数ｆ０および周波数ｆ０よりも低い周波数帯域の信号の帰還・結合による誤動作を防ぐことが可能となる。
　つぎに、導波管開口３０の開口寸法は、逓倍・増幅回路１２から出力される逓倍後の周波数Ｎ・ｆ０の高周波信号に対して、キャビティ５に電気的に結合する寸法を選ぶ。また、誘電体導波管４０の長さλｇ／４も、逓倍・増幅回路１２から出力される逓倍後の周波数Ｎ・ｆ０の高周波信号に対して、反射リアクタンス回路として機能するように設定する。すなわち、λｇは、周波数Ｎ・ｆ０の高周波信号に対応する波長である。
　このような、導波管開口３０および誘電体導波管４０の寸法選択により、導波管開口３０および誘電体導波管４０がキャビティを伝搬する信号に対して、誘電体の反射スタブとして働き、キャビティ５内の逓倍・増幅回路１２から空間を帰還し、逓倍前の発振器１０、増幅器１１へ結合するＮ倍波信号を抑えることができ、発振器、増幅器の誤動作を防止することができる。
　なお、導波管開口３０の寸法および先端短絡誘電体導波管４０の長さ（図３に示した寸法Ｗ）は、誘電体導波管４０内でＮ倍波信号の高次モード共振が発生しない寸法（例えは、Ｎ倍波信号の管内実効波長のλ/4未満）を選ぶようにしたほうが望ましい。また、導波管開口３０は、キャビティ壁との間で、対象（逓倍）信号周波数帯で共振が発生しない位置に配置するようにしたほうが望ましい。
　図４は、図１～図３に示した高周波モジュールのキャビティ５内の伝搬特性を示すもので、×が反射特性を、○が通過特性を示している。Ｎ＝２としている。図４から判るように、キャビティ幅Ｌを逓倍前の周波数ｆ０に対してカットオフとなる寸法に設定しているので、周波数ｆ０および周波数ｆ０よりも低い周波数帯域の信号はキャビティ５内を伝搬することはできなくなり、また、逓倍後の周波数２・ｆ０の高周波信号に対して反射リアクタンス回路として機能する導波管開口３０および誘電体導波管４０を設けているので、周波数２・ｆ０の高周波信号に対しては全反射で、通過特性は２５ｄＢ以上減衰している。
　図５は、図１～図３に示した高周波モジュールにおいて、表層信号線路２１の伝搬特性を示すもので、×が反射特性を、○が通過特性を示している。逓倍・増幅回路１２は、増幅回路１１から出力される周波数ｆ０の信号を、表層信号線路２１を介して入力し、これをＮ逓倍して増幅する回路であるため、表層信号線路２１は少なくとも周波数ｆ０の信号に対し良好な通過特性を持つ必要があるが、図５に示すように、表層信号線路２１の伝搬特性としては、各周波数域に亘って良好な通過特性が得られている。
　このように本実施の形態にかかる高周波収納ケースによれば、導波管開口３０および先端短絡の誘電体導波管４０を備え、この導波管開口３０および先端短絡の誘電体導波管４０をキャビティを伝搬する信号に対して、反射回路として動作させるようにしたので、高価なシールリングや蓋材およびフィードスルーを用いることなく、単一キャビティを用いた安価かつ簡単な構成によって、複数の高周波回路間の空間アイソレーションを確保することができる。
　また、本実施の形態にかかる高周波モジュールによれば、導波管開口３０および先端短絡の誘電体導波管４０から成る反射回路を挟んで源振チップと逓倍チップを分割レイアウトすることで、各チップ間のアイソレーションが確保できるため、送信波（逓倍波）の源振チップへの空間帰還を抑圧できる。すなわち、発振器等は、自身の基本波はカットオフ、逓倍波は反射回路により遮断されているため、空間負荷の影響を受けない安定動作が期待できる。
　なお、上記実施の形態においては、単一のキャビティ５内に収納する複数の高周波回路として、発振回路と逓倍回路とを採用するようにしたが、各高周波回路間の動作周波数は、自然数倍に限るわけではなく、動作周波数帯が異なる第１、第２の高周波回路を導波管開口３０および先端短絡の誘電体導波管４０から成る反射回路を挟んで分離配置するように構成してもよい。
　また、上記実施の形態では、多層誘電体基板２内に形成したＩＣ搭載凹部６内に高周波回路を収容する構成の高周波モジュールに本発明を適用するようにしたが、本発明は、ＩＣ搭載凹部６を持たない平坦な多層誘電体基板２の表層に高周波回路を搭載するような構成の高周波モジュールにも適用することができる。このような平坦な表層の多層誘電体基板２をもつ高周波モジュールの場合、多層誘電体基板２の表層に形成されて高周波回路が搭載される接地導体とシールド蓋材３によってキャビティ５を形成することができる。
　また、本実施の形態の高周波収納ケースは、縦列接続により空間帰還が問題となる多段増幅器チップの段間のアイソレーションを確保する場合に有効である。すなわち、この場合は、単一のキャビティ５内に、同一周波数帯で動作する２つ以上の増幅回路をそれぞれ導波管開口３０および先端短絡の誘電体導波管４０から成る反射回路を挟んで分離配置することで、縦列接続により空間帰還が問題となる各増幅回路間のアイソレーションを簡易に確保することができ、発振防止が期待できる。
　以上のように、本発明にかかる高周波収納ケースおよび高周波モジュールは、異なる周波数帯で動作する複数の高周波回路を搭載する場合に有用である。

Claims (5)

  1. 　多層誘電体基板上に搭載する複数の高周波回路を収納する高周波収納ケースにおいて、
    　少なくとも、多層誘電体基板に形成されて前記複数の高周波回路を信号伝搬方向に配列して搭載する接地導体と、前記複数の高周波回路を空間的に覆うシールド蓋材と、を電気的に接続して構成した電磁シールドによって形成され、かつ前記複数の高周波回路の配置方向と垂直となる方向の長さが、前記高周波回路から発生される第１の信号波の基板内実効波長の１／２より短い寸法を有するキャビティと、
    　高周波回路を搭載する前記接地導体上に形成され、前記キャビティに電気的に結合する導波管開口と、
    　前記導波管開口に接続され、多層誘電体基板の積層方向に形成された、前記高周波回路から発生される前記第１の信号波の周波数のＮ倍（Ｎ≧２）である第２の信号波の基板内実効波長の略１／４の長さを有する先端短絡の誘電体導波管と、
    　を備えることを特徴とする高周波収納ケース。
  2. 　前記キャビティは、前記接地導体と、前記シールド蓋材と、前記多層誘電体基板の表面の前記シールド蓋材の当接面に形成される表層接地導体と、表層接地導体と前記複数の高周波回路を搭載する接地導体とを接続するスルーホールとを電気的に接続することにより構成される請求項１に記載の高周波収納ケース。
  3. 　前記誘電体導波管は、内層接地導体と、前記接地導体および内層接地導体に接続される複数のスルーホールとにより構成されることを特徴とする請求項１または２に記載の高周波収納ケース。
  4. 　請求項１～３の何れか一つに記載の高周波収納ケースと、
    　前記第１の信号波を発生する前記高周波回路としての発振回路と、前記発振回路から発生される第１の信号波をＮ逓倍し、前記第２の信号波を発生する前記高周波回路としての逓倍回路と、
    　を備え、前記発振回路と逓倍回路とを前記導波管開口を挟んで前記キャビティ内に分離配置したことを特徴とする高周波モジュール。
  5. 　請求項１～３の何れか一つに記載の高周波収納ケースと、
    　前記導波管開口および先端短絡誘電体導波管が反射回路として機能する信号周波数帯を増幅する、前記高周波回路としての２つ以上の増幅回路と、
    　を備え、前記各増幅回路を前記導波管開口を挟んで前記キャビティ内に分離配置したことを特徴とする高周波モジュール。
PCT/JP2009/053593 2008-05-12 2009-02-26 高周波収納ケースおよび高周波モジュール WO2009139210A1 (ja)

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US12/918,239 US8035994B2 (en) 2008-05-12 2009-02-26 High frequency storing case and high frequency module
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019009457A (ja) * 2014-08-26 2019-01-17 三菱電機株式会社 高周波モジュール

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150075347A (ko) * 2013-12-25 2015-07-03 가부시끼가이샤 도시바 반도체 패키지, 반도체 모듈 및 반도체 디바이스
JP2015149649A (ja) 2014-02-07 2015-08-20 株式会社東芝 ミリ波帯用半導体パッケージおよびミリ波帯用半導体装置
JP2015149650A (ja) 2014-02-07 2015-08-20 株式会社東芝 ミリ波帯用半導体パッケージおよびミリ波帯用半導体装置
CN104767010B (zh) * 2015-04-03 2019-01-22 京信通信技术(广州)有限公司 一体式微波通信器件及天线
US10375865B2 (en) * 2017-03-24 2019-08-06 Microsoft Technology Licensing, Llc Mechanically attached edge shield
CN112259532B (zh) * 2020-09-30 2022-12-13 中国电子科技集团公司第十三研究所 微波毫米波封装器件及其制作方法
CN115996535B (zh) * 2023-03-23 2023-08-08 成都雷电微力科技股份有限公司 一种Ka频段功放架构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441421A (en) 1987-08-04 1989-02-13 Kubota Ltd Engine cooling mechanism for tractor
JP2002299503A (ja) * 2001-03-30 2002-10-11 Nec Corp フリップチップ実装用基板
JP2005311337A (ja) * 2004-03-26 2005-11-04 Mitsubishi Electric Corp 高周波パッケージ、送受信モジュールおよび無線装置
JP2006253953A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd 通信用高周波モジュールおよびその製造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3863181A (en) * 1973-12-03 1975-01-28 Bell Telephone Labor Inc Mode suppressor for strip transmission lines
JP3638173B2 (ja) * 1996-03-27 2005-04-13 本田技研工業株式会社 マイクロ波回路用パッケージ
US5668408A (en) 1996-04-12 1997-09-16 Hewlett-Packard Company Pin grid array solution for microwave multi-chip modules
EP0874415B1 (en) * 1997-04-25 2006-08-23 Kyocera Corporation High-frequency package
TW473882B (en) * 1998-07-06 2002-01-21 Hitachi Ltd Semiconductor device
JP3538045B2 (ja) * 1998-12-09 2004-06-14 三菱電機株式会社 Ｒｆ回路モジュール
US6642808B2 (en) * 2000-05-30 2003-11-04 Kyocera Corporation High frequency package, wiring board, and high frequency module having a cyclically varying transmission characteristic
JP2001352206A (ja) * 2000-06-07 2001-12-21 Mitsubishi Electric Corp 高周波回路装置
JP3570359B2 (ja) * 2000-08-24 2004-09-29 三菱電機株式会社 高周波モジュール
JP2002164465A (ja) * 2000-11-28 2002-06-07 Kyocera Corp 配線基板、配線ボード、それらの実装構造、ならびにマルチチップモジュール
CN101820741A (zh) * 2001-12-14 2010-09-01 莱尔德技术公司 包括有损耗的介质的电磁干扰屏蔽件
US7276987B2 (en) * 2002-10-29 2007-10-02 Kyocera Corporation High frequency line-to-waveguide converter and high frequency package
FR2847723B1 (fr) * 2002-11-22 2006-02-03 United Monolithic Semiconduct Composant electronique en boitier pour applications a des frequences millimetriques
JP2004327641A (ja) * 2003-04-24 2004-11-18 Tdk Corp 電子部品モジュール
EP1729340B1 (en) * 2004-03-26 2017-09-06 Mitsubishi Denki Kabushiki Kaisha High frequency package, transmitting and receiving module and wireless equipment
JP4056500B2 (ja) * 2004-06-28 2008-03-05 三菱電機株式会社 伝送線路基板および半導体パッケージ
JP4575261B2 (ja) * 2005-09-14 2010-11-04 株式会社東芝 高周波用パッケージ
KR100817070B1 (ko) * 2006-10-30 2008-03-26 삼성전자주식회사 다중 그라운드 쉴딩 반도체 패키지, 그 패키지의 제조방법 및 그 그라운드 쉴딩을 이용한 노이즈 방지방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441421A (en) 1987-08-04 1989-02-13 Kubota Ltd Engine cooling mechanism for tractor
JP2002299503A (ja) * 2001-03-30 2002-10-11 Nec Corp フリップチップ実装用基板
JP2005311337A (ja) * 2004-03-26 2005-11-04 Mitsubishi Electric Corp 高周波パッケージ、送受信モジュールおよび無線装置
JP2006253953A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd 通信用高周波モジュールおよびその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2284881A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019009457A (ja) * 2014-08-26 2019-01-17 三菱電機株式会社 高周波モジュール

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