WO2009104599A1 - 電子装置、実装基板積層体及びそれらの製造方法 - Google Patents
電子装置、実装基板積層体及びそれらの製造方法 Download PDFInfo
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- WO2009104599A1 WO2009104599A1 PCT/JP2009/052687 JP2009052687W WO2009104599A1 WO 2009104599 A1 WO2009104599 A1 WO 2009104599A1 JP 2009052687 W JP2009052687 W JP 2009052687W WO 2009104599 A1 WO2009104599 A1 WO 2009104599A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09545—Plated through-holes or blind vias without lands
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09572—Solder filled plated through-hole in the final product
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10719—Land grid array [LGA]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/0455—PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
- H05K3/0082—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention is based on the priority claims of Japanese patent applications: Japanese Patent Application No. 2008-036084 (filed on Feb. 18, 2008) and Japanese Patent Application No. 2008-170908 (filed on Jun. 30, 2008). The entire contents of this application are incorporated herein by reference.
- the present invention relates to an electronic device in which an electronic element package is mounted on a mounting substrate and a manufacturing method thereof, and more particularly to an electronic device in which an electronic device package having an LGA (Land Grid Array) type electrode is mounted on a mounting substrate and a manufacturing method thereof.
- the present invention also relates to a mounting substrate laminate in which a plurality of mounting substrates are stacked and mounted, and a method for manufacturing the same.
- the paste-like cream solder is printed on the electrodes of the mounting substrate using a metal mask, and then the BGA is mounted. Thereafter, the mounting substrate on which the BGA is mounted is passed through a reflow furnace, whereby the solder balls of the cream solder and the BGA are heated and melted, and the BGA and the mounting substrate are physically and electrically connected.
- An LGA (Land Grid Array) having planar electrodes arranged in a grid as connection terminals is also known as an electronic element package that does not have solder balls as compared to BGA. According to the LGA, the mounting height can be reduced by an amount corresponding to the height of the solder ball compared to the BGA.
- Patent Document 1 BGA mounting methods are disclosed in Patent Document 1 and Patent Document 2, for example.
- thermosetting adhesion starts to be cured at a temperature higher than the melting point of the solder at a predetermined position between each pad of the printed board at the position of each through hole of the printed board.
- the BGA solder ball connected to the BGA pad and the through hole of the printed board are mounted so as to overlap, and by heating the BGA and the printed board, the solder ball flows into the through hole, The BGA pad and the printed board pad are soldered together, and the BGA body and the printed board substrate are joined together with an adhesive.
- a step of forming a wiring layer having an electrode portion on a sheet-like insulating substrate with a conductor, a part of the wiring layer, and a predetermined position of the electrode portion The process of providing via holes and through holes in the substrate, the process of placing one or more passive elements or active elements connected to the wiring layer, and filling the via holes or through holes with solder to form a sheet-like insulating substrate
- a BGA type active element is mounted by a step of forming on the built-in flexible circuit board and a step of integrally forming a plurality of component built-in flexible circuit boards by interposing a gap-filling insulating sheet.
- a plurality of wiring films are formed on one surface, and one wiring film is formed on the wiring film.
- a reinforcing ring is fixed, and a semiconductor chip is face-bonded to a region surrounded by the reinforcing ring in a state where each electrode is connected to an inner portion of the corresponding wiring film.
- Patent Documents 1 to 3 The entire contents disclosed in Patent Documents 1 to 3 are incorporated herein by reference. The following analysis is given from the perspective of the present invention.
- the BGA mounting method described in Patent Document 1 has an effect of improving reliability by applying an adhesive to a printed board, the adhesive spreads to the through-holes by heating in the reflow process, and the solder There is a risk of blocking the connection.
- the mounting method described in Patent Document 1 uses a thermosetting adhesive that begins to cure at a temperature higher than the melting point of the solder. If the printed board or BGA warps due to heating, The ball and the printed board do not come into contact with each other, and connection failure may occur.
- an electronic device in which an electronic element package is mounted on a first mounting board includes LGA (Land Grid Array) type LGA electrodes.
- the first mounting board includes a through hole having a conductor covering the inner wall.
- the electronic element package and the first mounting substrate are mounted such that at least a part of the opening of the through hole overlaps with the LGA electrode.
- the LGA electrode and the conductor in the through hole are electrically connected by a conductive material disposed in the through hole. At least a part of a region of the LGA electrode that does not overlap with the opening of the through hole is bonded to the first mounting substrate via an adhesive.
- the electronic device further includes a second mounting substrate having a substrate electrode electrically connected to the through hole conductor.
- the first mounting substrate and the second mounting substrate are mounted such that at least a part of the opening of the through hole overlaps the substrate electrode.
- the substrate electrode and the conductor in the through hole are electrically connected by a conductive material disposed in the through hole. At least a portion of the substrate electrode that does not overlap with the opening of the through hole is bonded to the first mounting substrate via an adhesive.
- the area of the LGA electrode or the LGA electrode and the substrate electrode is larger than the opening area of the through hole on the side facing the LGA electrode or the LGA electrode and the substrate electrode.
- an electronic device in which an electronic element package is mounted on a first mounting substrate includes LGA (Land Grid Array) type LGA electrodes.
- the first mounting board includes a through hole having a conductor covering the inner wall. The area of the LGA electrode is smaller than the opening area of the through hole on the side facing the LGA electrode.
- the electronic device package and the first mounting substrate are mounted such that the LGA electrode is included in the opening of the through hole.
- the LGA electrode and the conductor in the through hole are electrically connected by a conductive material disposed in the through hole.
- the upper surface of the LGA electrode facing the first mounting substrate exists in the through hole. Of the region where the electronic element package and the first mounting substrate face each other, an adhesive is interposed in a region other than the opening of the through hole.
- the electronic device further includes a second mounting substrate having a substrate electrode electrically connected to the through hole conductor.
- the area of the substrate electrode is smaller than the opening area of the through hole on the side facing the substrate electrode.
- the first mounting substrate and the second mounting substrate are mounted such that the substrate electrode is included in the opening of the through hole.
- the substrate electrode and the conductor in the through hole are electrically connected by a conductive material disposed in the through hole.
- the upper surface of the substrate electrode facing the first mounting substrate exists in the through hole.
- an adhesive is present in a region other than the opening of the through hole.
- the LGA electrode of the electronic element package and the substrate electrode of the second mounting substrate are arranged on the same plane.
- the second mounting board has a through hole or a notch.
- the electronic device package is disposed in the through hole or the notch.
- the electronic element package and the second mounting substrate are bonded with resin.
- At least one electronic element is mounted on the second mounting board.
- the LGA electrode or the LGA electrode and the substrate electrode are covered with a conductive material.
- the first mounting substrate is an LGA electrode or an LGA electrode on the electronic device package or the first mounting substrate surface facing the electronic device package and the second mounting substrate.
- a conductor connected to the conductor of the through hole facing the substrate electrode is provided.
- the LGA electrode or the LGA electrode and the substrate electrode at least a part of the region that does not overlap with the opening of the through hole is bonded to the conductor on the first mounting substrate surface via an adhesive.
- the first mounting substrate is formed on the first mounting substrate surface facing the electronic element package, and the LGA electrode or the through hole conduction facing the LGA electrode and the substrate electrode. There is no conductor connected to the body.
- the electronic device package or the electronic device package and the region where the second mounting substrate and the first mounting substrate face each other are bonded to a region other than the through-hole opening.
- An agent is present.
- the adhesive is a photosensitive resin.
- the first mounting board does not have optical transparency with respect to the electronic element package or the electronic element package and the second mounting board other than through holes.
- the first mounting board has at least a part of the electronic device package or the light non-transmissive layer that blocks light from the electronic device package and the second mounting board.
- the conductive material is a first through the through hole, opposite to the first mounting board surface facing the electronic element package or the electronic element package and the second mounting board. It is continuously formed on the mounting substrate surface.
- a mounting substrate stack including a first mounting substrate and a second mounting substrate that is stacked and mounted on the first mounting substrate.
- the second mounting substrate has a planar electrode.
- the first mounting substrate has a through hole having a conductor covering the inner wall.
- the first mounting substrate and the second mounting substrate are mounted such that at least a part of the opening of the through hole overlaps with the planar electrode.
- the planar electrode and the through hole conductor are electrically connected by a conductive material disposed in the through hole. At least a portion of the planar electrode that does not overlap with the opening of the through hole is bonded to the first mounting substrate via an adhesive.
- a mounting substrate stack including a first mounting substrate and a second mounting substrate stacked and mounted on the first mounting substrate.
- the second mounting substrate has a planar electrode.
- the first mounting substrate has a through hole having a conductor covering the inner wall.
- the area of the planar electrode is smaller than the opening area of the through hole on the side facing the planar electrode.
- the first mounting substrate and the second mounting substrate are mounted such that the planar electrode is included in the opening of the through hole.
- the planar electrode and the through hole conductor are electrically connected by a conductive material disposed in the through hole.
- the upper surface of the planar electrode facing the first mounting substrate exists in the through hole.
- an adhesive is present in a region other than the opening of the through hole.
- the adhesive is a photosensitive resin.
- the first mounting board does not have optical transparency with respect to the second mounting board except for the through holes.
- a method for manufacturing an electronic device in which an electronic element package is mounted on a first mounting substrate.
- An adhesive placement step of placing an adhesive on at least a part of the electronic device package surface on which the LGA (Land Grid Array) type LGA electrode is formed is included.
- a bonding step is included in which the first mounting substrate having a through hole having a conductor on the inner wall and the electronic element package are stacked such that at least a part of the opening of the through hole overlaps the LGA electrode.
- An adhesive removing step of removing the adhesive present in the through hole so that at least a part of the LGA electrode is exposed at the opening of the through hole is included.
- a conductive material supplying step of supplying a conductive material to the through hole from the opening opposite to the opening of the through hole facing the LGA electrode is included.
- An electrical connection step of moving the conductive material to the exposed surface of the LGA electrode and electrically connecting the LGA electrode and the conductor of the through hole by the conductive material is included.
- a method for manufacturing an electronic device is provided.
- An electronic device package having an LGA (Land Grid Array) type LGA electrode, and a second mounting substrate on which at least one electronic device is mounted and having a planar electrode, the LGA electrode and the planar electrode face the adhesive plate.
- a positioning step of positioning by bonding to the adhesive plate is included.
- a joining step of joining the electronic element package and the second mounting substrate with a resin is included.
- a removal step of removing the electronic device package and the second mounting substrate from the adhesive plate is included.
- An adhesive placement step of placing an adhesive on at least a part of the electronic device package surface on which the LGA electrode is formed and on the second mounting substrate on which the planar electrode is formed is included.
- a first mounting board having at least one through hole having a conductor on the inner wall, an electronic element package, and a second mounting board are stacked so that at least a part of the opening of the through hole overlaps with the LGA electrode and the planar electrode.
- a joining step is included.
- An adhesive removing step of removing the adhesive existing in the through hole so that at least a part of the LGA electrode and the planar electrode is exposed at the opening of the through hole is included.
- a conductive material supply step of supplying a conductive material to the through hole from the opening opposite to the opening of the through hole facing the LGA electrode and the planar electrode is included.
- An electrical connection step is included in which the conductive material is moved to the exposed surfaces of the LGA electrode and the planar electrode, and the LGA electrode and planar electrode are electrically connected to the conductor of the through hole by the conductive material.
- the area of the LGA electrode or LGA electrode and the planar electrode is larger than the opening area of the through hole on the side facing the LGA electrode or LGA electrode and planar electrode.
- the bonding step at least a part of the LGA electrode or the LGA electrode and the planar electrode that does not overlap with the opening of the through hole is bonded to the first mounting substrate via an adhesive.
- the area of the LGA electrode or LGA electrode and the planar electrode is smaller than the opening area of the through hole on the side facing the LGA electrode or LGA electrode and the planar electrode.
- the bonding step at least a part of the LGA electrode or the LGA electrode and the planar electrode facing the first mounting substrate is inserted into the through hole.
- the adhesive is a photosensitive resin.
- the adhesive removal step includes an exposure step of exposing the adhesive in the through hole. After the exposure step, a development step of removing the adhesive in the through hole with a developer is included.
- the first mounting board does not have optical transparency with respect to the electronic element package or the electronic element package and the second mounting board except for the through holes.
- the exposure step only the adhesive in the through hole is exposed from the opening of the through hole using the first mounting substrate as a mask.
- the conductive material is cream solder.
- the LGA electrode or the LGA electrode and the planar electrode are electrically connected to the through hole conductor by heating and melting the conductive material.
- a method for manufacturing a mounting substrate laminate is provided.
- An adhesive placement step of placing an adhesive on at least a part of the second mounting substrate surface on which the planar electrode is formed is included.
- a joining step of laminating a first mounting substrate having a through hole having a conductor on the inner wall and a second mounting substrate so that at least a part of the opening of the through hole overlaps with the planar electrode is included.
- An adhesive removing step of removing the adhesive present in the through hole so that at least a part of the planar electrode is exposed at the opening of the through hole is included.
- a conductive material supplying step of supplying a conductive material to the through hole from the opening opposite to the opening of the through hole facing the planar electrode is included.
- An electrical connection step is included in which the conductive material is moved to the exposed surface of the planar electrode, and the planar electrode and the conductor in the through hole are electrically connected by the conductive material.
- the present invention has at least one of the following effects.
- the electronic device there is no need to interpose a conductive material between the LGA electrode of the electronic device package and the second substrate electrode of the second mounting substrate and the first substrate electrode of the first mounting substrate.
- the distance between the second mounting substrate and the first mounting substrate can be shortened, whereby the electronic device can be thinned.
- the electronic device can be further thinned. it can.
- the LGA electrode and the second substrate electrode are covered with a conductive material.
- the connection portion between the conductive material and the LGA electrode is not easily broken, and the connection reliability can be further improved.
- the electronic element package, the second mounting board, and the first mounting board are bonded together in advance before the electrical connection by the conductive material, the warp of the first mounting board during the heat treatment is performed. Can be suppressed. Thereby, the reliability of the electrical connection between the electronic element package and the second mounting board and the first mounting board can be improved.
- the adhesive in the through hole since only the adhesive in the through hole is removed, parts other than the through hole opening (for example, including the periphery of the through hole opening) are joined by the adhesive.
- the bondability between the two mounting substrate and the first mounting substrate can be made higher.
- the conductive material for electrically connecting the LGA electrode and the second substrate electrode and the conductor on the inner wall of the through hole is disposed on the surface opposite to the bonding surface between the electronic element package and the second mounting substrate.
- the conductive material on the opposite surface functions as a stopper, and even when the first mounting board is bent or stress due to dropping is applied, the LGA It is possible to ensure electrical connection between the electrode and the second substrate electrode and the through-hole conductor (for example, preventing the conductive material from coming off).
- the LGA electrode and the second substrate electrode can be electrically connected to the through hole conductor even if the amount of the conductive material supplied to the plurality of through holes is not constant.
- the electronic element package and the second mounting board are not stacked.
- wiring can be routed on the second mounting board, and the first mounting board needs to be thick. There is no. Thereby, the electronic device can be thinned.
- the electronic device package and the second mounting substrate are joined with a resin to reduce the impact and stress applied to the electrical connection portion between the first mounting substrate, the electronic device package, and the second mounting substrate. Connection reliability can be improved.
- the mounting substrate laminate can also be thinned.
- FIG. 1 is a schematic cross-sectional view of an electronic device according to a first embodiment of the present invention.
- FIG. 3 is a schematic process diagram for explaining the electronic device manufacturing method according to the first embodiment of the present invention.
- FIG. 6 is a schematic cross-sectional view of an electronic device according to a second embodiment of the present invention.
- FIG. 6 is a schematic cross-sectional view of an electronic device according to a third embodiment of the present invention.
- FIG. 6 is a schematic cross-sectional view of an electronic device according to a fourth embodiment of the present invention.
- FIG. 9 is a schematic cross-sectional view of an electronic device according to a fifth embodiment of the invention.
- FIG. 10 is a schematic cross-sectional view of an electronic device according to a sixth embodiment of the present invention.
- FIG. 10 is a schematic cross-sectional view of an electronic device according to a sixth embodiment of the present invention.
- FIG. 10 is a schematic cross-sectional view of an electronic device according to a seventh embodiment of the present invention.
- FIG. 10 is a schematic sectional view of an electronic device according to an eighth embodiment of the present invention.
- FIG. 12 is a schematic plan view of the electronic device package, the second mounting substrate, and the electronic device shown in FIG. 11. Schematic process drawing for explaining a method for manufacturing an electronic device according to a tenth embodiment of the present invention.
- FIG. 1 is a schematic cross-sectional view of an electronic device according to the first embodiment of the present invention.
- the electronic device 1 includes an electronic element package 2 in which electronic elements are packaged, and a mounting substrate 4 on which the electronic element package 2 is mounted.
- the electronic element package 2 is an LGA type package having a flat LGA electrode 3.
- an electronic element (not shown) in the electronic element package 2
- various electronic elements can be used.
- an active element such as a semiconductor element and a passive element such as a chip capacitor can be applied.
- the surface area of the LGA electrode 3 on the surface facing the mounting substrate 4 is equal to or larger than the opening area of the through hole 6 of the mounting substrate 4.
- the mounting substrate 4 penetrates the substrate electrode (land) 5 formed on the substrate surface and the substrate electrode 5, is electrically connected (connected) to the substrate electrode 5, and a conductor covering the inner wall (for example, A through hole 6 having a metal plating (for example, Cu plating) of 5 ⁇ m to 30 ⁇ m is provided.
- a flexible substrate can be used as the mounting substrate 4, for example.
- the size of the substrate electrode 5 of the mounting substrate 4 is preferably 0.15 mm to 0.3 mm. This is because if the size of the substrate electrode 5 is too large, a short circuit between adjacent electrodes is likely to occur, and if the size of the substrate electrode 5 is too small, a connection failure is likely to occur due to misalignment or the like.
- the mounting substrate 4 does not have optical transparency with respect to the electronic element package 2 except for the through hole 6.
- the mounting substrate 4 is light transmissive, for example, as a flexible substrate
- at least a light transmissive portion of the mounting substrate 4 is attached to the electronic element package.
- a light non-transmissive layer 7 for shielding light is provided.
- a light non-transmissive layer 7 is formed on a surface other than the substrate electrode 5 and the through-hole, which is not opposed to the electronic element package 2.
- the light non-transmissive layer 7 can be formed by, for example, applying a silver paste on the mounting substrate 4, but the material and the forming method are not limited to this, and the mounting substrate 4 is made light non-transmissive. If it can be applied, various materials and forming methods can be selected.
- the electronic element package 2 is arranged so that the LGA electrode 3 of the electronic element package 2 and the substrate electrode 5 of the mounting substrate 4 face each other, in particular, so that at least a part of the opening of the through hole 6 covers the LGA electrode 3. It is mounted on the mounting substrate 2.
- the through hole 6 is filled with a conductive material 9, and the LGA electrode 3 of the electronic element package 2 and the inner wall of the through hole 6 are electrically and physically connected by the conductive material 9.
- the conductive material 9 for example, a solder (for example, SnAgCu-based lead-free solder), a conductive adhesive containing a conductive filler, or the like can be used.
- the conductive material 9 is continuously formed from the through hole 6 (LGA electrode 3) on the surface of the mounting substrate 4 opposite to the surface facing the electronic element package 2.
- the adhesive 8 is disposed between the electronic element package 2 and the mounting substrate 4 except for the opening region of the through hole 6, and the electronic element package 2 and the mounting substrate 4 are joined by the adhesive 8.
- the LGA electrode 3 is larger than the opening area of the through hole 6, and the surface of the LGA electrode 3 that does not overlap the opening of the through hole 6 is bonded to the substrate electrode 5 with an adhesive.
- the adhesive 8 for example, a positive photosensitive resin can be used.
- the distance between the LGA electrode 3 of the electronic element package 2 and the substrate electrode 5 of the mounting substrate 4 is preferably 1 ⁇ m to 20 ⁇ m.
- a flexible substrate having a thickness of 50 ⁇ m can be used as the mounting substrate 4, and a silver paste having a thickness of 12 ⁇ m can be coated on the flexible substrate as the light non-transmissive layer 7.
- a semiconductor package in which a semiconductor element is packaged can be used as the electronic element package 2.
- the diameter of the LGA electrode 3 of the semiconductor package can be set to ⁇ 0.25 mm
- the diameter of the substrate electrode 5 of the flexible substrate can be set to ⁇ 0.25 mm
- the diameter of the through hole 6 can be set to ⁇ 0.15 mm.
- FIG. 2 is a schematic process diagram for explaining the method for manufacturing the electronic device according to the first embodiment of the present invention.
- the positive photosensitive resin adhesive 8 is disposed on the LGA-type electronic element package 2 (including the LGA electrode 3) (FIG. 2A; adhesive placement step).
- the thickness of the adhesive 8 is preferably 10 ⁇ m to 50 ⁇ m.
- the adhesive 8 may be a liquid type or a film type.
- the mounting substrate 4 and the electronic element package 2 are laminated so that at least a part of the opening of the through hole 6 overlaps with the LGA electrode 3, and then heated and bonded (FIG. 2B; bonding process). .
- the adhesive 8 is also present inside the through hole 6.
- the heating conditions time, temperature, etc. may be set appropriately according to the type of adhesive used. For example, in the case of a positive photosensitive resin, heating is performed at 130 ° C. for 10 minutes.
- the mounting substrate 4 substrate electrode 5 in FIG. 2
- the adhesive 8 Is done.
- the mounting substrate 4 is inserted so that at least a part of the LGA electrode 3 is inserted into the through hole 6. And the electronic device package 2 are stacked.
- the mounting substrate 4 that does not have optical transparency or the mounting substrate 4 itself has optical transparency
- the mounting substrate 4 and the light non-transparent layer 7 are used as a mask.
- the photosensitive resin that is the adhesive 8 inside the through hole 6 is exposed (exposure process).
- the exposed photosensitive resin inside the through hole 6 is dissolved and removed with a developer (development process) to expose the LGA electrode 3 of the electronic element package 2 (FIG. 2 (c); adhesive removal process).
- the exposure conditions irradiation wavelength, exposure energy amount, etc.
- the developer is not particularly limited, and can be appropriately selected according to the photosensitive resin to be used.
- a photosensitive resin is used as the adhesive, but the adhesive and the method for removing the adhesive are not limited to the above forms, and the adhesive in the through hole 6 in the adhesive removal step. Any adhesive and its removal method may be used as long as they can be removed.
- the conductive material 9 is supplied to the through hole 6 of the mounting substrate 4 (FIG. 2D; conductive material supply step).
- a method for supplying the conductive material 9 for example, when cream solder is used as the conductive material 9, a printing method using a metal mask can be selected.
- the thickness of the metal mask is appropriately set according to the opening area (diameter) of the through hole 6. For example, when the diameter of the through hole is 0.1 mm, the thickness of the metal mask is preferably 0.05 mm.
- the conductive material 9 is melted and filled in the through hole 6 and moved to the LGA electrode 3 of the electronic element package 2, and the conductors on the inner walls of the LGA electrode 3 and the through hole 6 of the electronic element package 2 are transferred.
- the conductive material 9 (FIG. 2E; electrical connection step).
- the conductive material 9 may be heated by passing the mounting substrate 4 on which the electronic element package 2 is mounted through a reflow furnace.
- the electronic device 1 can be manufactured through the above steps.
- the electronic device and the manufacturing method thereof since it is not necessary to interpose a conductive material between the LGA electrode and the substrate electrode of the electronic element package, the distance between the electronic element package and the mounting substrate is shortened. (For example, 10 ⁇ m), which can make the electronic device thinner. Further, the electronic device can be further reduced in thickness by reducing the area of the LGA electrode with respect to the opening area of the through hole and not forming the substrate electrode (land) of the mounting substrate.
- a conductive material for electrically connecting the LGA electrode and the conductor on the inner wall of the through hole is also connected to the surface opposite to the bonding surface with the electronic element package.
- the conductive material on the opposite surface functions as a stopper, and even when the mounting substrate is bent or stress is applied due to dropping, the conductive material of the LGA electrode and the through hole is conductive. It is possible to ensure electrical connection with the body (for example, preventing the conductive material from coming off).
- FIG. 3 is a schematic cross-sectional view of an electronic device according to the second embodiment of the present invention.
- the mounting substrate 4 is formed around the opening of the through hole 6 on the mounting substrate surface facing the electronic element package 2 and is connected to the conductor of the through hole 6.
- the mounting substrate 14 does not have a conductor corresponding to the substrate electrode 5 in the first embodiment.
- the electronic device 11 includes an electronic element package 2 and a mounting substrate 14 on which the electronic element package 2 is mounted. Since no substrate electrode is formed on the surface of the mounting substrate 14 facing the electronic element package 2, the LGA electrode 3 of the electronic element package 2 has an adhesive 8 other than the through holes (openings and conductors) 16. Thus, it is bonded to the substrate (resin) of the mounting substrate 14. Since the LGA electrode 3 and the conductor of the through hole 6 are electrically connected by the conductive material 9 through the opening of the through hole 6 (that is, the conductor of the through hole 6 is substantially an electrode), Even if a so-called land is not formed on the surface of the mounting substrate 14, electrical connection between the electronic element package 2 and the mounting substrate 14 can be ensured.
- a suitable method can be selected as appropriate.
- the wiring layer of the mounting substrate 14 is etched, the wiring layer (substrate electrode) around the opening of the through hole 6 may be removed by etching, or after the mounting substrate 14 is fabricated, a portion corresponding to the substrate electrode May be removed mechanically (for example, removed by grinding).
- the thickness of the electronic device is further reduced by an amount corresponding to the thickness of the mounting electrode. can do.
- FIG. 4 is a schematic cross-sectional view of an electronic device according to the third embodiment of the present invention.
- the LGA electrode 3 of the electronic device package 2 has a surface area that is equal to or larger than the opening area of the through hole 6 of the mounting substrate 4.
- the LGA electrode 23 has a surface area smaller than the opening area of the through hole 6 of the mounting substrate 4.
- the electronic device 21 includes an electronic element package 22 and a mounting substrate 4 on which the electronic element package 22 is mounted.
- the LGA electrode 23 of the electronic element package 22 is included in the opening of the through hole 6, and the upper surface of the LGA electrode 23 facing the electronic element package 22 exists in the through hole 6. Accordingly, the upper surface and the side surface of the LGA electrode 23 are covered with the conductive material 9 and are electrically connected to the conductor of the through hole 6.
- the substrate electrode 5 of the mounting substrate 4 faces a region other than the LGA electrode 23 of the electronic element package 22 and is bonded via an adhesive 8.
- the diameter of the substrate electrode 5 of the mounting substrate 4 is ⁇ 0.25 mm and the opening diameter of the through hole 6 is ⁇ 0.15 mm
- the diameter of the LGA electrode 23 of the electronic element package 22 can be ⁇ 0.1 mm.
- the thickness of the electronic device can be further reduced by the thickness of the LGA electrode of the electronic element package inserted into the through hole. Moreover, since the LGA electrode is covered with a conductive material, the reliability against thermal stress can be improved.
- FIG. 5 is a schematic cross-sectional view of an electronic device according to the fourth embodiment of the present invention.
- the fourth embodiment is a combination of the second embodiment and the third embodiment.
- the electronic device 31 includes an electronic element package 22 and a mounting substrate 14 on which the electronic element package 22 is mounted.
- the area of the surface facing the mounting substrate 14 of the LGA electrode 23 of the electronic element package 22 is smaller than the opening area of the through hole 16 as in the third embodiment, and a part of the upper side of the LGA electrode 23 is the through hole 16. Is inserted inside.
- the LGA electrode 23 is covered with the conductive material 9 and is electrically connected to the conductor of the through hole 16.
- the mounting substrate 14 does not have a conductor corresponding to the substrate electrode on the surface facing the electronic element package 22, and the region of the mounting substrate 14 other than the opening of the through hole 16. Are bonded to the region of the electronic element package 22 other than the LGA electrode 23 via the adhesive 8.
- the thickness of the electronic device can be further reduced by the thickness of the LGA electrode inserted into the through hole and the thickness of the substrate electrode on the mounting substrate surface.
- FIG. 6 is a schematic cross-sectional view of an electronic device according to the fifth embodiment of the present invention.
- the through hole 46 of the mounting substrate 44 is formed in a tapered shape.
- the electronic device 41 includes an electronic element package 22 and a mounting substrate 44 on which the electronic element package 22 is mounted.
- the through hole 46 of the mounting substrate 44 has a truncated cone shape that decreases in diameter toward the electronic element package 22.
- the diameter of the opening facing the electronic element package 22 can be set to ⁇ 0.15 mm, and the diameter of the opening on the opposite side (conductive material 9 supply side surface) can be set to ⁇ 0.2 mm.
- the opening diameter of the through hole on the conductive material supply side is large, the filling property of the conductive material into the through hole can be improved.
- FIG. 6 illustrates the electronic device package according to the third embodiment, it is needless to say that the electronic device package according to the first embodiment can be applied. Further, in FIG. 6, a mounting substrate having a substrate electrode on the mounting substrate surface is illustrated, but a mounting substrate having no substrate electrode (so-called land) on the mounting substrate surface can be applied as in the second embodiment. It goes without saying that.
- other forms can be similar to those of the electronic device in the first embodiment.
- FIG. 7 is a schematic cross-sectional view of an electronic device according to the sixth embodiment of the present invention.
- the conductive material 9 is filled in the entire through holes 6, 16, and 46.
- the conductive material 9 only needs to be filled in a part of the through hole 6.
- the through hole supplied with the conductive material 9 that fills a part of the through hole 6 may be mixed in the same mounting board. That is, the amount of the conductive material may not be uniform in the plurality of through holes in one electronic device. For example, when supplying a paste-like conductive material by printing, if the LGA electrode and the conductor of the through hole are electrically connected, the printing amount may vary.
- FIG. 8 shows a schematic cross-sectional view of an electronic device according to the seventh embodiment of the present invention
- FIG. 9 shows a schematic cross-sectional view of the electronic device according to the eighth embodiment of the present invention.
- the light non-transmissive layer 7 provided when the mounting substrate has light transmittance is formed on the mounting substrate surface opposite to the surface facing the electronic element package.
- the light non-transmissive layer is formed at other locations.
- the light non-transmissive layer 67 is formed on the surface of the mounting substrate 64 facing the electronic element package 2, and is bonded to the electronic element package 2 by the adhesive 8. Has been.
- the light non-transmissive layer 77 is formed in the mounting substrate 74.
- the light non-transparent layer may be formed on any part of the mounting substrate as shown in FIGS. 1 to 9 when the mounting substrate has optical transparency.
- the light non-transmissive layer may be formed only in the portion having light transparency.
- FIGS. 8 and 9 have been described based on the first embodiment shown in FIG. 1. However, the seventh embodiment and the eighth embodiment can also be applied to the second to sixth embodiments. Needless to say.
- FIG. 10 the schematic sectional drawing of the mounting board
- the electrical connection between the electronic element package and the mounting substrate has been described.
- the above embodiment can also be applied to the stacked mounting of the mounting substrate and the mounting substrate.
- the mounting substrate laminate 101 includes a first mounting substrate 4 and a second mounting substrate 102.
- the form of the first mounting board 4 is the same as the form of the mounting board 4 in the first embodiment.
- the second mounting substrate 102 has a second substrate electrode 103 which is a planar electrode for electrically connecting to the conductor (through hole 6) of the first mounting substrate 4.
- connection form and manufacturing method of the first mounting board 4 and the second mounting board 102 in the mounting board laminate 101 are the same as the first mounting board 4 in the first embodiment except that the electronic device package is replaced with the second mounting board.
- the connection form and the manufacturing method of the electronic element package 2 are the same, and the description of the first embodiment is cited and the description thereof is omitted. Thereby, the mounting substrate stack 101 can be thinned.
- the mounting substrate laminate according to the ninth embodiment shown in FIG. 10 has been described based on the first embodiment. However, the connection form, the mounting substrate form, and the like in the second to eighth embodiments are also described. It can be applied to the mounting substrate laminate according to the ninth embodiment.
- FIG. 11 is a schematic cross-sectional view of an electronic device according to the tenth embodiment of the present invention.
- the first mounting substrate, the electronic element package, and the second mounting substrate are connected.
- the electronic device 81 includes the electronic element package 2, the first mounting substrate 4, and the second mounting substrate 82.
- Each form of the electronic element package 2 and the first mounting board 4 is the same as each form of the electronic element package 2 and the mounting board 4 in the first embodiment.
- the second mounting substrate 82 has a flat plate-like second substrate electrode 83 for electrical connection with the first substrate electrode 5 of the first mounting substrate 4.
- at least one electronic element 84 is mounted on the second mounting substrate 82. In the form shown in FIG. 11, the electronic element 84 is mounted on the surface opposite to the surface on which the first substrate electrode 83 is formed.
- One first mounting board 4 is electrically connected to both the electronic element package 2 and the second mounting board 82 so as to bridge. Accordingly, when the LGA electrode 3 of the electronic device package 2 and the first substrate electrode 5 of the first mounting substrate 4 electrically connected to the second substrate electrode 83 of the second mounting substrate 82 are on the same plane, the electronic device The electronic device package 2 and the second mounting substrate 82 are arranged so that the LGA electrode 3 of the package 2 and the second substrate electrode 83 of the second mounting substrate 82 exist on the same plane.
- the electronic element package 2 and the second mounting substrate 82 are preferably joined (fixed) with a resin 85.
- the resin 85 for example, an epoxy resin can be used.
- the form of electrical connection between the first mounting board 4 and the electronic device package 2 and the second mounting board 82 is the same as that of the first embodiment except that the first mounting board 4 is electrically connected to each other. It is.
- FIG. 12 is a schematic plan view of the electronic element package 2, the second mounting substrate 82, and the electronic element 84 shown in FIG. In FIG. 12, the mounting substrate 4, the resin 85, and the like are not shown.
- the second mounting substrate 82 is formed with a through hole 82a for inserting and arranging the electronic element package 2.
- the shape and size of the through hole 82 a can be a larger shape, for example, a rectangle of 14 mm ⁇ 14 mm.
- the electronic element package 2 is inserted into the through hole 82 a, and the resin 85 is disposed at least in the gap between the electronic element package 2 and the second mounting substrate 82.
- the resin 85 is preferably arranged so as to form the same plane as the electronic device package 2 and the second mounting substrate 82 with respect to the first mounting substrate 4.
- the electronic element package 2 is disposed in the through hole 82 a of the second mounting substrate 82, but the electronic element 84 may be disposed instead of the electronic element package 2.
- the thicker one of the electronic element package 2 and the electronic element 84 is disposed in the through hole 82a, which contributes to a reduction in thickness.
- the tenth embodiment has been described using the mounting substrate and the electronic device package in the first embodiment, the mounting substrate and the electronic device package in the second to eighth embodiments can also be applied to the tenth embodiment. Further, the embodiments may be combined and applied to the tenth embodiment.
- the second mounting board and the electronic element package are electrically connected via the first mounting board, so that a plurality of electronic elements are mounted on the second mounting board.
- the electronic device can be thinned because the wiring can be routed on the second mounting board without increasing the thickness of the first mounting board. Further, the electronic device can be further thinned by inserting the electronic device package or the electronic device into the through hole of the second mounting substrate.
- FIG. 13 is a schematic process diagram for explaining an electronic device manufacturing method according to the tenth embodiment of the present invention.
- the second mounting substrate 82 on which at least one electronic element 84 is mounted is bonded onto the adhesive plate 86 so that the second substrate electrode 83 faces the adhesive plate 86 (FIG. 13A; positioning step).
- the adhesive plate 86 for example, a structure in which a quartz sheet and an aluminum plate are laminated can be used. The second mounting substrate 82 and the electronic package 2 adhered to the adhesive plate 86 can be easily removed.
- the electronic element package 2 is bonded to the adhesive plate 86 so that the LGA electrode 3 faces the adhesive plate 86 (FIG. 13B; positioning step).
- a mark indicating an arrangement position of the electronic element package 2 or the like is formed on the second mounting substrate 82 or the adhesive plate 86. Note that the second mounting substrate 82 may be bonded after the electronic element package 2 is first bonded to the adhesive plate 86.
- the resin 85 is supplied between the electronic device package 2 bonded to the adhesive plate 86 and the second mounting substrate 82, and the resin 85 is cured by heating, so that the electronic device package 2 and the second mounting substrate 82 are integrated.
- the potting method can be used as a method for supplying the resin 85.
- the entire surface of the electronic element package and the second mounting substrate is resin-transferred by the transfer molding method. The method of sealing with can be used.
- the electronic element package 2 and the second mounting substrate 82 integrated with the resin 85 are removed from the adhesive plate 86 (FIG. 13 (d); removal step).
- the LGA electrode 3 of the electronic device package 2 and the second substrate electrode 83 of the second mounting substrate 82 are arranged on the same plane or substantially the same plane. And can be directed in the same direction.
- the mounting substrate 4 may be configured to cross the electronic element package 2 as shown in FIG.
- the adhesive plate by using the adhesive plate, it is possible to easily form a configuration in which the first mounting substrate can be simultaneously mounted on the electronic element package and the second mounting substrate.
- the electronic device package and the electrode of the second mounting substrate can be easily electrically connected by the first mounting substrate.
- FIG. 14 is a schematic cross-sectional view of an electronic device according to the eleventh embodiment of the present invention.
- the electronic element package and the second mounting substrate are mainly joined with resin.
- the electronic element 84 and the electronic element package 2 are sealed. Further, the entire surface of one side of the electronic element package 2 and the second mounting substrate 82 is covered with the resin 95.
- the step of connecting the mounting substrate 4 (for example, the conductive material supplying step) is performed. It can be easily implemented. Thereby, for example, the adhesive can be made to have a uniform thickness, and variations in the supply amount of the conductive material can be suppressed.
- the through hole 82a is formed in order to arrange the electronic device package 2 from the center of the second mounting substrate 82, but the shape of the second mounting substrate is the arrangement position of the electronic device package and the electronic device. Can be changed as appropriate.
- FIG. 15A when the electronic element package 2 is arranged from the end of the second mounting substrate 111, a notch 111 a is formed at the end of the second mounting substrate 111. it can.
- the second mounting substrate 112 is not provided with a through hole or a notch, and the electronic element The package 2 may be simply disposed beside the second mounting substrate 112.
- a plurality of electronic element packages 2 are arranged, a plurality of notches or through holes 113a and 113b can be formed in the second mounting substrate 113 as shown in FIG.
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Abstract
Description
本発明は、日本国特許出願:特願2008-036084号(2008年 2月18日出願)及び特願2008-170908号(2008年 6月30日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、電子素子パッケージを実装基板に実装した電子装置及びその製造方法に関し、特にLGA(Land Grid Array)型電極を有する電子素子パッケージを実装基板に実装した電子装置及びその製造方法に関する。また、本発明は、複数の実装基板を積層実装した実装基板積層体及びその製造方法に関する。
以下の分析は、本発明の観点から与えられる。
2,22 電子素子パッケージ
3,23 LGA電極
4,14,44,64,74 (第1)実装基板
5,15,45,65,75 (第1)基板電極
6,16,46,66,76 スルーホール
7,67,77 光非透過層
8 接着剤
9 導電材
82,102,111,112,113 第2実装基板
82a,113a,113b 貫通孔
111a 切り欠き
83,103 第2基板電極
84 電子素子
85,95 樹脂
86 粘着プレート
101 実装基板積層体
Claims (28)
- 電子素子パッケージを第1実装基板に実装した電子装置であって、
前記電子素子パッケージは、LGA(Land Grid Array)型のLGA電極を備え、
前記第1実装基板は、内壁を被覆する導電体を有するスルーホールを備え、
前記電子素子パッケージと前記第1実装基板とは前記スルーホールの開口の少なくとも一部が前記LGA電極と重なるように実装され、
前記LGA電極と前記スルーホールの前記導電体とは、前記スルーホール内に配された導電材によって電気的に接続され、
前記LGA電極のうち前記スルーホールの前記開口と重なっていない領域の少なくとも一部は、前記第1実装基板と接着剤を介して接合されていることを特徴とする電子装置。 - 前記スルーホールの前記導電体と電気的に接続される基板電極を有する第2実装基板をさらに備え、
前記第1実装基板と前記第2実装基板とは前記スルーホールの開口の少なくとも一部が前記基板電極と重なるように実装され、
前記基板電極と前記スルーホールの前記導電体とは、前記スルーホール内に配された導電材によって電気的に接続され、
前記基板電極のうち前記スルーホールの前記開口と重なっていない領域の少なくとも一部は、前記第1実装基板と接着剤を介して接合されていることを特徴とする請求項1に記載の電子装置。 - 前記LGA電極又は前記LGA電極及び前記基板電極の面積は、前記LGA電極又は前記LGA電極及び前記基板電極と対向する側の前記スルーホールの開口面積より大きいことを特徴とする請求項1又は2に記載の電子装置。
- 電子素子パッケージを第1実装基板に実装した電子装置であって、
前記電子素子パッケージは、LGA(Land Grid Array)型のLGA電極を備え、
前記第1実装基板は、内壁を被覆する導電体を有するスルーホールを備え、
前記LGA電極の面積は、前記LGA電極と対向する側の前記スルーホールの開口面積より小さく、
前記電子素子パッケージと前記第1実装基板とは前記LGA電極が前記スルーホールの開口に包含されるように実装され、
前記LGA電極と前記スルーホールの前記導電体とは、前記スルーホール内に配された導電材によって電気的に接続され、
前記第1実装基板に対向する前記LGA電極の上面は、前記スルーホール内に存在し、
前記電子素子パッケージと前記第1実装基板とが対向する領域のうち、前記スルーホールの前記開口以外の領域には接着剤が介在していることを特徴とする電子装置。 - 前記スルーホールの前記導電体と電気的に接続される基板電極を有する第2実装基板をさらに備え、
前記基板電極の面積は、前記基板電極と対向する側の前記スルーホールの開口面積より小さく、
前記第1実装基板と前記第2実装基板とは前記基板電極が前記スルーホールの開口に包含されるように実装され、
前記基板電極と前記スルーホールの前記導電体とは、前記スルーホール内に配された導電材によって電気的に接続され、
前記第1実装基板に対向する前記基板電極の上面は、前記スルーホール内に存在し、
前記第1実装基板と前記第2実装基板とが対向する領域のうち、前記スルーホールの前記開口以外の領域には接着剤が介在していることを特徴とする請求項4に記載の電子装置。 - 前記電子素子パッケージの前記LGA電極と前記第2実装基板の前記基板電極とは同一平面上に配列されていることを特徴とする請求項2又は5に記載の電子装置。
- 前記第2実装基板は、貫通孔又は切り欠きを有し、
前記電子素子パッケージは、前記貫通孔又は切り欠き内に配置されていることを特徴とする請求項2,5又は6に記載の電子装置。 - 前記電子素子パッケージと前記第2実装基板とは樹脂で接合されていることを特徴とする請求項2,5~7のいずれか一項に記載の電子装置。
- 前記第2実装基板には少なくとも1つの電子素子が実装されていることを特徴とする2,5~8のいずれか一項に記載の電子装置。
- 前記LGA電極又は前記LGA電極及び前記基板電極は前記導電材によって覆われていることを特徴とする請求項4又は5に記載の電子装置。
- 前記第1実装基板は、前記電子素子パッケージ又は前記電子素子パッケージ及び前記第2実装基板と対向する前記第1実装基板面上に、前記LGA電極又は前記LGA電極及び前記基板電極と対向する前記スルーホールの導電体と連設された導電体を有し、
前記LGA電極又は前記LGA電極及び前記基板電極のうち前記スルーホールの前記開口と重なっていない領域の少なくとも一部は、前記第1実装基板面上の前記導電体と接着剤を介して接合されていることを特徴とする請求項1~10のいずれか一項に記載の電子装置。 - 前記第1実装基板は、前記電子素子パッケージ又は前記電子素子パッケージ及び前記第2実装基板と対向する前記第1実装基板面上に、前記LGA電極又は前記LGA電極及び前記基板電極と対向する前記スルーホールの導電体と連設された導電体を有しないことを特徴とする請求項1~10のいずれか一項に記載の電子装置。
- 前記電子素子パッケージ又は前記電子素子パッケージ及び前記第2実装基板と前記第1実装基板とが対向する領域のうち、前記スルーホールの前記開口以外の領域には接着剤が介在していることを特徴とする請求項1~12のいずれか一項に記載の電子装置。
- 前記接着剤は感光性樹脂であることを特徴とする請求項1~13のいずれか一項に記載の電子装置。
- 前記第1実装基板は、前記スルーホール以外は前記電子素子パッケージ又は前記電子素子パッケージ及び前記第2実装基板に対して光透過性を有しないことを特徴とする請求項1~14のいずれか一項に記載の電子装置。
- 前記第1実装基板は、前記電子素子パッケージ又は前記電子素子パッケージ及び前記第2実装基板に対する光を遮光する光非透過層を少なくとも一部に有することを特徴とする請求項15に記載の電子装置。
- 前記導電材は、前記スルーホールから、前記電子素子パッケージ又は前記電子素子パッケージ及び前記第2実装基板と対向する前記第1実装基板面とは反対側の第1実装基板面上へ連続して形成されていることを特徴とする請求項1~16のいずれか一項に記載の電子装置。
- 第1実装基板と、
前記第1実装基板に積層実装される第2実装基板と、を備え、
前記第2実装基板は、平面電極を有し、
前記第1実装基板は、内壁を被覆する導電体を有するスルーホールを有し、
前記第1実装基板と前記第2実装基板とは前記スルーホールの開口の少なくとも一部が前記平面電極と重なるように実装され、
前記平面電極と前記スルーホールの前記導電体とは、前記スルーホール内に配された導電材によって電気的に接続され、
前記平面電極のうち前記スルーホールの前記開口と重なっていない領域の少なくとも一部は、前記第1実装基板と接着剤を介して接合されていることを特徴とする実装基板積層体。 - 第1実装基板と、
前記第1実装基板に積層実装される第2実装基板と、を備え、
前記第2実装基板は、平面電極を有し、
前記第1実装基板は、内壁を被覆する導電体を有するスルーホールを有し、
前記平面電極の面積は、前記平面電極と対向する側の前記スルーホールの開口面積より小さく、
前記第1実装基板と前記第2実装基板とは前記平面電極が前記スルーホールの開口に包含されるように実装され、
前記平面電極と前記スルーホールの前記導電体とは、前記スルーホール内に配された導電材によって電気的に接続され、
前記第1実装基板に対向する前記平面電極の上面は、前記スルーホール内に存在し、
前記第1実装基板と前記第2実装基板とが対向する領域のうち、前記スルーホールの前記開口以外の領域には接着剤が介在していることを特徴とする実装基板積層体。 - 前記接着剤は感光性樹脂であり、
前記第1実装基板は、前記スルーホール以外は前記第2実装基板に対して光透過性を有しないことを特徴とする請求項18又は19に記載の実装基板積層体。 - 電子素子パッケージを第1実装基板に実装した電子装置を製造する方法であって、
LGA(Land Grid Array)型のLGA電極が形成された前記電子素子パッケージ面上の少なくとも一部に接着剤を配置する接着剤配置工程と、
内壁に導電体を有するスルーホールを備える第1実装基板と前記電子素子パッケージとを、前記スルーホールの開口の少なくとも一部が前記LGA電極と重なるように積層する接合工程と、
前記スルーホールの前記開口において前記LGA電極の少なくとも一部が露出するように前記スルーホール内に存在する接着剤を除去する接着剤除去工程と、
前記LGA電極と対向している前記スルーホールの開口とは反対側の開口から前記スルーホールに導電材を供給する導電材供給工程と、
前記導電材を前記LGA電極の露出面へ移動させ、前記LGA電極と前記スルーホールの導電体とを前記導電材によって電気的に接続する電気的接続工程と、を含むことを特徴とする電子装置の製造方法。 - LGA(Land Grid Array)型のLGA電極を有する電子素子パッケージと、少なくとも1つの電子素子が実装されていると共に平面電極を有する第2実装基板とを、前記LGA電極及び前記平面電極が粘着プレートと対向するように、前記粘着プレートに接着して位置決めする位置決め工程と、
前記電子素子パッケージと前記第2実装基板とを樹脂で接合する接合工程と、
前記電子素子パッケージ及び前記第2実装基板を粘着プレートから取り外す取外し工程と、
前記LGA電極が形成された前記電子素子パッケージ面上及び前記平面電極が形成された第2実装基板上の少なくとも一部に接着剤を配置する接着剤配置工程と、
内壁に導電体を有する少なくとも1つのスルーホールを備える第1実装基板と、前記電子素子パッケージ及び第2実装基板とを、前記スルーホールの開口の少なくとも一部が前記LGA電極及び前記平面電極と重なるように積層する接合工程と、
前記スルーホールの前記開口において前記LGA電極及び前記平面電極の少なくとも一部が露出するように前記スルーホール内に存在する接着剤を除去する接着剤除去工程と、
前記LGA電極及び前記平面電極と対向している前記スルーホールの開口とは反対側の開口から前記スルーホールに導電材を供給する導電材供給工程と、
前記導電材を前記LGA電極及び前記平面電極の露出面へ移動させ、前記LGA電極及び前記平面電極と前記スルーホールの導電体とを前記導電材によって電気的に接続する電気的接続工程と、を含むことを特徴とする電子装置の製造方法。 - 前記LGA電極又は前記LGA電極及び前記平面電極の面積は、前記LGA電極又は前記LGA電極及び前記平面電極と対向する側の前記スルーホールの開口面積より大きく、
前記接合工程において、少なくとも、前記LGA電極又は前記LGA電極及び前記平面電極のうち前記スルーホールの前記開口と重なっていない領域の少なくとも一部と前記第1実装基板とを接着剤を介して接合することを特徴とする請求項21又は22に記載の電子装置の製造方法。 - 前記LGA電極又は前記LGA電極及び前記平面電極の面積は、前記LGA電極又は前記LGA電極及び前記平面電極と対向する側の前記スルーホールの開口面積より小さく、
前記接合工程において、前記第1実装基板に対向する前記LGA電極又は前記LGA電極及び前記平面電極の少なくとも一部を前記スルーホールに挿入することを特徴とする請求項21又は22に記載の電子装置の製造方法。 - 前記接着剤は感光性樹脂であり、
前記接着剤除去工程は、前記スルーホール内の前記接着剤を露光する露光工程と、
前記露光工程後、現像剤によって前記スルーホール内の前記接着剤を除去する現像工程と、を含むことを特徴とする請求項21~24のいずれか一項に記載の電子装置の製造方法。 - 前記第1実装基板は、前記スルーホール以外は前記電子素子パッケージ又は前記電子素子パッケージ及び前記第2実装基板に対して光透過性を有さず、
前記露光工程において、前記第1実装基板をマスクとして、前記スルーホールの開口から前記スルーホール内の前記接着剤のみを露光することを特徴とする請求項25に記載の電子装置の製造方法。 - 前記導電材はクリームはんだであり、
前記電気的接続工程において、前記導電材を加熱溶融することにより前記LGA電極又は前記LGA電極及び前記平面電極と前記スルーホールの導電体とを電気的に接続することを特徴とする請求項21~26のいずれか一項に記載の電子装置の製造方法。 - 平面電極が形成された前記第2実装基板面上の少なくとも一部に接着剤を配置する接着剤配置工程と、
内壁に導電体を有するスルーホールを備える第1実装基板と前記第2実装基板とを、前記スルーホールの開口の少なくとも一部が前記平面電極と重なるように積層する接合工程と、
前記スルーホールの前記開口において前記平面電極の少なくとも一部が露出するように前記スルーホール内に存在する接着剤を除去する接着剤除去工程と、
前記平面電極と対向している前記スルーホールの開口とは反対側の開口から前記スルーホールに導電材を供給する導電材供給工程と、
前記導電材を前記平面電極の露出面へ移動させ、前記平面電極と前記スルーホールの導電体とを前記導電材によって電気的に接続する電気的接続工程と、を含むことを特徴とする実装基板積層体の製造方法。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS631094A (ja) * | 1986-06-20 | 1988-01-06 | 富士通株式会社 | フレキシブル及びリジツド印刷配線複合基板 |
JPH04269894A (ja) * | 1991-02-26 | 1992-09-25 | Tokyo Electric Co Ltd | プリント回路基板への面実装部品の半田付け方法 |
JPH05267360A (ja) * | 1992-03-18 | 1993-10-15 | Oki Electric Ind Co Ltd | 半導体装置 |
JPH06216492A (ja) * | 1993-01-21 | 1994-08-05 | Hitachi Ltd | 電子装置 |
JP2002237673A (ja) * | 2001-02-08 | 2002-08-23 | Murata Mfg Co Ltd | 回路基板装置 |
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US20070045812A1 (en) * | 2005-08-31 | 2007-03-01 | Micron Technology, Inc. | Microfeature assemblies including interconnect structures and methods for forming such interconnect structures |
US7629541B2 (en) * | 2006-06-19 | 2009-12-08 | Endicott Interconnect Technologies, Inc. | High speed interposer |
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---|---|---|---|---|
JPS631094A (ja) * | 1986-06-20 | 1988-01-06 | 富士通株式会社 | フレキシブル及びリジツド印刷配線複合基板 |
JPH04269894A (ja) * | 1991-02-26 | 1992-09-25 | Tokyo Electric Co Ltd | プリント回路基板への面実装部品の半田付け方法 |
JPH05267360A (ja) * | 1992-03-18 | 1993-10-15 | Oki Electric Ind Co Ltd | 半導体装置 |
JPH06216492A (ja) * | 1993-01-21 | 1994-08-05 | Hitachi Ltd | 電子装置 |
JP2002237673A (ja) * | 2001-02-08 | 2002-08-23 | Murata Mfg Co Ltd | 回路基板装置 |
Cited By (1)
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