WO2009025338A1 - Igbt用のシリコン単結晶ウェーハ及びigbt用のシリコン単結晶ウェーハの製造方法 - Google Patents

Igbt用のシリコン単結晶ウェーハ及びigbt用のシリコン単結晶ウェーハの製造方法 Download PDF

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Publication number
WO2009025338A1
WO2009025338A1 PCT/JP2008/064951 JP2008064951W WO2009025338A1 WO 2009025338 A1 WO2009025338 A1 WO 2009025338A1 JP 2008064951 W JP2008064951 W JP 2008064951W WO 2009025338 A1 WO2009025338 A1 WO 2009025338A1
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WO
WIPO (PCT)
Prior art keywords
igbt
single crystal
silicon single
crystal wafer
wafer
Prior art date
Application number
PCT/JP2008/064951
Other languages
English (en)
French (fr)
Inventor
Shigeru Umeno
Toshiaki Ono
Koji Kato
Manabu Nishimoto
Masataka Hourai
Original Assignee
Sumco Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corporation filed Critical Sumco Corporation
Priority to JP2009529064A priority Critical patent/JP5304649B2/ja
Publication of WO2009025338A1 publication Critical patent/WO2009025338A1/ja

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    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/20Controlling or regulating
    • C30B15/203Controlling or regulating the relationship of pull rate (v) to axial thermal gradient (G)
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02Heat treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333Vertical insulated gate bipolar transistors
    • H01L29/66348Vertical insulated gate bipolar transistors with a recessed gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thermal Sciences (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

チョクラルスキー法によって育成されたシリコン単結晶からなるIGBT用のシリコン単結晶ウェーハであって、引き上げ速度マージンを拡大することが可能であるとともに、抵抗率のバラツキが小さなウェーハの製造が可能なように、結晶径方向全域においてCOP欠陥および転位クラスタが排除されており、IGBT用デバイスプロセス熱処理後に20nm以上の酸素析出物密度が1×105個/cm3以下である。
PCT/JP2008/064951 2007-08-21 2008-08-21 Igbt用のシリコン単結晶ウェーハ及びigbt用のシリコン単結晶ウェーハの製造方法 WO2009025338A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009529064A JP5304649B2 (ja) 2007-08-21 2008-08-21 Igbt用のシリコン単結晶ウェーハの製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-215332 2007-08-21
JP2007215332 2007-08-21

Publications (1)

Publication Number Publication Date
WO2009025338A1 true WO2009025338A1 (ja) 2009-02-26

Family

ID=40378238

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/064951 WO2009025338A1 (ja) 2007-08-21 2008-08-21 Igbt用のシリコン単結晶ウェーハ及びigbt用のシリコン単結晶ウェーハの製造方法

Country Status (2)

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JP (1) JP5304649B2 (ja)
WO (1) WO2009025338A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012101957A1 (ja) * 2011-01-24 2012-08-02 信越半導体株式会社 シリコン単結晶ウェーハの製造方法及びアニールウェーハ
JP2013142054A (ja) * 2012-01-12 2013-07-22 Shin Etsu Handotai Co Ltd シリコン基板の製造方法
JP7466790B1 (ja) 2023-02-27 2024-04-12 三菱電機株式会社 半導体装置の製造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240071775A1 (en) * 2022-08-24 2024-02-29 Semiconductor Components Industries, Llc Methods of manufacturing semiconductor devices semiconductor devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005154172A (ja) * 2003-11-21 2005-06-16 Shin Etsu Handotai Co Ltd シリコン単結晶の製造方法及びシリコン単結晶製造装置の設計方法並びにシリコン単結晶製造装置
JP2006312575A (ja) * 2005-04-08 2006-11-16 Sumco Corp シリコンウェーハおよびその製造方法
JP2006344823A (ja) * 2005-06-09 2006-12-21 Sumco Corp Igbt用のシリコンウェーハ及びその製造方法
JP2007191350A (ja) * 2006-01-19 2007-08-02 Sumco Corp Igbt用シリコン単結晶ウェーハ及びigbt用シリコン単結晶ウェーハの製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060147565A1 (en) * 2002-06-28 2006-07-06 Pharmachem Laboratories, Inc. Purified amylase inhibitor and novel process for obtaining the same
KR100743821B1 (ko) * 2003-02-25 2007-07-30 가부시키가이샤 섬코 실리콘 단결정 육성 방법, 실리콘 웨이퍼 제조 방법 및 soi 기판 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005154172A (ja) * 2003-11-21 2005-06-16 Shin Etsu Handotai Co Ltd シリコン単結晶の製造方法及びシリコン単結晶製造装置の設計方法並びにシリコン単結晶製造装置
JP2006312575A (ja) * 2005-04-08 2006-11-16 Sumco Corp シリコンウェーハおよびその製造方法
JP2006344823A (ja) * 2005-06-09 2006-12-21 Sumco Corp Igbt用のシリコンウェーハ及びその製造方法
JP2007191350A (ja) * 2006-01-19 2007-08-02 Sumco Corp Igbt用シリコン単結晶ウェーハ及びigbt用シリコン単結晶ウェーハの製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012101957A1 (ja) * 2011-01-24 2012-08-02 信越半導体株式会社 シリコン単結晶ウェーハの製造方法及びアニールウェーハ
CN103328696A (zh) * 2011-01-24 2013-09-25 信越半导体股份有限公司 单晶硅晶片的制造方法及退火晶片
US8916953B2 (en) 2011-01-24 2014-12-23 Shin-Etsu Handotai Co., Ltd. Method for manufacturing silicon single crystal wafer and annealed wafer
CN103328696B (zh) * 2011-01-24 2016-05-11 信越半导体股份有限公司 单晶硅晶片的制造方法及退火晶片
JP2013142054A (ja) * 2012-01-12 2013-07-22 Shin Etsu Handotai Co Ltd シリコン基板の製造方法
JP7466790B1 (ja) 2023-02-27 2024-04-12 三菱電機株式会社 半導体装置の製造方法

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JPWO2009025338A1 (ja) 2010-11-25

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