WO2008111396A1 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
WO2008111396A1
WO2008111396A1 PCT/JP2008/053373 JP2008053373W WO2008111396A1 WO 2008111396 A1 WO2008111396 A1 WO 2008111396A1 JP 2008053373 W JP2008053373 W JP 2008053373W WO 2008111396 A1 WO2008111396 A1 WO 2008111396A1
Authority
WO
WIPO (PCT)
Prior art keywords
display data
memory
display
integrated circuit
semiconductor integrated
Prior art date
Application number
PCT/JP2008/053373
Other languages
English (en)
French (fr)
Inventor
Shoji Kawahara
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009503959A priority Critical patent/JP5115548B2/ja
Priority to CN200880008413.7A priority patent/CN101636778B/zh
Priority to US12/526,333 priority patent/US9019285B2/en
Publication of WO2008111396A1 publication Critical patent/WO2008111396A1/ja

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Image Processing (AREA)

Abstract

　小面積化を図りつつ低消費電力で表示装置の表示データを効率良くメモリから読み出し、表示装置コントローラへ表示データを送ることができる半導体集積回路装置を提供することにある。 　表示装置の表示用データが格納されているメモリに接続され、前記表示用データを前記メモリより読み出して前記表示装置へ転送する半導体集積回路装置であって、前記表示用データを保持する表示データバッファと、前記表示用データを、前記メモリのページサイズ単位でプリフェッチして前記表示データバッファに保持させるとともに、１つのページのプリフェッチが終了した時点で該ページをクローズし、前記メモリを省電力モードに移行させるメモリコントローラと、前記表示データバッファに保持されている表示用データを前記表示装置に転送する表示装置コントローラと、を含む。
PCT/JP2008/053373 2007-03-15 2008-02-27 半導体集積回路装置 WO2008111396A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009503959A JP5115548B2 (ja) 2007-03-15 2008-02-27 半導体集積回路装置
CN200880008413.7A CN101636778B (zh) 2007-03-15 2008-02-27 半导体集成电路装置
US12/526,333 US9019285B2 (en) 2007-03-15 2008-02-27 Semiconductor integrated circuit device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007066590 2007-03-15
JP2007-066590 2007-03-15

Publications (1)

Publication Number Publication Date
WO2008111396A1 true WO2008111396A1 (ja) 2008-09-18

Family

ID=39759338

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/053373 WO2008111396A1 (ja) 2007-03-15 2008-02-27 半導体集積回路装置

Country Status (4)

Country Link
US (1) US9019285B2 (ja)
JP (1) JP5115548B2 (ja)
CN (1) CN101636778B (ja)
WO (1) WO2008111396A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011122088A1 (ja) * 2010-03-29 2011-10-06 ブラザー工業株式会社 表示装置及び表示装置のプログラム
WO2012014802A1 (ja) * 2010-07-30 2012-02-02 ブラザー工業株式会社 表示装置及び当該表示装置のｃｐｕが実行するコンピュータプログラム
JP2017516123A (ja) * 2014-03-02 2017-06-15 クアルコム，インコーポレイテッド Ｄｒａｍメモリシステムにおいて省電力静止画像表示リフレッシュを提供するためのシステムおよび方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8810589B1 (en) * 2009-11-12 2014-08-19 Marvell Israel (M.I.S.L) Ltd. Method and apparatus for refreshing display
WO2012174681A1 (en) * 2011-06-24 2012-12-27 Intel Corporation Techniques for controlling power consumption of a system
WO2018223100A1 (en) * 2017-06-01 2018-12-06 University Of Virginia Patent Foundation System on a chip with customized data flow architecture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06274410A (ja) * 1993-03-23 1994-09-30 Toshiba Corp 表示制御システム
JPH09297562A (ja) * 1996-05-09 1997-11-18 Tamura Electric Works Ltd Ｌｃｄ表示装置
JPH10105367A (ja) * 1996-09-30 1998-04-24 Toshiba Corp 画像処理装置

Family Cites Families (16)

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JPH0512387A (ja) 1991-07-04 1993-01-22 Sankyo Seiki Mfg Co Ltd 画像処理装置
JPH08123953A (ja) 1994-10-21 1996-05-17 Mitsubishi Electric Corp 画像処理装置
JP3519199B2 (ja) * 1996-02-06 2004-04-12 株式会社ソニー・コンピュータエンタテインメント 画像生成装置
US7127573B1 (en) * 2000-05-04 2006-10-24 Advanced Micro Devices, Inc. Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions
JP2003242027A (ja) 2002-02-13 2003-08-29 Sony Corp インタフェース装置、データ処理システム、及びデータ処理方法
JP2004258212A (ja) * 2003-02-25 2004-09-16 Renesas Technology Corp 画面表示装置
JP4749793B2 (ja) 2004-08-05 2011-08-17 パナソニック株式会社 省電力処理装置、省電力処理方法、及び省電力処理プログラム
US8028143B2 (en) * 2004-08-27 2011-09-27 Qualcomm Incorporated Method and apparatus for transmitting memory pre-fetch commands on a bus
US20070188506A1 (en) * 2005-02-14 2007-08-16 Lieven Hollevoet Methods and systems for power optimized display
US20070191007A1 (en) * 2006-02-14 2007-08-16 Claude Hayek Method and system for a processor that handles a plurality of wireless access communication protocols
US20080022050A1 (en) * 2006-07-18 2008-01-24 Via Technologies, Inc. Pre-Fetching Data for a Predictably Requesting Device
US20080028181A1 (en) * 2006-07-31 2008-01-31 Nvidia Corporation Dedicated mechanism for page mapping in a gpu
US8035647B1 (en) * 2006-08-24 2011-10-11 Nvidia Corporation Raster operations unit with interleaving of read and write requests using PCI express
US8155316B1 (en) * 2006-10-19 2012-04-10 NVIDIA Corporaton Contract based memory management for isochronous streams
US7805587B1 (en) * 2006-11-01 2010-09-28 Nvidia Corporation Memory addressing controlled by PTE fields
GB2445373B (en) * 2007-01-03 2010-12-29 Advanced Risc Mach Ltd A data processing apparatus and method for managing access to a display buffer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06274410A (ja) * 1993-03-23 1994-09-30 Toshiba Corp 表示制御システム
JPH09297562A (ja) * 1996-05-09 1997-11-18 Tamura Electric Works Ltd Ｌｃｄ表示装置
JPH10105367A (ja) * 1996-09-30 1998-04-24 Toshiba Corp 画像処理装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011122088A1 (ja) * 2010-03-29 2011-10-06 ブラザー工業株式会社 表示装置及び表示装置のプログラム
WO2012014802A1 (ja) * 2010-07-30 2012-02-02 ブラザー工業株式会社 表示装置及び当該表示装置のｃｐｕが実行するコンピュータプログラム
JP2017516123A (ja) * 2014-03-02 2017-06-15 クアルコム，インコーポレイテッド Ｄｒａｍメモリシステムにおいて省電力静止画像表示リフレッシュを提供するためのシステムおよび方法

Also Published As

Publication number Publication date
JP5115548B2 (ja) 2013-01-09
US20100321398A1 (en) 2010-12-23
JPWO2008111396A1 (ja) 2010-06-24
CN101636778B (zh) 2011-12-28
CN101636778A (zh) 2010-01-27
US9019285B2 (en) 2015-04-28

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