CN101636778A - 半导体集成电路装置 - Google Patents
半导体集成电路装置 Download PDFInfo
- Publication number
- CN101636778A CN101636778A CN200880008413.7A CN200880008413A CN101636778A CN 101636778 A CN101636778 A CN 101636778A CN 200880008413 A CN200880008413 A CN 200880008413A CN 101636778 A CN101636778 A CN 101636778A
- Authority
- CN
- China
- Prior art keywords
- video data
- controller
- impact damper
- lcd
- dram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
- G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/12—Frame memory handling
- G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Image Processing (AREA)
Abstract
Description
Claims (4)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP066590/2007 | 2007-03-15 | ||
JP2007066590 | 2007-03-15 | ||
PCT/JP2008/053373 WO2008111396A1 (ja) | 2007-03-15 | 2008-02-27 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101636778A true CN101636778A (zh) | 2010-01-27 |
CN101636778B CN101636778B (zh) | 2011-12-28 |
Family
ID=39759338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200880008413.7A Active CN101636778B (zh) | 2007-03-15 | 2008-02-27 | 半导体集成电路装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9019285B2 (zh) |
JP (1) | JP5115548B2 (zh) |
CN (1) | CN101636778B (zh) |
WO (1) | WO2008111396A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8810589B1 (en) * | 2009-11-12 | 2014-08-19 | Marvell Israel (M.I.S.L) Ltd. | Method and apparatus for refreshing display |
JP2011209363A (ja) * | 2010-03-29 | 2011-10-20 | Brother Industries Ltd | 表示装置及び表示装置のプログラム |
JP2012032637A (ja) * | 2010-07-30 | 2012-02-16 | Brother Ind Ltd | 表示装置及び当該表示装置のcpuが実行するコンピュータプログラム |
EP2724207A4 (en) * | 2011-06-24 | 2015-01-21 | Intel Corp | METHOD FOR CONTROLLING THE POWER CONSUMPTION OF A SYSTEM |
US20150248741A1 (en) * | 2014-03-02 | 2015-09-03 | Qualcomm Incorporated | System and method for providing power-saving static image display refresh in a dram memory system |
US10963408B2 (en) | 2017-06-01 | 2021-03-30 | University Of Virginia Patent Foundation | System on a chip with customized data flow architecture |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0512387A (ja) | 1991-07-04 | 1993-01-22 | Sankyo Seiki Mfg Co Ltd | 画像処理装置 |
JPH06274410A (ja) * | 1993-03-23 | 1994-09-30 | Toshiba Corp | 表示制御システム |
JPH08123953A (ja) | 1994-10-21 | 1996-05-17 | Mitsubishi Electric Corp | 画像処理装置 |
JP3519199B2 (ja) * | 1996-02-06 | 2004-04-12 | 株式会社ソニー・コンピュータエンタテインメント | 画像生成装置 |
JPH09297562A (ja) * | 1996-05-09 | 1997-11-18 | Tamura Electric Works Ltd | Lcd表示装置 |
JP3732593B2 (ja) * | 1996-09-30 | 2006-01-05 | 株式会社東芝 | 画像処理装置 |
US7127573B1 (en) * | 2000-05-04 | 2006-10-24 | Advanced Micro Devices, Inc. | Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions |
JP2003242027A (ja) | 2002-02-13 | 2003-08-29 | Sony Corp | インタフェース装置、データ処理システム、及びデータ処理方法 |
JP2004258212A (ja) * | 2003-02-25 | 2004-09-16 | Renesas Technology Corp | 画面表示装置 |
JP4749793B2 (ja) | 2004-08-05 | 2011-08-17 | パナソニック株式会社 | 省電力処理装置、省電力処理方法、及び省電力処理プログラム |
US8028143B2 (en) * | 2004-08-27 | 2011-09-27 | Qualcomm Incorporated | Method and apparatus for transmitting memory pre-fetch commands on a bus |
US20070188506A1 (en) * | 2005-02-14 | 2007-08-16 | Lieven Hollevoet | Methods and systems for power optimized display |
US20070191007A1 (en) * | 2006-02-14 | 2007-08-16 | Claude Hayek | Method and system for a processor that handles a plurality of wireless access communication protocols |
US20080022050A1 (en) * | 2006-07-18 | 2008-01-24 | Via Technologies, Inc. | Pre-Fetching Data for a Predictably Requesting Device |
US20080028181A1 (en) * | 2006-07-31 | 2008-01-31 | Nvidia Corporation | Dedicated mechanism for page mapping in a gpu |
US8035647B1 (en) * | 2006-08-24 | 2011-10-11 | Nvidia Corporation | Raster operations unit with interleaving of read and write requests using PCI express |
US8155316B1 (en) * | 2006-10-19 | 2012-04-10 | NVIDIA Corporaton | Contract based memory management for isochronous streams |
US7805587B1 (en) * | 2006-11-01 | 2010-09-28 | Nvidia Corporation | Memory addressing controlled by PTE fields |
GB2445373B (en) * | 2007-01-03 | 2010-12-29 | Advanced Risc Mach Ltd | A data processing apparatus and method for managing access to a display buffer |
-
2008
- 2008-02-27 CN CN200880008413.7A patent/CN101636778B/zh active Active
- 2008-02-27 JP JP2009503959A patent/JP5115548B2/ja active Active
- 2008-02-27 US US12/526,333 patent/US9019285B2/en active Active
- 2008-02-27 WO PCT/JP2008/053373 patent/WO2008111396A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
US9019285B2 (en) | 2015-04-28 |
JP5115548B2 (ja) | 2013-01-09 |
WO2008111396A1 (ja) | 2008-09-18 |
JPWO2008111396A1 (ja) | 2010-06-24 |
CN101636778B (zh) | 2011-12-28 |
US20100321398A1 (en) | 2010-12-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: RENESAS ELECTRONICS CORPORATION Free format text: FORMER OWNER: NEC CORP. Effective date: 20130712 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20130712 Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corporation Address before: Tokyo, Japan Patentee before: NEC Corp. |
|
CP02 | Change in the address of a patent holder |
Address after: Tokyo, Japan Patentee after: Renesas Electronics Corporation Address before: Kanagawa, Japan Patentee before: Renesas Electronics Corporation |