WO2008104324A1 - Procédé d'intégration de puces dans des cavités de cartes à circuit imprimé - Google Patents

Procédé d'intégration de puces dans des cavités de cartes à circuit imprimé Download PDF

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Publication number
WO2008104324A1
WO2008104324A1 PCT/EP2008/001399 EP2008001399W WO2008104324A1 WO 2008104324 A1 WO2008104324 A1 WO 2008104324A1 EP 2008001399 W EP2008001399 W EP 2008001399W WO 2008104324 A1 WO2008104324 A1 WO 2008104324A1
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WO
WIPO (PCT)
Prior art keywords
cavity
chip
circuit board
printed circuit
adhesive
Prior art date
Application number
PCT/EP2008/001399
Other languages
German (de)
English (en)
Inventor
Roland SCHÖNHOLZ
Original Assignee
Würth Elektronik GmbH & Co. KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Würth Elektronik GmbH & Co. KG filed Critical Würth Elektronik GmbH & Co. KG
Publication of WO2008104324A1 publication Critical patent/WO2008104324A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/0556—Disposition
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/05573—Single external layer
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    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0125—Shrinkable, e.g. heat-shrinkable polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a method for producing a printed circuit board, which has an active electronic chip in a cavity, and a printed circuit board having an electronic chip in a cavity.
  • the electrical connection between the terminals of the chip and the circuit board is done in such a way that mounted on the outside of the chip connection pads are connected via wires with also mounted on the outside of the circuit board connection pads.
  • the whole can then be potted and laminated with another outer layer.
  • the invention is based on the object to provide a method for embedding electronic chips in printed circuit boards, which can be easily performed and provides good results.
  • the invention proposes a method with the features mentioned in claim 1. Further developments of the invention are the subject of dependent claims.
  • the invention also proposes a printed circuit board with the features of claim 13.
  • the chip is accommodated in the cavity, with its mechanical and electrical connection with the printed circuit board on the bottom of the cavity and the underside of the chip facing this bottom.
  • a customary in electronics adhesive is used, which is introduced untargeted in the cavity.
  • This adhesive cures, it develops a tensile force that causes the chip to more firmly retract into the cavity and connect its leads to conductive areas on the bottom of the cavity. This happens to the extent that not only an electrical connection is done by touching surfaces, but even a mechanical connection in the manner of cold welding.
  • the adhesive is temperature resistant up to a temperature which is higher than the temperatures generated during processing of the printed circuit board. The provided with the chip circuit board can therefore be further treated.
  • the electrical connection between the terminal pads is disposed on the backside of the chip between it and the bottom of the cavity at a protected location.
  • the cavity is covered by means of a further layer which is laminated onto the printed circuit board, in which case the electronic chip is completely embedded in the printed circuit board.
  • the structuring of the bottom of the cavity that is to say the arrangement of the connection pads, can take place prior to the production of the printed circuit board from individual layers, ie before the production of the cavity.
  • connection points of the electronic component and a metallic conductive layer of the printed circuit board and after the curing of the adhesive, the structuring of the metallic conductive layer of the printed circuit board is performed.
  • any suitable means may be used to make the cavity, the invention preferably proposing to make it by means of a laser which opens the top layer to the metallic bottom forming cavity.
  • connection pads on the bottom of the cavity autocatalytically with gold.
  • connection pads on the bottom of the cavity autocatalytically with gold.
  • other metallic surfaces which allow a contacting of the chip.
  • conductive adhesives can additionally support the electrical connection.
  • circuit board assembly is described in claim 13.
  • Figure 1 shows schematically the section through a portion of a printed circuit board at the beginning of the method according to the invention
  • FIG. 2 shows the section of FIG. 1 after opening the upper copper layer
  • FIG. 3 shows the section of FIGS. 1 and 2 after the cavity has been produced
  • Figure 4 shows the same section after the introduction of the adhesive
  • FIG. 5 shows the arrangement of the electronic chip above the cavity
  • FIG. 6 shows the section with the chip inserted and bonded in the cavity
  • FIG. 7 shows the same section after lamination of an outer cover layer
  • Figure 8 shows the section through a printed circuit board beginning of the method according to a second embodiment
  • FIG. 9 shows the same section after a first method step
  • FIG. 10 shows the same section after a second method step
  • FIG. 11 shows a detail of the printed circuit board after a third method step
  • Figure 12 shows the same section of the circuit board with inserted component
  • FIG. 13 shows the section after filling the cavity
  • FIG. 14 shows the printed circuit board structured on both sides
  • FIG. 15 shows the further lamination of the printed circuit board of FIG. 14 on both sides;
  • FIG. 16 shows a schematic section through a multilayer printed circuit board
  • Figure 17 is a simplified section through a further embodiment.
  • the illustrated in Figure 1 in a section the starting point for the inventive method performing circuit board includes a central core layer 1, which in turn can be constructed in multiple layers.
  • the core layer 1 has on its one side, in Figure 1 above, an etched structure with connection pads 2. These are connected via interconnects within the core layer 1 with other connection pads in combination.
  • the upper copper layer 5 is now opened in the area where a cavity is to be attached. This is done by free etching of the copper layer 5 or another suitable method, so that there creates a window 7, where the prepreg 3 forms the top or outside of the circuit board. This can also be done using a laser or some other method that is common in the treatment of printed circuit boards. Within this window 7 thus formed, the material of the prepreg 3 is now removed in a next step by means of a laser, so that now a cavity 8 is created, which extends within the window 7 to the top of the core layer 1. The connection pads 2 are now free.
  • the cavity is then cleaned and the surface covered with Au-resist. Then, the cavity is opened in the resist by photo-structuring and the connection pads 2 preferably autocatalytically coated with a nickel / gold layer. Thereafter, the Au resist is removed again.
  • the exposed Cu surface can be contacted with a suitable wet or dry cleaning process.
  • an adhesive 9 is introduced into the cavity, for example with a dispenser, which delivers a required portion. This is shown in FIG.
  • the electronic chip 12 is brought about, which also has on its directed into the interior of the cavity bottom 10 connecting pads 11, which correspond in their arrangement to the connection pads 2 of the circuit board.
  • the chip 12 is now inserted into the cavity and pressed, so that the adhesive 9 also connects to the bottom 10 of the chip 12.
  • the glue now hardens and shrinks.
  • the preferably gold contacts of the chip 12 are firmly attracted to the also preferably gold-plated contact surfaces of the connection pads 2 of the circuit board. This leads to a kind of cold welding between the connection pads 11 of the chip 12 and the connection pads 2 of the circuit board.
  • the connection of the chip to the pads can be supported with ultrasound.
  • the chip 12 is thus electrically and mechanically connected to the connection pads 2 of the circuit board, and is also secured by the cured adhesive 9 mechanically in the cavity.
  • a further layer 14 is laminated to the top of the circuit board, which thus closes the cavity with the chip 12 contained therein.
  • FIGS. 8 to 14 show individual method steps for producing a printed circuit board according to a second exemplary embodiment of the invention.
  • the starting point is a core layer 1 made of a commercially available standard material, ie an insulation.
  • This standard material as the core layer 1 is provided on both sides with a respective conductive layer 5, 6, usually made of copper.
  • Figure 8 shows a section of such a starting material.
  • a window 7 is formed in the copper layer 5 on one side. This can be NEN etching process or using a laser or other method that is common in the treatment of printed circuit boards.
  • the cavity 8 is now generated, in which the electronic chip is to be inserted.
  • This cavity 8 can be manufactured in the same way as has been described in detail in the previous embodiment. As a result, therefore, a cavity 8 has been created in the core layer 1, which reaches down to the inside of the lower copper layer 6 in FIG. This inner side of the copper layer 6 thus forms the bottom of the cavity 8.
  • the chip 12 is pressed ahead with its connection points 11 in the adhesive 9.
  • the adhesive volume is displaced by the chip 12 so that the chip 12 is wetted on its underside and on the sides.
  • the connection pads 11 of the chip 12 are pressed by means of pressure and / or temperature and / or ultrasound on the inside of the copper layer 6 and electrically conductively connected to this conductive layer.
  • the adhesive 9 develops a tensile force, which additionally fixes the chip 12 and supports the contacting. The result of this process is shown in FIG.
  • the cavity 8 is filled with a filler or adhesive customary in electronics, so that the upper side of the filled filler extends approximately flush with the upper side of the core 1.
  • the structuring of the copper layers 5 and 6 on the upper side and on the underside of the core material 1 then takes place in this exemplary embodiment of the method according to the invention.
  • the structuring of the conductive layers 5, 6 results in the layout
  • the elements are patterned using a known and commonly used in printed circuit board manufacturing process. In this case, a laser can be used, which is tuned specifically for the patterning of metallic conductive layers. However, structuring can also be done by etching.
  • the article shown in Figure 14 can now be processed as a core with the known lamination process to a multilayer.
  • insulation layers 15, 16 are laminated together with outer conductive films 17, 18 on both sides of the circuit board of FIG.
  • the insulating layers can be, for example, prepregs, and the conductive layers 17, 18 are copper foils.
  • FIG. 16 shows yet another multilayer printed circuit board which is composed of two printed circuit boards of FIG. The AnAuthierung done by Microvias 19, buried vias 20 and / or through-contacted holes 21. All these contacts are shown here only schematically.
  • FIGS. 8 to 14 differs primarily from the previously described method in that the structuring of the parts of the printed circuit board which are connected to the connection points of the chip takes place only after the connection has been established.
  • FIG. 17 shows yet another example of how electronic components can be accommodated in printed circuit boards using the method presented here.
  • a cavity 8 is formed in the core layer 1, into which an electronic component 12 is inserted. This could be done, for example, as shown in FIG. 14 for this result.
  • a further layer 29 is laminated to the top, which is then already structured, in which then a cavity 28 is introduced.
  • another electronic component 22 is housed, in the same manner as described herein. In order to allow a contacting, this may be a component 22 which is larger than the lower component 12, so that the contacting can take place outside the edges of the cavity 8.
  • step-like cavity With the method according to the invention, it is thus also possible to produce a step-like cavity and to accommodate in this step cavity 8, 28 two electronic components within the same circuit board. Even in the method shown schematically in Figure 17, it is possible to choose a different order of manufacture. For example, first the step-shaped cavity, consisting of the parts 8 and 28 can be produced, and then only the first electronic component 12 can be accommodated in the first cavity 8.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

La présente invention concerne un procédé et une carte à circuit imprimé fabriquée selon ce procédé. Selon cette invention, une cavité est pratiquée dans la carte à circuit imprimé sur une de ses faces planes, par exemple par fraisage libre d'un évidement avec un laser CO2. Le fond de la cavité comporte une structure, c'est-à-dire des plots de connexion, qui servent à assurer la liaison électrique. Une puce est introduite dans la cavité, laquelle puce présente, sur sa face inférieure tournée vers le fond de la cavité, des plots de connexion qui peuvent concorder avec les plots de connexion de la carte à circuit imprimé. Un adhésif est introduit dans la cavité afin de fixer la puce dans la cavité, et la puce est enfoncée dans cet adhésif. Lors du durcissement, l'adhésif se rétracte et comprime les connexions de la puce contre les connexions situées sur le fond de la cavité. Il se forme ainsi une liaison électrique et mécanique solide entre les plots de connexion en contact les uns avec les autres. De plus, la puce est maintenue par l'adhésif. On obtient alors une carte à circuit imprimé comportant une puce qui est maintenue dans une cavité et qui peut être complètement recouverte par rapport à l'extérieur. Les liaisons électriques sont logées de manière sûre dans l'espace situé entre le fond de la cavité et la puce électronique.
PCT/EP2008/001399 2007-02-26 2008-02-22 Procédé d'intégration de puces dans des cavités de cartes à circuit imprimé WO2008104324A1 (fr)

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DE102007010731.7 2007-02-26
DE102007010731A DE102007010731A1 (de) 2007-02-26 2007-02-26 Verfahren zum Einbetten von Chips und Leiterplatte

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US20150007934A1 (en) * 2012-02-21 2015-01-08 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for Producing a Circuit Board and Use of Such a Method
US10187997B2 (en) 2014-02-27 2019-01-22 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
US10219384B2 (en) 2013-11-27 2019-02-26 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Circuit board structure
US10779413B2 (en) 2013-12-12 2020-09-15 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method of embedding a component in a printed circuit board
US11523520B2 (en) 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board

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DE102009027530A1 (de) 2009-07-08 2011-01-20 Robert Bosch Gmbh Leiterplatte
DE112016003990B4 (de) 2015-09-02 2023-09-07 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Elektronisches Gerät mit eingebetteter elektronischer Komponente und Herstellungsverfahren
DE102017102999A1 (de) * 2017-02-15 2018-08-16 Endress+Hauser SE+Co. KG Leiterplatte und Verfahren zur deren Herstellung

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EP0908844A1 (fr) * 1997-10-07 1999-04-14 De La Rue Cartes Et Systemes Carte à microcircuit combinant des plages de contact extérieur et une antenne,et procédé de fabrication d'une telle carte
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US20150007934A1 (en) * 2012-02-21 2015-01-08 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for Producing a Circuit Board and Use of Such a Method
US9648758B2 (en) * 2012-02-21 2017-05-09 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for producing a circuit board and use of such a method
US10219384B2 (en) 2013-11-27 2019-02-26 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Circuit board structure
US11172576B2 (en) 2013-11-27 2021-11-09 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for producing a printed circuit board structure
US10779413B2 (en) 2013-12-12 2020-09-15 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method of embedding a component in a printed circuit board
US10187997B2 (en) 2014-02-27 2019-01-22 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
US11523520B2 (en) 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board

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