WO2008104324A1 - Method for incorporating chips in circuit board cavities - Google Patents

Method for incorporating chips in circuit board cavities Download PDF

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Publication number
WO2008104324A1
WO2008104324A1 PCT/EP2008/001399 EP2008001399W WO2008104324A1 WO 2008104324 A1 WO2008104324 A1 WO 2008104324A1 EP 2008001399 W EP2008001399 W EP 2008001399W WO 2008104324 A1 WO2008104324 A1 WO 2008104324A1
Authority
WO
WIPO (PCT)
Prior art keywords
cavity
chip
circuit board
printed circuit
adhesive
Prior art date
Application number
PCT/EP2008/001399
Other languages
German (de)
French (fr)
Inventor
Roland SCHÖNHOLZ
Original Assignee
Würth Elektronik GmbH & Co. KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Würth Elektronik GmbH & Co. KG filed Critical Würth Elektronik GmbH & Co. KG
Publication of WO2008104324A1 publication Critical patent/WO2008104324A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05573—Single external layer
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    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0125—Shrinkable, e.g. heat-shrinkable polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a method for producing a printed circuit board, which has an active electronic chip in a cavity, and a printed circuit board having an electronic chip in a cavity.
  • the electrical connection between the terminals of the chip and the circuit board is done in such a way that mounted on the outside of the chip connection pads are connected via wires with also mounted on the outside of the circuit board connection pads.
  • the whole can then be potted and laminated with another outer layer.
  • the invention is based on the object to provide a method for embedding electronic chips in printed circuit boards, which can be easily performed and provides good results.
  • the invention proposes a method with the features mentioned in claim 1. Further developments of the invention are the subject of dependent claims.
  • the invention also proposes a printed circuit board with the features of claim 13.
  • the chip is accommodated in the cavity, with its mechanical and electrical connection with the printed circuit board on the bottom of the cavity and the underside of the chip facing this bottom.
  • a customary in electronics adhesive is used, which is introduced untargeted in the cavity.
  • This adhesive cures, it develops a tensile force that causes the chip to more firmly retract into the cavity and connect its leads to conductive areas on the bottom of the cavity. This happens to the extent that not only an electrical connection is done by touching surfaces, but even a mechanical connection in the manner of cold welding.
  • the adhesive is temperature resistant up to a temperature which is higher than the temperatures generated during processing of the printed circuit board. The provided with the chip circuit board can therefore be further treated.
  • the electrical connection between the terminal pads is disposed on the backside of the chip between it and the bottom of the cavity at a protected location.
  • the cavity is covered by means of a further layer which is laminated onto the printed circuit board, in which case the electronic chip is completely embedded in the printed circuit board.
  • the structuring of the bottom of the cavity that is to say the arrangement of the connection pads, can take place prior to the production of the printed circuit board from individual layers, ie before the production of the cavity.
  • connection points of the electronic component and a metallic conductive layer of the printed circuit board and after the curing of the adhesive, the structuring of the metallic conductive layer of the printed circuit board is performed.
  • any suitable means may be used to make the cavity, the invention preferably proposing to make it by means of a laser which opens the top layer to the metallic bottom forming cavity.
  • connection pads on the bottom of the cavity autocatalytically with gold.
  • connection pads on the bottom of the cavity autocatalytically with gold.
  • other metallic surfaces which allow a contacting of the chip.
  • conductive adhesives can additionally support the electrical connection.
  • circuit board assembly is described in claim 13.
  • Figure 1 shows schematically the section through a portion of a printed circuit board at the beginning of the method according to the invention
  • FIG. 2 shows the section of FIG. 1 after opening the upper copper layer
  • FIG. 3 shows the section of FIGS. 1 and 2 after the cavity has been produced
  • Figure 4 shows the same section after the introduction of the adhesive
  • FIG. 5 shows the arrangement of the electronic chip above the cavity
  • FIG. 6 shows the section with the chip inserted and bonded in the cavity
  • FIG. 7 shows the same section after lamination of an outer cover layer
  • Figure 8 shows the section through a printed circuit board beginning of the method according to a second embodiment
  • FIG. 9 shows the same section after a first method step
  • FIG. 10 shows the same section after a second method step
  • FIG. 11 shows a detail of the printed circuit board after a third method step
  • Figure 12 shows the same section of the circuit board with inserted component
  • FIG. 13 shows the section after filling the cavity
  • FIG. 14 shows the printed circuit board structured on both sides
  • FIG. 15 shows the further lamination of the printed circuit board of FIG. 14 on both sides;
  • FIG. 16 shows a schematic section through a multilayer printed circuit board
  • Figure 17 is a simplified section through a further embodiment.
  • the illustrated in Figure 1 in a section the starting point for the inventive method performing circuit board includes a central core layer 1, which in turn can be constructed in multiple layers.
  • the core layer 1 has on its one side, in Figure 1 above, an etched structure with connection pads 2. These are connected via interconnects within the core layer 1 with other connection pads in combination.
  • the upper copper layer 5 is now opened in the area where a cavity is to be attached. This is done by free etching of the copper layer 5 or another suitable method, so that there creates a window 7, where the prepreg 3 forms the top or outside of the circuit board. This can also be done using a laser or some other method that is common in the treatment of printed circuit boards. Within this window 7 thus formed, the material of the prepreg 3 is now removed in a next step by means of a laser, so that now a cavity 8 is created, which extends within the window 7 to the top of the core layer 1. The connection pads 2 are now free.
  • the cavity is then cleaned and the surface covered with Au-resist. Then, the cavity is opened in the resist by photo-structuring and the connection pads 2 preferably autocatalytically coated with a nickel / gold layer. Thereafter, the Au resist is removed again.
  • the exposed Cu surface can be contacted with a suitable wet or dry cleaning process.
  • an adhesive 9 is introduced into the cavity, for example with a dispenser, which delivers a required portion. This is shown in FIG.
  • the electronic chip 12 is brought about, which also has on its directed into the interior of the cavity bottom 10 connecting pads 11, which correspond in their arrangement to the connection pads 2 of the circuit board.
  • the chip 12 is now inserted into the cavity and pressed, so that the adhesive 9 also connects to the bottom 10 of the chip 12.
  • the glue now hardens and shrinks.
  • the preferably gold contacts of the chip 12 are firmly attracted to the also preferably gold-plated contact surfaces of the connection pads 2 of the circuit board. This leads to a kind of cold welding between the connection pads 11 of the chip 12 and the connection pads 2 of the circuit board.
  • the connection of the chip to the pads can be supported with ultrasound.
  • the chip 12 is thus electrically and mechanically connected to the connection pads 2 of the circuit board, and is also secured by the cured adhesive 9 mechanically in the cavity.
  • a further layer 14 is laminated to the top of the circuit board, which thus closes the cavity with the chip 12 contained therein.
  • FIGS. 8 to 14 show individual method steps for producing a printed circuit board according to a second exemplary embodiment of the invention.
  • the starting point is a core layer 1 made of a commercially available standard material, ie an insulation.
  • This standard material as the core layer 1 is provided on both sides with a respective conductive layer 5, 6, usually made of copper.
  • Figure 8 shows a section of such a starting material.
  • a window 7 is formed in the copper layer 5 on one side. This can be NEN etching process or using a laser or other method that is common in the treatment of printed circuit boards.
  • the cavity 8 is now generated, in which the electronic chip is to be inserted.
  • This cavity 8 can be manufactured in the same way as has been described in detail in the previous embodiment. As a result, therefore, a cavity 8 has been created in the core layer 1, which reaches down to the inside of the lower copper layer 6 in FIG. This inner side of the copper layer 6 thus forms the bottom of the cavity 8.
  • the chip 12 is pressed ahead with its connection points 11 in the adhesive 9.
  • the adhesive volume is displaced by the chip 12 so that the chip 12 is wetted on its underside and on the sides.
  • the connection pads 11 of the chip 12 are pressed by means of pressure and / or temperature and / or ultrasound on the inside of the copper layer 6 and electrically conductively connected to this conductive layer.
  • the adhesive 9 develops a tensile force, which additionally fixes the chip 12 and supports the contacting. The result of this process is shown in FIG.
  • the cavity 8 is filled with a filler or adhesive customary in electronics, so that the upper side of the filled filler extends approximately flush with the upper side of the core 1.
  • the structuring of the copper layers 5 and 6 on the upper side and on the underside of the core material 1 then takes place in this exemplary embodiment of the method according to the invention.
  • the structuring of the conductive layers 5, 6 results in the layout
  • the elements are patterned using a known and commonly used in printed circuit board manufacturing process. In this case, a laser can be used, which is tuned specifically for the patterning of metallic conductive layers. However, structuring can also be done by etching.
  • the article shown in Figure 14 can now be processed as a core with the known lamination process to a multilayer.
  • insulation layers 15, 16 are laminated together with outer conductive films 17, 18 on both sides of the circuit board of FIG.
  • the insulating layers can be, for example, prepregs, and the conductive layers 17, 18 are copper foils.
  • FIG. 16 shows yet another multilayer printed circuit board which is composed of two printed circuit boards of FIG. The AnAuthierung done by Microvias 19, buried vias 20 and / or through-contacted holes 21. All these contacts are shown here only schematically.
  • FIGS. 8 to 14 differs primarily from the previously described method in that the structuring of the parts of the printed circuit board which are connected to the connection points of the chip takes place only after the connection has been established.
  • FIG. 17 shows yet another example of how electronic components can be accommodated in printed circuit boards using the method presented here.
  • a cavity 8 is formed in the core layer 1, into which an electronic component 12 is inserted. This could be done, for example, as shown in FIG. 14 for this result.
  • a further layer 29 is laminated to the top, which is then already structured, in which then a cavity 28 is introduced.
  • another electronic component 22 is housed, in the same manner as described herein. In order to allow a contacting, this may be a component 22 which is larger than the lower component 12, so that the contacting can take place outside the edges of the cavity 8.
  • step-like cavity With the method according to the invention, it is thus also possible to produce a step-like cavity and to accommodate in this step cavity 8, 28 two electronic components within the same circuit board. Even in the method shown schematically in Figure 17, it is possible to choose a different order of manufacture. For example, first the step-shaped cavity, consisting of the parts 8 and 28 can be produced, and then only the first electronic component 12 can be accommodated in the first cavity 8.

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Abstract

A method and a circuit board manufactured according to the method are proposed. A cavity is formed in the circuit board starting from one of the flat sides, for example in that a recess is cut out with a CO2 laser. The bottom of the cavity comprises a structuring, which is to say connection pads, which provide the electrical connection. A chip is inserted in the cavity, said chip having connecting pads on the bottom side thereof, facing the bottom of the cavity, said pads being connectable to the connecting pads of the circuit board. An adhesive is introduced in the cavity to secure the chip in the cavity, the chip being pressed into said adhesive. During curing, the adhesive shrinks and thereby presses the connections of the chip against the connections on the bottom of the cavity. A secure electrical and mechanical connection is thus formed between the connecting pads, which are in contact with each other. The chip is also held by the adhesive. The result is a circuit board having a chip present in the cavity, wherein the chip can be completely covered toward the outside. The electrical connections are securely located in the space between the bottom of the cavity and the electronic chip.

Description

Beschreibung description
Verfahren zum Einbinden von Chips in Kavitäten von LeiterplattenMethod for incorporating chips in cavities of printed circuit boards
Die Erfindung betrifft ein Verfahren zum Herstellen einer Leiterplatte, die in einer Kavität einen aktiven elektronischen Chip aufweist, sowie eine einen elektronischen Chip in einer Kavität aufweisende Leiterplatte.The invention relates to a method for producing a printed circuit board, which has an active electronic chip in a cavity, and a printed circuit board having an electronic chip in a cavity.
Es ist bekannt, dass man für spezielle Anwendungen aktive elektronische Bauteile, so genannte Chips, in Vertiefungen von Leiterplatten unterbringen kann. Dies ist beispielsweise bei Chipkarten bekannt. Dies hat den Vorteil, dass die Leiterplatten mit den Chips flach sind.It is known that for special applications it is possible to accommodate active electronic components, so-called chips, in printed circuit board recesses. This is known, for example, in smart cards. This has the advantage that the printed circuit boards are flat with the chips.
Bei den bisherigen Leiterplatten geschieht die elektrische Verbindung zwischen den Anschlüssen des Chips und der Leiterplatte in der Weise, dass auf der Außenseite des Chips angebrachte Anschlusspads über Drähte mit ebenfalls auf der Außenseite der Leiterplatte angebrachten Anschlusspads verbunden werden. Das ganze kann dann vergossen und mit einer weiteren äußeren Schicht laminiert werden.In the previous circuit boards, the electrical connection between the terminals of the chip and the circuit board is done in such a way that mounted on the outside of the chip connection pads are connected via wires with also mounted on the outside of the circuit board connection pads. The whole can then be potted and laminated with another outer layer.
Ebenfalls bekannt sind Verfahren, bei denen in der Leiterplatten eingebettete Chips von außen mittels Mikrovias direkt angebunden werden. Diese Chips werden mit verpresst.Also known are methods in which chips embedded in the printed circuit boards are directly connected externally by means of microvia. These chips are pressed with.
Der Erfindung liegt die Aufgabe zu Grunde, ein Verfahren zum Einbetten elektronischer Chips in Leiterplatten zu schaffen, das sich einfach durchführen lässt und gute Ergebnisse liefert.The invention is based on the object to provide a method for embedding electronic chips in printed circuit boards, which can be easily performed and provides good results.
Zur Lösung dieser Aufgabe schlägt die Erfindung ein Verfahren mit den im Anspruch 1 genannten Merkmalen vor. Weiterbildungen der Erfindung sind Gegenstand von Unteransprüchen. Die Erfindung schlägt ebenfalls eine Leiterplatte mit den Merkmalen des Anspruchs 13 vor.To solve this problem, the invention proposes a method with the features mentioned in claim 1. Further developments of the invention are the subject of dependent claims. The invention also proposes a printed circuit board with the features of claim 13.
Bei dem von der Erfindung vorgeschlagenen Verfahren wird der Chip in der Kavität untergebracht, wobei seine mechanische und elektrische Verbindung mit der Leiterplatte auf dem Boden der Kavität und der diesen Boden zugewandten Unterseite des Chips geschieht. Dabei wird ein in der Elektronik üblicher Kleber verwendet, der ungezielt in die Kavität eingebracht wird. Beim Aushärten dieses Klebers entwickelt er eine Zugkraft, die dazu führt, dass der Chip fester in die Kavität eingezogen wird und sich seine Anschlüsse mit leitenden Bereichen auf dem Boden der Kavität verbinden. Dies geschieht soweit, dass nicht nur eine elektrische Verbindung durch ein Berühren von Flächen geschieht, sondern sogar eine mechanische Verbindung nach Art einer Kaltverschweißung. Der Kleber ist bis zu einer Temperatur temperaturbeständig, die höher liegt als die beim Verarbeiten der Leiterplatte entstehenden Temperaturen. Die mit dem Chip versehene Leiterplatte kann also weiterbehandelt werden.In the method proposed by the invention, the chip is accommodated in the cavity, with its mechanical and electrical connection with the printed circuit board on the bottom of the cavity and the underside of the chip facing this bottom. In this case, a customary in electronics adhesive is used, which is introduced untargeted in the cavity. As this adhesive cures, it develops a tensile force that causes the chip to more firmly retract into the cavity and connect its leads to conductive areas on the bottom of the cavity. This happens to the extent that not only an electrical connection is done by touching surfaces, but even a mechanical connection in the manner of cold welding. The adhesive is temperature resistant up to a temperature which is higher than the temperatures generated during processing of the printed circuit board. The provided with the chip circuit board can therefore be further treated.
Die elektrische Verbindung zwischen den Anschlusspads ist auf der Rückseite des Chips zwischen diesem und dem Boden der Kavität an einer geschützten Stelle angeordnet.The electrical connection between the terminal pads is disposed on the backside of the chip between it and the bottom of the cavity at a protected location.
In Weiterbildung der Erfindung kann vorgesehen sein, dass die Kavität mithilfe einer weiteren Schicht abgedeckt wird, die auf die Leiterplatte auflaminiert wird, wobei dann der elektronische Chip vollständig in der Leiterplatte eingebettet ist.In a further development of the invention it can be provided that the cavity is covered by means of a further layer which is laminated onto the printed circuit board, in which case the electronic chip is completely embedded in the printed circuit board.
Die Strukturierung des Bodens der Kavität, also die Anordnung der Anschlusspads, kann schon vor der Herstellung der Leiterplatte aus einzelnen Schichten geschehen, also vor der Herstellung der Kavität. Es ist aber ebenfalls möglich und wird von der Erfindung vorgeschlagen, die notwendige Strukturierung des Bodens der Kavität erst nach dem Herstellen der Kavität durchzuführen.The structuring of the bottom of the cavity, that is to say the arrangement of the connection pads, can take place prior to the production of the printed circuit board from individual layers, ie before the production of the cavity. However, it is also possible and is proposed by the invention to carry out the necessary structuring of the bottom of the cavity only after the production of the cavity.
Eine nochmals weitere Möglichkeit besteht darin, dass nach Herstellung der elektrisch leitenden Verbindung zwischen den Anschlussstellen des elektronischen Bauteils und einer metallischen leitenden Schicht der Leiterplatte und nach dem Aushärten des Klebers die Strukturierung der metallischen leitenden Schicht der Leiterplatte durchgeführt wird.Yet another possibility is that after the electrically conductive connection between the connection points of the electronic component and a metallic conductive layer of the printed circuit board and after the curing of the adhesive, the structuring of the metallic conductive layer of the printed circuit board is performed.
Zur Herstellung der Kavität kann jedes geeignete Mittel verwendet werden, wobei die Erfindung vorzugsweise die Herstellung mithilfe eines Lasers vorschlägt, der die obere Schicht bis zu der metallischen den Boden der Kavität bildenden Schicht öffnet.Any suitable means may be used to make the cavity, the invention preferably proposing to make it by means of a laser which opens the top layer to the metallic bottom forming cavity.
In Weiterbildung der Erfindung kann vorgesehen sein, die Anschlusspads auf dem Boden der Kavität autokatalytisch mit Gold zu beschichten. Es ist aber auch möglich, andere metallische Oberflächen zu verwenden, die eine Kontaktierung des Chips ermöglichen.In a further development of the invention can be provided to coat the connection pads on the bottom of the cavity autocatalytically with gold. But it is also possible to use other metallic surfaces, which allow a contacting of the chip.
Beim Einsetzen des Chips kann erfindungsgemäß vorgesehen sein, den Chip in die Kavität einzudrücken, um ihn fest gegen den Kleber anzudrücken und den Kleber gleichmäßig zur Anlage an der Unterseite des Chips zu bringen. Bekannte, leitfähige Kleber können die elektrische Verbindung zusätzlich unterstützen.When inserting the chip can be inventively provided to depress the chip in the cavity to press firmly against the adhesive and to bring the adhesive evenly to rest against the bottom of the chip. Known, conductive adhesives can additionally support the electrical connection.
Der von der Erfindung vorgeschlagene Leiterplattenaufbau ist im Anspruch 13 beschrieben.The proposed by the invention circuit board assembly is described in claim 13.
Weitere Merkmale, Einzelheiten und Vorzüge der Erfindung ergeben sich aus den Ansprüchen und der Zusammenfassung, deren beider Wortlaut durch Bezugnahme zum Inhalt der Beschreibung gemacht wird, - A -Further features, details and advantages of the invention will become apparent from the claims and the abstract, the wording of which is incorporated by reference into the content of the description, - A -
der folgenden Beschreibung bevorzugter Ausführungsformen der Erfindung sowie anhand der Zeichnung. Hierbei zeigen:the following description of preferred embodiments of the invention and with reference to the drawing. Hereby show:
Figur 1 schematisch den Schnitt durch einen Abschnitt einer Leiterplatte zu Beginn des erfindungsgemäßen Verfahrens;Figure 1 shows schematically the section through a portion of a printed circuit board at the beginning of the method according to the invention;
Figur 2 den Schnitt der Figur 1 nach dem öffnen der oberen Kupferschicht;FIG. 2 shows the section of FIG. 1 after opening the upper copper layer;
Figur 3 den Schnitt der Figur 1 und 2 nach Herstellen der Kavität;FIG. 3 shows the section of FIGS. 1 and 2 after the cavity has been produced;
Figur 4 den gleichen Schnitt nach dem Einbringen des Klebers;Figure 4 shows the same section after the introduction of the adhesive;
Figur 5 die Anordnung des elektronischen Chips oberhalb der Kavität;FIG. 5 shows the arrangement of the electronic chip above the cavity;
Figur 6 den Schnitt mit dem in der Kavität eingesetzten und verklebten Chip;FIG. 6 shows the section with the chip inserted and bonded in the cavity;
Figur 7 den gleichen Schnitt nach Auflaminieren einer äußeren Deckschicht;FIG. 7 shows the same section after lamination of an outer cover layer;
Figur 8 den Schnitt durch eine Leiterplatte Beginn des Verfahrens nach einer zweiten Ausführungsform;Figure 8 shows the section through a printed circuit board beginning of the method according to a second embodiment;
Figur 9 den gleichen Abschnitt nach einem ersten Verfahrensschritt;FIG. 9 shows the same section after a first method step;
Figur 10 den gleichen Abschnitt nach einem zweiten Verfahrensschritt;FIG. 10 shows the same section after a second method step;
Figur 11 einen Ausschnitt der Leiterplatte nach einem dritten Verfahrensschritt;FIG. 11 shows a detail of the printed circuit board after a third method step;
Figur 12 den gleichen Ausschnitt aus der Leiterplatte mit eingesetztem Bauteil; Figur 13 den Schnitt nach dem Ausfüllen der Kavität;Figure 12 shows the same section of the circuit board with inserted component; FIG. 13 shows the section after filling the cavity;
Figur 14 die auf beiden Seiten strukturierte Leiterplatte;FIG. 14 shows the printed circuit board structured on both sides;
Figur 15 die weitere Laminierung der Leiterplatte der Figur 14 auf beiden Seiten;FIG. 15 shows the further lamination of the printed circuit board of FIG. 14 on both sides;
Figur 16 einen schematischen Schnitt durch eine Multilayerleiterplatte;FIG. 16 shows a schematic section through a multilayer printed circuit board;
Figur 17 einen vereinfachten Schnitt durch eine weitere Ausführungsform.Figure 17 is a simplified section through a further embodiment.
Die in Figur 1 in einem Schnitt dargestellte den Ausgangspunkt für das erfindungsgemäße Verfahren darstellende Leiterplatte enthält eine mittlere Kernschicht 1 , die ihrerseits mehrlagig aufgebaut sein kann. Die Kernschicht 1 weist an ihrer einen Seite, in Figur 1 oben, eine geätzte Struktur mit Anschlusspads 2 auf. Diese stehen über Leiterbahnen innerhalb der Kernschicht 1 mit anderen Anschlusspads in Verbindung.The illustrated in Figure 1 in a section the starting point for the inventive method performing circuit board includes a central core layer 1, which in turn can be constructed in multiple layers. The core layer 1 has on its one side, in Figure 1 above, an etched structure with connection pads 2. These are connected via interconnects within the core layer 1 with other connection pads in combination.
Oberhalb und unterhalb der Kernschicht 1 ist diese mit jeweils einem Prepreg 3, 4 verbunden, und die beiden Außenseiten sind mit einer Kupferfolie 5, 6 versehen, wobei die gesamte Leiterplatte verpresst ist.Above and below the core layer 1, this is connected to a respective prepreg 3, 4, and the two outer sides are provided with a copper foil 5, 6, wherein the entire circuit board is pressed.
Als erster Schritt bei dem dargestellten Ausführungsbeispiel wird nun die obere Kupferschicht 5 in dem Bereich, wo eine Kavität angebracht werden soll, geöffnet. Dies geschieht durch Freiätzen der Kupferschicht 5 oder ein anderes geeignetes Verfahren, so dass dort ein Fenster 7 entsteht, wo der Prepreg 3 die Oberseite beziehungsweise Außenseite der Leiterplatte bildet. Dies kann auch mithilfe eines Lasers oder mit einer sonstigen Methode geschehen, die bei der Behandlung von Leiterplatten üblich ist. Innerhalb dieses so gebildeten Fensters 7 wird nun in einem nächsten Schritt mithilfe eines Lasers das Material des Prepregs 3 entfernt, so dass jetzt eine Kavität 8 entsteht, die innerhalb des Fensters 7 bis auf die Oberseite der Kernschicht 1 reicht. Die Anschlusspads 2 liegen jetzt frei.As a first step in the illustrated embodiment, the upper copper layer 5 is now opened in the area where a cavity is to be attached. This is done by free etching of the copper layer 5 or another suitable method, so that there creates a window 7, where the prepreg 3 forms the top or outside of the circuit board. This can also be done using a laser or some other method that is common in the treatment of printed circuit boards. Within this window 7 thus formed, the material of the prepreg 3 is now removed in a next step by means of a laser, so that now a cavity 8 is created, which extends within the window 7 to the top of the core layer 1. The connection pads 2 are now free.
Anschließend wird die Kavität gesäubert und die Oberfläche mit Au- resist abgedeckt. Dann wird die Kavität im Resist durch Fotostrukturieren geöffnet und die Anschlusspads 2 vorzugsweise autokatalytisch mit einer Nickel/Goldschicht überzogen. Danach wird das Au-Resist wieder entfernt.The cavity is then cleaned and the surface covered with Au-resist. Then, the cavity is opened in the resist by photo-structuring and the connection pads 2 preferably autocatalytically coated with a nickel / gold layer. Thereafter, the Au resist is removed again.
Alternativ kann die freiliegende Cu- Oberfläche mit einem geeigneten nassen oder trockenen Reinigungsverfahren kontaktierfähig gemacht werden.Alternatively, the exposed Cu surface can be contacted with a suitable wet or dry cleaning process.
Dies ist im Einzelnen nicht dargestellt, da es sich um in der Leiterplattenherstellung übliche Vorgänge handelt. Anschließend wird in einem nächsten Schritt ein Kleber 9 in die Kavität eingebracht, beispielsweise mit einem Dispenser, der eine erforderliche Portion abgibt. Dies ist in Figur 4 dargestellt.This is not shown in detail, since it is common in printed circuit board manufacturing processes. Subsequently, in a next step, an adhesive 9 is introduced into the cavity, for example with a dispenser, which delivers a required portion. This is shown in FIG.
Nun wird der elektronische Chip 12 herbeigeführt, der auf seiner in das Innere der Kavität gerichteten Unterseite 10 ebenfalls Anschlusspads 11 aufweist, die in ihrer Anordnung den Anschlusspads 2 der Leiterplatte entsprechen. Dies ist schematisch in Figur 5 darzustellen versucht worden. Der Chip 12 wird nun in die Kavität eingesetzt und angedrückt, so dass sich der Kleber 9 auch mit der Unterseite 10 des Chips 12 verbindet. Dies ist in Figur 6 dargestellt. Der Kleber härtet nun aus und schrumpft dabei. Dabei werden die vorzugsweise Gold-Kontakte des Chips 12 fest an die ebenfalls vorzugsweise vergoldeten Kontaktflächen der Anschlusspads 2 der Leiterplatte angezogen. Dies führt zu einer Art Kaltverschweißung zwischen den Anschlusspads 11 des Chips 12 und den Anschlusspads 2 der Leiterplatte. Die Verbindung des Chips mit den Anschlussflächen kann mit Ultraschall unterstützt werden.Now, the electronic chip 12 is brought about, which also has on its directed into the interior of the cavity bottom 10 connecting pads 11, which correspond in their arrangement to the connection pads 2 of the circuit board. This has been attempted schematically in FIG. The chip 12 is now inserted into the cavity and pressed, so that the adhesive 9 also connects to the bottom 10 of the chip 12. This is shown in FIG. The glue now hardens and shrinks. In this case, the preferably gold contacts of the chip 12 are firmly attracted to the also preferably gold-plated contact surfaces of the connection pads 2 of the circuit board. This leads to a kind of cold welding between the connection pads 11 of the chip 12 and the connection pads 2 of the circuit board. The connection of the chip to the pads can be supported with ultrasound.
Der Chip 12 ist also mit den Anschlusspads 2 der Leiterplatte elektrisch und mechanisch verbunden, und wird außerdem von dem ausgehärteten Kleber 9 mechanisch in der Kavität gesichert.The chip 12 is thus electrically and mechanically connected to the connection pads 2 of the circuit board, and is also secured by the cured adhesive 9 mechanically in the cavity.
Gegebenenfalls ist es auch möglich, den zwischen dem Chip 12 und den Wänden der Kavität gebildeten Spalt auszugießen.Optionally, it is also possible to pour out the gap formed between the chip 12 and the walls of the cavity.
Nach dem Aushärten des Klebers 9 wird eine weitere Schicht 14 auf die Oberseite der Leiterplatte auflaminiert, die damit die Kavität mit dem darin enthaltenen Chip 12 abschließt.After curing of the adhesive 9, a further layer 14 is laminated to the top of the circuit board, which thus closes the cavity with the chip 12 contained therein.
Die elektrische Einbindung des Chips in das elektronische Netzwerk erfolgt über innenliegende Leiterbahnen.The electrical integration of the chip in the electronic network via internal tracks.
Was hier für einen einzelnen Chip 12 an der Oberseite der Leiterplatte gezeigt und beschrieben wurde, kann selbstverständlich für mehrere derartige Chips durchgeführt werden, die auch auf beiden Seiten der Kernschicht 1 beziehungsweise in unterschiedlichen Lagen/Tiefen des Multilayeraufbaus vorhanden sein können.Of course, what has been shown and described herein for a single chip 12 on top of the circuit board may be performed for a plurality of such chips, which may also be present on both sides of the core layer 1 and at different layers / depths of the multilayer structure.
Die Figuren 8 bis 14 zeigen einzelne Verfahrensschritte zum Herstellen einer Leiterplatte nach einem zweiten Ausführungsbeispiel der Erfindung. Ausgangspunkt ist eine Kernschicht 1 aus einem handelsüblichen Standardmaterial, also einer Isolation. Dieses Standardmaterial als Kernschicht 1 ist auf beiden Seiten mit jeweils einer leitenden Schicht 5, 6 versehen, üblicherweise aus Kupfer bestehend. Figur 8 zeigt einen Ausschnitt aus einem solchen Ausgangsmaterial. In einem ersten Verfahrensschritt, dessen Ergebnis in Figur 9 dargestellt ist, wird in der Kupferschicht 5 auf einer Seite ein Fenster 7 gebildet. Dies kann durch ei- nen Ätzprozess oder auch mithilfe eines Lasers oder mit einer sonstigen Methode geschehen, die bei der Behandlung von Leiterplatten üblich ist.FIGS. 8 to 14 show individual method steps for producing a printed circuit board according to a second exemplary embodiment of the invention. The starting point is a core layer 1 made of a commercially available standard material, ie an insulation. This standard material as the core layer 1 is provided on both sides with a respective conductive layer 5, 6, usually made of copper. Figure 8 shows a section of such a starting material. In a first method step, the result of which is shown in FIG. 9, a window 7 is formed in the copper layer 5 on one side. This can be NEN etching process or using a laser or other method that is common in the treatment of printed circuit boards.
Nach dem öffnen der Kupferschicht wird nun die Kavität 8 erzeugt, in die der elektronische Chip eingefügt werden soll. Diese Kavität 8 kann in der gleichen Weise hergestellt werden, wie dies bei der vorhergehenden Ausführungsform im einzelnen beschrieben wurde. Als Ergebnis ist also eine Kavität 8 in der Kernschicht 1 entstanden, die bis auf die Innenseite der in Figur 10 unteren Kupferschicht 6 reicht. Diese Innenseite der Kupferschicht 6 bildet also den Boden der Kavität 8.After opening the copper layer, the cavity 8 is now generated, in which the electronic chip is to be inserted. This cavity 8 can be manufactured in the same way as has been described in detail in the previous embodiment. As a result, therefore, a cavity 8 has been created in the core layer 1, which reaches down to the inside of the lower copper layer 6 in FIG. This inner side of the copper layer 6 thus forms the bottom of the cavity 8.
Nun wird in die Kavität 8 Kleber 9 eingefüllt, in ähnlicher Weise wie bei der vorhergehenden Ausführungsform. Das Ergebnis zeigt die Figur 11.Now glue 9 is filled in the cavity 8 in a manner similar to the previous embodiment. The result is shown in FIG. 11.
Anschließend wird der Chip 12 mit seinen Anschlussstellen 11 voraus in den Kleber 9 eingedrückt. Das Klebervolumen wird von dem Chip 12 so verdrängt, dass der Chip 12 an seiner Unterseite und an den Seiten benetzt wird. Die Anschlusspads 11 des Chips 12 werden mithilfe von Druck und/oder Temperatur und/oder mit Ultraschall auf die Innenseite der Kupferschicht 6 angedrückt und mit dieser leitfähigen Schicht elektrisch leitend verbunden. Der Kleber 9 entwickelt eine Zugkraft, die den Chip 12 zusätzlich fixiert und die Kontaktierung unterstützt. Das Ergebnis dieses Vorgangs ist in Figur 12 dargestellt.Subsequently, the chip 12 is pressed ahead with its connection points 11 in the adhesive 9. The adhesive volume is displaced by the chip 12 so that the chip 12 is wetted on its underside and on the sides. The connection pads 11 of the chip 12 are pressed by means of pressure and / or temperature and / or ultrasound on the inside of the copper layer 6 and electrically conductively connected to this conductive layer. The adhesive 9 develops a tensile force, which additionally fixes the chip 12 and supports the contacting. The result of this process is shown in FIG.
Anschließend wird die Kavität 8 mit einem in der Elektronik üblichen Füllstoff beziehungsweise Kleber aufgefüllt, so dass die Oberseite des eingefüllten Füllstoffs ungefähr bündig mit der Oberseite des Kerns 1 verläuft.Subsequently, the cavity 8 is filled with a filler or adhesive customary in electronics, so that the upper side of the filled filler extends approximately flush with the upper side of the core 1.
Anschließend erfolgt bei diesem Ausführungsbeispiel des erfindungsgemäßen Verfahrens die Strukturierung der Kupferschichten 5 und 6 auf der Oberseite und auf der Unterseite des Kernmaterials 1. Aus der Strukturierung der leitfähigen Schichten 5, 6 ergeben sich die Lay- outelemente, Leiterbahnen und die Anschlusselemente für die Kontak- tierung des Chips 12. Die Strukturierung erfolgt mit einem bekannten und bei der Leiterplattenherstellung üblicherweise verwendeten Verfahren. Hierbei kann ein Laser zum Einsatz kommen, der speziell für das Strukturieren von metallischen leitenden Schichten abgestimmt ist. Die Strukturierung kann allerdings auch ätztechnisch erfolgen.The structuring of the copper layers 5 and 6 on the upper side and on the underside of the core material 1 then takes place in this exemplary embodiment of the method according to the invention. The structuring of the conductive layers 5, 6 results in the layout The elements are patterned using a known and commonly used in printed circuit board manufacturing process. In this case, a laser can be used, which is tuned specifically for the patterning of metallic conductive layers. However, structuring can also be done by etching.
Der in Figur 14 dargestellte Gegenstand kann nun als Kern mit den bekannten Laminationsverfahren zu einem Multilayer verarbeitet werden. Beispielsweise werden auf beiden Seiten der Leiterplatte der Figur 14 Isolationsschichten 15, 16 zusammen mit äußeren leitfähigen Folien 17, 18 laminiert. Bei den Isolationsschichten kann es sich beispielsweise um Prepregs handeln, und bei den leitfähigen Schichten 17, 18 um Kupferfolien.The article shown in Figure 14 can now be processed as a core with the known lamination process to a multilayer. For example, insulation layers 15, 16 are laminated together with outer conductive films 17, 18 on both sides of the circuit board of FIG. The insulating layers can be, for example, prepregs, and the conductive layers 17, 18 are copper foils.
Figur 16 zeigt eine nochmals weitere Multilayerleiterplatte, die aus zwei Leiterplatten der Figur 14 zusammengesetzt ist. Die Ankontaktierung erfolgt durch Microvias 19, vergrabene Vias 20 und/oder durch durch- kontaktierte Löcher 21. Alle diese Kontaktierungen sind hier nur schematisch dargestellt.FIG. 16 shows yet another multilayer printed circuit board which is composed of two printed circuit boards of FIG. The Ankontaktierung done by Microvias 19, buried vias 20 and / or through-contacted holes 21. All these contacts are shown here only schematically.
Das in den Figuren 8 bis 14 beschriebene Verfahren unterscheidet sich in erster Linie dadurch von dem vorher beschriebenen Verfahren, dass die Strukturierung der Teile der Leiterplatte, die mit den Anschlussstellen des Chips in Verbindung stehen, erst nach dem Herstellen dieser Verbindung erfolgt.The method described in FIGS. 8 to 14 differs primarily from the previously described method in that the structuring of the parts of the printed circuit board which are connected to the connection points of the chip takes place only after the connection has been established.
In der Figur 17 ist nun noch ein weiteres Beispiel dargestellt, wie man mit dem hier vorgestellten Verfahren elektronische Bauteile in Leiterplatten unterbringen kann. Zunächst ist, wie bei den bisher beschriebenen Ausführungsformen, in der Kernschicht 1 eine Kavität 8 gebildet, in die ein elektronisches Bauteil 12 eingesetzt ist. Dies könnte beispielsweise so geschehen seien, die diesem Ergebnis in Figur 14 dargestellt ist. An- schließend wird auf die Oberseite, die dann schon strukturiert ist, eine weitere Schicht 29 auflaminiert, in die dann eine Kavität 28 eingebracht wird. In dieser Kavität wird dann ein weiteres elektronisches Bauteil 22 untergebracht, in der gleichen Weise, wie dies hierin beschrieben wurde. Um eine Kontaktierung zu ermöglichen, kann es sich dabei um ein Bauteil 22 handeln, das größer ist als das untere Bauteil 12, so dass die Kontaktierung außerhalb der Ränder der Kavität 8 erfolgen kann. Mit dem Verfahren nach der Erfindung ist es also auch möglich, eine stufenartige Kavität herzustellen und in diese Stufenkavität 8, 28 zwei elektronische Bauteile innerhalb der gleichen Leiterplatte unterzubringen. Auch bei dem in Figur 17 schematisch dargestellten Verfahren ist es möglich, eine andere Reihenfolge der Herstellung zu wählen. Beispielsweise kann zunächst die stufenförmige Kavität, bestehend aus den Teilen 8 und 28 hergestellt werden, und anschließend erst das erste elektronische Bauteil 12 in der ersten Kavität 8 untergebracht werden. FIG. 17 shows yet another example of how electronic components can be accommodated in printed circuit boards using the method presented here. First, as in the previously described embodiments, a cavity 8 is formed in the core layer 1, into which an electronic component 12 is inserted. This could be done, for example, as shown in FIG. 14 for this result. At- closing a further layer 29 is laminated to the top, which is then already structured, in which then a cavity 28 is introduced. In this cavity, then another electronic component 22 is housed, in the same manner as described herein. In order to allow a contacting, this may be a component 22 which is larger than the lower component 12, so that the contacting can take place outside the edges of the cavity 8. With the method according to the invention, it is thus also possible to produce a step-like cavity and to accommodate in this step cavity 8, 28 two electronic components within the same circuit board. Even in the method shown schematically in Figure 17, it is possible to choose a different order of manufacture. For example, first the step-shaped cavity, consisting of the parts 8 and 28 can be produced, and then only the first electronic component 12 can be accommodated in the first cavity 8.

Claims

Patentansprüche claims
1. Verfahren zum Anordnen elektronischer Chips (12) in Leiterplatten, mit folgenden Verfahrensschritten:1. A method for arranging electronic chips (12) in printed circuit boards, comprising the following method steps:
1.1 in einer Leiterplatte wird eine Kavität (8) gebildet,1.1 in a circuit board, a cavity (8) is formed,
1.2 der Boden der Kavität (8) wird zur Bildung von Anschlussstellen (2) der Leiterplatte strukturiert,1.2 the bottom of the cavity (8) is structured to form connection points (2) of the printed circuit board,
1.3 in die Kavität (8) wird Kleber (9) eingebracht,1.3 in the cavity (8) adhesive (9) is introduced,
1.4 ein mit Anschlussstellen (11 ) versehener Chip (12) wird mit den Anschlussstellen (11 ) voraus in die mit Kleber (9) versehene Kavität (8) eingebracht,1.4 a chip (12) provided with connection points (11) is introduced in advance into the cavity (8) provided with adhesive (9) with the connection points (11),
1.5 beim Aushärten des Klebers (9) werden durch das Aushärten des Klebers (9) leitende Bereiche der Leiterplatte und die Anschlussstellen (11 ) des Chips (12) miteinander elektrisch leitend verbunden, insbesondere stoffschlüssig verbunden.1.5 during curing of the adhesive (9) by the curing of the adhesive (9) conductive areas of the circuit board and the connection points (11) of the chip (12) are electrically conductively connected, in particular materially connected.
2. Verfahren nach Anspruch 1 , bei dem auf die mit dem Chip (12) versehene Leiterplatte zur Abdeckung der Kavität (8) in eine weitere Schicht (14) auflaminiert wird.2. The method of claim 1, wherein on the with the chip (12) provided printed circuit board for covering the cavity (8) in a further layer (14) is laminated.
3. Verfahren nach Anspruch 1 oder 2, bei dem der spätere Boden der Kavität (8) vor dem Herstellen der Kavität (8) strukturiert wird.3. The method of claim 1 or 2, wherein the subsequent bottom of the cavity (8) before the production of the cavity (8) is structured.
4. Verfahren nach Anspruch 1 oder 2, bei dem der Boden der Kavität (8) nach dem Herstellen der Kavität (8) strukturiert wird.4. The method according to claim 1 or 2, wherein the bottom of the cavity (8) after the production of the cavity (8) is structured.
5. Verfahren nach Anspruch 1 oder 2, bei dem der Boden der Kavität (8) nach Herstellen der elektrisch leitenden Verbindung zwischen Bereichen der Leiterplatte und den Anschlussstellen (11 ) des Chips (12) strukturiert wird. 5. The method of claim 1 or 2, wherein the bottom of the cavity (8) after making the electrically conductive connection between areas of the circuit board and the connection points (11) of the chip (12) is structured.
6. Verfahren nach einem der vorhergehenden Ansprüche, bei dem die Kavität (8) mithilfe eines Lasers, insbesondere eines CO2 Lasers, hergestellt wird.6. The method according to any one of the preceding claims, wherein the cavity (8) by means of a laser, in particular a CO2 laser, is produced.
7. Verfahren nach einem der vorhergehenden Ansprüche, bei dem die auf dem Boden der Kavität (8) vorhandenen Anschlusspads (2) autokatalytisch mit Gold beschichtet werden.7. The method according to any one of the preceding claims, wherein the on the bottom of the cavity (8) existing connection pads (2) are coated autocatalytically with gold.
8. Verfahren nach einem der vorhergehenden Ansprüche, bei dem der mit den Anschlussstellen (11 ) versehene Chip (12) gegen die Anschlusspads (2) angedrückt wird.8. The method according to any one of the preceding claims, wherein the provided with the connection points (11) chip (12) against the connection pads (2) is pressed.
9. Verfahren nach einem der vorhergehenden Ansprüche, bei dem in der Leiterplatte eine stufenförmige Kavität (8, 28) gebildet wird.9. The method according to any one of the preceding claims, wherein in the circuit board, a step-shaped cavity (8, 28) is formed.
10. Verfahren nach Anspruch 9, bei dem in jedem Teil der stufenförmigen Kavität (8, 28) ein Chip (12, 22) angeordnet wird.10. The method of claim 9, wherein in each part of the stepped cavity (8, 28) a chip (12, 22) is arranged.
11. Verfahren nach Anspruch 10, bei dem der zweite Teil (28) der stufenförmigen Kavität (8, 28) nach dem Anordnen des Chips (12) in dem ersten Teil (8) der stufenförmigen Kavität (8, 28) gebildet wird.11. The method of claim 10, wherein the second part (28) of the stepped cavity (8, 28) after arranging the chip (12) in the first part (8) of the stepped cavity (8, 28) is formed.
12. Verfahren nach Anspruch 10, bei dem der zweite Teil (28) der stufenförmigen Kavität (8, 28) vor dem Anordnen des Chips (12) in dem ersten Teil (8) der stufenförmigen Kavität (8, 28) gebildet wird.12. The method of claim 10, wherein the second part (28) of the stepped cavity (8, 28) before arranging the chip (12) in the first part (8) of the stepped cavity (8, 28) is formed.
13. Leiterplatte, mit mindestens einer in ihr gebildeten Kavität (8), deren Boden Anschlusspads (2) aufweist, sowie mit einem in der Kavität (8) angeordneten elektronischen Chip (12), der auf seiner dem Boden der Kavität (8) zugewandten Unterseite (10) Anschlusspads (11 ) aufweist, mit denen er mit den Anschlusspads (2) der Leiterplatte elektrisch leitend und mechanisch verbunden ist.13. Circuit board, with at least one cavity formed in it (8), the bottom of which has connection pads (2), as well as with an in the cavity (8) arranged electronic chip (12) on its bottom of the cavity (8) facing Underside (10) Connection pads (11), with which it is electrically conductively and mechanically connected to the connection pads (2) of the circuit board.
14. Leiterplatte nach Anspruch 13, bei der die Kavität (8) mit dem darin enthaltenen elektronischen Chip (12) von einem weiteren Layer (14) abgedeckt ist, der mit der Leiterplatte laminiert ist.14. The printed circuit board according to claim 13, wherein the cavity (8) with the electronic chip (12) contained therein is covered by another layer (14) which is laminated to the printed circuit board.
15. Leiterplatte, insbesondere nach Anspruch 13 oder 14, herstellbar nach dem Verfahren nach einem der Ansprüche 1 bis 8. 15. Printed circuit board, in particular according to claim 13 or 14, producible by the method according to one of claims 1 to 8.
PCT/EP2008/001399 2007-02-26 2008-02-22 Method for incorporating chips in circuit board cavities WO2008104324A1 (en)

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