WO2008069074A1 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- WO2008069074A1 WO2008069074A1 PCT/JP2007/072953 JP2007072953W WO2008069074A1 WO 2008069074 A1 WO2008069074 A1 WO 2008069074A1 JP 2007072953 W JP2007072953 W JP 2007072953W WO 2008069074 A1 WO2008069074 A1 WO 2008069074A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 149
- 238000000034 method Methods 0.000 title description 9
- 238000004519 manufacturing process Methods 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims description 24
- 150000001875 compounds Chemical class 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- -1 nitride compound Chemical class 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 239000011733 molybdenum Substances 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 13
- 230000006378 damage Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 33
- 229910002601 GaN Inorganic materials 0.000 description 17
- 238000010586 diagram Methods 0.000 description 17
- 230000003071 parasitic effect Effects 0.000 description 15
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 240000004050 Pentaglottis sempervirens Species 0.000 description 1
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a high-frequency Ga N (gallium nitride) FET (field effect transistor) and a method for manufacturing the same.
- a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a high-frequency Ga N (gallium nitride) FET (field effect transistor) and a method for manufacturing the same.
- Ga N gallium nitride
- FET field effect transistor
- a field plate is provided as a fourth electrode on an insulating layer between a gate electrode and a source electrode, and the field plate is electrically connected to the source electrode, whereby electric field concentration in the gate electrode is achieved.
- a technique for mitigating this problem and preventing the destruction of semiconductor elements is known.
- FIG. 11 is a cross-sectional view showing an example of a semiconductor device provided with such a field plate electrode.
- a GaN layer 48 and an AlGaN (aluminum gallium nitride) layer 49 are laminated on a semi-insulating SiC (silicon carbide) 47, and on the surface of the AlGaN layer 49.
- a gate electrode 50 that is a Schottky electrode, and a source electrode 51 and a drain electrode 52 that are ohmic electrodes are formed.
- the gate electrode 50, the source electrode 51, and the drain electrode 52 are arranged in parallel to each other.
- the surface of the AlGaN layer 49 including these electrodes is covered with an insulating film 54.
- a field plate electrode 55 is provided on the insulating film 54 between the gate electrode 50 and the drain electrode 52.
- the field plate electrode 55 is also formed of a striped conductor, and is disposed in parallel with the gate electrode 50 and the drain electrode 52. Although not shown, the field plate electrode 55 is used in parallel or partially overlapped with the gate electrode 50 in the width direction, and is connected to the source electrode 51 by a wiring member such as a wire. It is held at the same potential as 51.
- the field plate electrode 55 allows the gate electrode 50 to have a high drain voltage. Electric field concentration in the wedge 56 is alleviated. Thus, it is known that the field plate electrode 55 improves the withstand voltage of the FET and suppresses the current collab phenomenon, for example, as described in Patent Document 1 and Patent Document 2.
- Patent Document 1 Japanese Patent Laid-Open No. 9205211
- Patent Document 2 JP 2002-231733 A
- the field plate electrode 55 is disposed in the vicinity of the gate electrode 50, parasitic capacitance is generated in the gate electrode 50.
- the parasitic capacitance increases, and the amplification characteristics of the FET in the high frequency region deteriorate. In other words, the FET gain decreases due to the parasitic capacitance.
- the prevention of FET current collapsing or the improvement of the withstand voltage by the field plate electrode as the fourth electrode is in a trade-off relationship with the amplification gain of the FET.
- An object of the present invention is to provide a semiconductor device that solves this trade-off relationship, prevents element destruction due to relaxation of electric field concentration, and prevents a decrease in gain.
- an object of the present invention is to easily manufacture a semiconductor device including a fourth electrode through which a high-frequency signal is input / output by reducing the area occupied by the electrode on the element.
- a nitride-based compound semiconductor layer formed on a substrate, a source electrode formed on the semiconductor layer, a source electrode force, A drain electrode formed at a position on the semiconductor layer spaced apart from the semiconductor electrode, a gate electrode formed on the semiconductor layer between the drain electrode and the source electrode, and the semiconductor layer and the gate electrode so as to cover the gate electrode
- the resistor includes the gate electrode.
- the field plate A semiconductor device having a resistance value larger than the high-frequency impedance of the stray capacitance between the electrodes is provided.
- a nitride-based compound semiconductor layer formed on a substrate, a source electrode formed on the semiconductor layer, and the semiconductor layer spaced from the source electrode
- the resistor is a floating member between the gate electrode and the field plate.
- a semiconductor device having a resistance value larger than the high frequency impedance of the capacitor and formed by the sheet resistance of the semiconductor layer is provided.
- a source electrode formed on a nitride-based compound semiconductor layer formed on a substrate, and formed on a position on the semiconductor layer spaced from the source electrode.
- a unit FET having a drain electrode and a gate electrode formed on the semiconductor layer between the drain electrode and the source electrode, and a predetermined region on the semiconductor layer.
- a step of separating, forming a ohmic electrode by depositing Ti / Al on the semiconductor layer, forming a Schottky electrode by depositing Ni / Au on the semiconductor layer, and covering the gate electrode A step of forming an insulating film made of SiN or SiO on the semiconductor layer, a step of forming a trench penetrating the insulating film by etching, and the trench on the source electrode.
- a semiconductor device having a step of forming a metal region Tsu is provided.
- FIG. 1 is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a schematic plane pattern configuration diagram showing an arrangement of electrodes of the semiconductor device according to the first embodiment of the present invention.
- FIG. 3 is a plan pattern configuration diagram showing an example of a resistor made of a metal thin film in the semiconductor device according to the first embodiment of the present invention.
- FIG. 4 is a schematic plan view showing an electrode arrangement of a semiconductor device according to a second embodiment of the present invention. Turn configuration diagram.
- FIG. 5 is a schematic plane pattern configuration diagram of a semiconductor device according to a third embodiment of the present invention.
- FIG. 6 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 7 is a schematic plane pattern configuration diagram showing an arrangement of electrodes of a semiconductor device according to a fifth embodiment of the present invention.
- FIG. 8 is a schematic sectional view taken along the chain line A—B in FIG.
- FIG. 9 is a schematic planar pattern configuration diagram showing an electrode structure of a multi-finger type semiconductor device according to a sixth embodiment of the present invention.
- FIG. 10 is a schematic planar pattern configuration diagram showing an electrode structure of a multi-finger type semiconductor device according to a seventh embodiment of the present invention.
- FIG. 11 is a bird's-eye view including a schematic cross-sectional structure for explaining an electrode configuration of a conventional semiconductor device.
- the semiconductor element is formed on a substrate selected from a SiC substrate, a GaN / SiC substrate, an AlGaN / GaN / SiC substrate, a diamond substrate, and a sapphire substrate.
- the semiconductor element is It is configured as a high electron mobility transistor (HEMT) that utilizes the high electron mobility in the two-dimensional gas (2DEG) induced at the terror junction interface.
- HEMT high electron mobility transistor
- 2DEG two-dimensional gas
- the semiconductor element can be configured as a metal semiconductor (MES) FET using a Schottky gate.
- MES metal semiconductor
- FIG. 1 is a schematic sectional view of a semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a schematic plane pattern configuration diagram showing the arrangement of the electrodes of the semiconductor device according to the first embodiment of the present invention.
- FIG. 3 is a plan pattern configuration diagram showing an example of a resistor made of a metal thin film in the semiconductor device according to the first embodiment of the present invention.
- the semiconductor device includes a substrate as shown in FIG. 1 and FIG.
- the 11 includes a gallium nitride compound semiconductor layer 12 formed on the substrate 11.
- the compound semiconductor layer 12 includes a GaN layer 13 formed on the substrate 11 and an AlGaN layer 14 formed on the GaN layer 13.
- a source electrode 21, a gate electrode 22, and a drain electrode 23 are provided on the surface of the compound semiconductor layer 12, that is, the surface of the AlGaN layer 14.
- the source electrode 21 and the drain electrode 23 are formed of, for example, a striped conductor of A1, and are placed on the A1 GaN layer 14 by ohmic contact.
- the gate electrode 22 is formed of, for example, an Au stripe conductor, and is placed on the AlGaN layer 14 by a Schottky contact.
- An insulating film 24 such as a nitride film is formed on the surface of the AlGaN layer 14 except for the source electrode 21, the gate electrode 22 and the drain electrode 23.
- the field plate electrode 25 is formed of, for example, an Au stripe conductor.
- the field plate electrode 25 is connected to the source electrode 21 through a resistor 26 having a high resistance value. That is, as shown in FIG. 2, one end of the resistor 26 is connected to the lower end of the source electrode 21, and the other end is connected to the wiring member 25a at the lower end of the field plate electrode 25 via the wiring member 25b straddling the gate electrode 22. It is connected to the.
- the resistance value of the resistor 26 depends on the parasitic capacitance between the field plate electrode 25 and the gate electrode 22. It is determined to have a sufficiently high value compared to the impedance for the high-frequency signal used.
- This parasitic capacitance C is caused by the insulating film 2 between the field plate electrode 25 and the gate electrode 22.
- the dielectric constant is ⁇
- the area where the field plate electrode 25 and the gate electrode 22 face each other is S
- the resistance value R of the resistor 26 is
- the resistance value is calculated using a specific example as follows.
- the width of the field plate electrode 25 and the gate electrode 22 is 1 m
- the gate width (stripe conductor length) is 1 mm
- the relative permittivity ⁇ of SiN is 7, and the permittivity ⁇ in vacuum is 8 .
- the capacitance C per gate width lmm is approximately
- the resistance value R against the gate width lmm is
- the value is selected so as to satisfy.
- the unit transistors that is, the gate widths of the pair of gate electrode 22, source electrode 21 and drain electrode 23 are 100 m. It is desirable to insert a resistor 26 having a resistance value of about 500 ( ⁇ , 5 & ⁇ for a sufficiently larger resistance value) between the field plate electrode 25 and the source electrode 21.
- the source electrode 21 is set to the ground potential, that is, O (V)
- the gate electrode 22 is ⁇ 5 (V)
- the drain electrode 23 is +50
- a DC bias voltage of V When a DC bias voltage of V is applied and a high frequency signal is applied between the source electrode 21 and the gate electrode 22, an amplified high frequency signal is output to the drain electrode 23.
- a high voltage of 55 (V) is applied between the gate electrode 22 and the drain electrode 23.
- the field plate electrode 25 is provided, the electric field concentration is alleviated and the insulating film 24 is destroyed. Element collaboration is avoided.
- the field plate electrode 25 is separated from the gate electrode 22 via the insulating film 24, no direct current flows therebetween. However, since the field plate electrode 25 is connected to the source electrode 22 via the resistor 26, its DC potential is maintained at O (V). As a result, the electric field concentration on the gate electrode 22 can be reduced.
- the field plate electrode 25 is connected to the gate electrode 22 through a low impedance formed by a parasitic capacitance between the field plate electrode 25 and the gate electrode 22 for high-frequency signals, and is connected to the resistor 26. Since a high-frequency current flows, the resistance of the field plate electrode 25 can be made substantially open to the gate electrode 22 by increasing the resistance value sufficiently. The ability to praise parasitic capacitance.
- the resistor 26 provided in the compound semiconductor device to which the present invention is applied be formed planarly on the surface of the semiconductor layer 12 via an insulating film.
- a resistor 26 for example, 5 & ⁇
- a linear resistor with a width of 1 ⁇ m and a length of 10000 m. It is formed as a coil pattern. That is, the sheet resistance values of these metals are shown in Table 1. Therefore, in order to obtain a high resistance value, the length of the metal thin film becomes considerably long.
- the gate electrode 22 and the field plate electrode 25 are shown by straight lines in order to simplify the drawing.
- FIG. 4 is a schematic plane pattern configuration diagram showing the electrode arrangement of the semiconductor device according to the second embodiment of the present invention.
- one set of electrode patterns shown in FIG. 3 is repeatedly arranged about 100 sets. That is, in this semiconductor device, the source electrode 21, the gate electrode 22, the drain electrode 23, and the field plate electrode 25 are repeatedly arranged in the horizontal direction.
- the gate electrode 22 and the field plate electrode 25 are shown as straight lines in order to simplify the drawing, but in actuality, they have a pattern arrangement as shown in FIG.
- the plurality of drain electrodes 23 have their upper ends connected to a common drain electrode wiring 23-1.
- the lower ends of the gate electrodes 22 are connected to a common gate electrode wiring 22-2.
- the gate electrode wiring 22-2 is connected to a gate electrode pad 23-3 provided for every predetermined number of continuous gates, for example, every five gate electrodes 22.
- the field plate electrodes 25 are connected to field plate electrode wirings 25 2 provided in common every predetermined number of, for example, 10 field plate electrodes 25 through bridge wirings 25-3. .
- the lower ends of the source electrodes 21 are connected to a common source electrode wiring 21-1 via a bridge wiring 21-2 every predetermined number, for example, every five.
- the source electrode wiring 21-1 is connected to a source electrode pad 21-2 disposed between two adjacent gate electrode pads 22-3.
- a striped resistor 26 is connected between the field plate electrode wiring 25-2 and the source electrode pad 21-2.
- the source electrode wiring 21-1 is separated almost at the center thereof.
- the resistor 26 is connected to the source electrode pad 21-2 through a gap where the source electrode wiring 21-1 is separated.
- FIG. 5 (a) is a schematic plane pattern configuration diagram of a semiconductor device according to the third embodiment of the present invention.
- FIG. 5 (b) shows a schematic plane pattern configuration diagram of a semiconductor device according to a modification of the third embodiment of the present invention.
- a common field plate electrode wiring 25-2 is provided for all field plate electrodes 25.
- a resistor 26 is provided between both ends thereof and the source electrode pad 21-2. The resistance value of these antibody 26 can be about 100 ⁇ .
- the semiconductor device according to the modification of the third embodiment of the present invention has a common field plate electrode wiring for all field plate electrodes 25. 25-2 Force to be provided In order to suppress oscillation due to the length of this wiring, a dividing resistor 28 is inserted for each length of about half the wavelength of the high-frequency signal used.
- the other parts in FIG. 5 are substantially the same as the respective parts in FIG. 4, and thus the corresponding parts are denoted by the same reference numerals and detailed description thereof is omitted.
- FIG. 6 is a schematic sectional view of a semiconductor device according to the fourth embodiment of the present invention.
- the semiconductor device according to the fourth embodiment of the present invention has a field plate 22- provided on the gate electrode 22 in comparison with the first embodiment shown in FIG.
- the insulating film 24 formed on the surface of the compound semiconductor layer 12 is a two-layer (first insulating film 24a and second insulating film 24b).
- Other configurations are almost the same. Therefore, in FIG. 6, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
- the source electrode 21 is set to the ground potential, that is, 0 (V)
- the gate electrode 22 is ⁇ 5 (V)
- the drain electrode 23 is +50 ( V) DC bias voltage is applied, and high frequency is applied between the source electrode 21 and the gate electrode 22.
- a wave signal is applied, an amplified high frequency signal is output to the drain electrode 23.
- a high voltage of 55 (V) is applied between the gate electrode 22 and the drain electrode 23.
- the field plate electrode 25 is provided, the electric field concentration is reduced, and the insulating film 24a and the insulating film 24 Collaborating of elements due to destruction of 24b is avoided.
- the field plate electrode 25 is separated from the gate electrode 22 via the insulating film 24a and the insulating film 24b, no direct current flows therebetween. Since the field plate electrode 25 is connected to the source electrode 22 via the resistor 26, its DC potential is maintained at O (V). As a result, the concentration of the electric field with respect to the gate electrode 22 can be reduced.
- the field plate electrode 25 is a field plate electrode for high-frequency signals.
- the plate electrode 25 can be in a substantially open state with the gate electrode 22, and the ability to learn the parasitic capacitance between the field plate electrode 25 and the gate electrode 22 can be achieved.
- the amplification gain as a transistor element is not lowered and the field plate even if the thickness of the second insulating film 24b is sufficiently small.
- the electric field concentration relaxation function of the electrode 25 can be sufficiently exhibited.
- FIG. 7 is a schematic plane pattern configuration diagram showing the arrangement of the electrodes of the semiconductor device according to the fifth embodiment of the present invention.
- FIG. 8 shows a schematic cross-sectional structure diagram along the chain line AB in FIG.
- a semiconductor device includes a substrate as shown in FIGS.
- the 11 includes a gallium nitride-based compound semiconductor layer 12 formed in 11.
- the compound semiconductor layer 12 includes a GaN layer 13 formed on the substrate 11 and an AlGaN layer 14 formed on the GaN layer 13.
- a source electrode 21, a gate electrode 22, and a drain electrode 23 are provided on the surface of the compound semiconductor layer 12, that is, the surface of the AlGaN layer 14.
- the source electrode 21 and the drain electrode 23 are formed by, for example, a striped conductor of A1. And is placed on the AlGaN layer 14 by ohmic contact.
- the gate electrode 22 is formed of, for example, an Au stripe-shaped conductor, and is placed on the AlGaN layer 14 by a Schottky contact.
- an insulating film 24 such as a nitride film is formed in a portion excluding the source electrode 21, the gate electrode 22 and the drain electrode 23.
- the field plate electrode 25 is formed.
- the field plate electrode 25 is formed of, for example, a striped conductor of A1.
- the field plate electrode 25 is connected to the source electrode 21 through a resistor 26 having a high resistance value.
- the resistor 26 has one end connected to the upper end of the S source electrode 21 and the other end connected to the upper end of the field plate electrode 25 via the wiring member 27 as an insulating layer on the compound semiconductor layer 12. Formed through.
- the substrate 11 and the gallium nitride compound semiconductor layer 12 are the same as those in the semiconductor device shown in FIG.
- a terminal member 28 made of Ti / A and a source electrode 21 are deposited on the surface of the compound semiconductor layer 12, and these form an ohmic contact with the AlGaN layer 14.
- the surfaces of the terminal member 28 and the source electrode 21 are covered with an insulating layer 29 such as SiN or SiO.
- contact holes are formed in the surface portions of the terminal member 27 and the source electrode 21 by a reactive ion etching (RIE) method, etc., through which the wiring member 27 and a bridge wiring 21 described later are interposed. —2 is connected.
- RIE reactive ion etching
- the source electrode 21 is set to the ground potential, that is, 0 V, and a direct current bias voltage of 5 V is applied to the gate electrode 22 and +50 V is applied to the drain electrode 23.
- a high-frequency signal is applied between the source electrode 21 and the gate electrode 22
- an amplified high-frequency signal is output to the drain electrode 23.
- a high voltage of 55 V is applied between the gate electrode 22 and the drain electrode 23. Since the field plate electrode 25 is provided on the gate electrode 22, the electric field concentration is alleviated and the element is destroyed. Avoided.
- the field plate electrode 25 is interposed between the gate electrode 22 and the insulating film 24. DC current does not flow between them. However, since the field plate electrode 25 is connected to the source electrode 22 via the resistor 26, its DC potential is maintained at 0V. Thereby, the electric field concentration on the gate electrode 22 can be relaxed. On the other hand, the field plate electrode 25 is connected to the gate electrode 22 through a low impedance formed by the parasitic capacitance between the field plate electrode 25 and the gate electrode 22 for high-frequency signals. Therefore, the impedance between the source electrode 21 and the gate electrode 22 is governed by the resistance value of the resistor 26.
- the field plate electrode 25 and the gate electrode 22 are The effect of the low impedance formed by the parasitic capacitance between the electrodes 22 can be ignored, and the force can be made substantially open. Therefore, by sufficiently reducing the film thickness of the insulating film 24, the electric field concentration relaxation function of the field plate electrode 25 can be sufficiently exerted without lowering the amplification gain as a transistor element.
- FIG. 9 is a schematic plane pattern configuration diagram showing a part of the electrode structure of the multi-finger type semiconductor device according to the sixth embodiment of the present invention.
- four sets of unit FETs including a source electrode 21, a gate electrode 22, a drain electrode 23, and a field plate electrode 25 are repeatedly arranged in the horizontal direction.
- the drain electrodes 23 are connected at their upper ends to a common drain electrode wiring 23-1.
- Each gate electrode 22 has its lower end connected to a common gate electrode wiring 22-1.
- the gate electrode wiring 22-1 is connected to a plurality of gate electrode pads 22-2 arranged in the lateral direction IJ below the electrode array.
- Each source electrode 21 is connected via a bridge wiring 21-2 to a plurality of source electrode pads 21-1 arranged alternately with gate electrode pads 22-2 in the lateral direction below the electrode arrangement! / RU
- the resistor 26 which is a sheet resistance, is arranged so as to connect between the upper end portion of each source electrode 21 and each wiring member 27.
- the sheet resistance value or the surface resistance value of the resistor 26 depends on the field plate electrode 25 and the gate resistance.
- the parasitic capacitance to the gate electrode 22 is determined to have a sufficiently high value compared to the impedance for the high frequency signal used. Since the sheet resistance value is higher than the metal resistance, the area occupied by the resistor 26 on the semiconductor element is small.
- the sheet resistance value of the semiconductor resistor formed on the semiconductor layer 12 via the insulating layer is, for example, 500 ( ⁇ / sq).
- the semiconductor device since the sheet resistance of the semiconductor resistance is used, the element area of the high power FET is reduced. This makes it easy to create high-power FETs.
- the gate electrode wiring extending from the gate electrode 25 to the gate electrode pad 22-2 By avoiding crossover wiring, the generation of parasitic capacitance is reduced and the operating characteristics of the FET in the high frequency range are not degraded.
- FIG. 10 is a schematic plane pattern configuration diagram showing a part of the electrode structure of the multi-finger type semiconductor device according to the seventh embodiment of the present invention.
- the sheet resistance is the source electrode pad 21-1 and the gate electrode pad 22— Located on the 2 side.
- the resistors 26 are arranged so as to connect the lower end portion of the source electrode 21 and the wiring member 27, respectively. Since the structure of the resistor 26 and other electrode patterns are the same as those of the resistor shown in FIG. 8 and the electrode pattern shown in FIG. 9, detailed description thereof is omitted.
- the element area of the high power FET can be reduced.
- the semiconductor device of the sixth and seventh embodiments of the present invention it is possible to easily create a high-power FET regardless of whether the sheet resistance position is up or down. Will come in. [0063]
- the resistor has a smaller occupied area by using the sheet resistance of the semiconductor, so that the multi-finger FET for high power is reduced. Therefore, it can be applied without enlarging the element area.
- Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, the constituent elements over different embodiments may be appropriately combined.
- the present invention is a force applied to MESFET.
- the semiconductor device of the present invention is not limited to this, and a semiconductor layer made of GaN / AlGaN is formed on a silicon carbide (SiC) substrate.
- SiC silicon carbide
- HEMTs high electron mobility transistors
- semi-insulating GaAs substrates formed with AlGaAs / GaAs HEMTs can do.
- a resistor having a larger resistance value than the high-frequency impedance between the field plate and the gate electrode is inserted into the line connecting the field plate electrode and the source electrode.
- the high-frequency signal is isolated from the potential of the source electrode, and a potential synchronized with the gate electrode is obtained, so that the parasitic capacitance between the field plate electrode and the gate electrode is suppressed, and a decrease in gain is prevented.
- Can do For DC signal In this case, no current flows through the inserted resistor, so that no voltage drop occurs in the resistor, and the potential of the field plate electrode is maintained at the same potential as that of the source electrode. Is done.
- the resistance is formed by using the sheet resistance having a higher resistivity than that of the metal resistor, the area occupied by the electrode on the element can be reduced, and the multi-finger type power amplification device Can adapt to In addition, since the FET and the resistor can be formed almost simultaneously, the process can be simplified.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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EP07832675.8A EP2015353B1 (en) | 2006-12-07 | 2007-11-28 | Semiconductor device |
US12/300,795 US8154079B2 (en) | 2006-12-07 | 2007-11-28 | Semiconductor device and fabrication method of the semiconductor device |
JP2008548242A JP5072862B2 (ja) | 2006-12-07 | 2007-11-28 | 半導体装置及び半導体装置の製造方法 |
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JP2006330337 | 2006-12-07 | ||
JP2006-330337 | 2006-12-07 | ||
JP2006-338609 | 2006-12-15 | ||
JP2006338609 | 2006-12-15 |
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WO2008069074A1 true WO2008069074A1 (ja) | 2008-06-12 |
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PCT/JP2007/072953 WO2008069074A1 (ja) | 2006-12-07 | 2007-11-28 | 半導体装置及び半導体装置の製造方法 |
Country Status (6)
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US (1) | US8154079B2 (ja) |
EP (1) | EP2015353B1 (ja) |
JP (1) | JP5072862B2 (ja) |
KR (1) | KR101033388B1 (ja) |
TW (1) | TW200840045A (ja) |
WO (1) | WO2008069074A1 (ja) |
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US20100025737A1 (en) * | 2008-07-29 | 2010-02-04 | Nec Electronics Corporation | Field-effect transistor |
JP2010199241A (ja) * | 2009-02-24 | 2010-09-09 | Fujitsu Ltd | 半導体装置 |
WO2010120825A2 (en) * | 2009-04-14 | 2010-10-21 | Triquint Semiconductor, Inc. | Field-plated transistor including feedback resistor |
US20110215378A1 (en) * | 2010-03-02 | 2011-09-08 | Samsung Electronics Co., Ltd. | High electron mobility transistors exhibiting dual depletion and methods of manufacturing the same |
WO2013027722A1 (ja) * | 2011-08-22 | 2013-02-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2013051287A (ja) * | 2011-08-30 | 2013-03-14 | Toyota Central R&D Labs Inc | 高電子移動度トランジスタとその製造方法 |
US8754496B2 (en) | 2009-04-14 | 2014-06-17 | Triquint Semiconductor, Inc. | Field effect transistor having a plurality of field plates |
JP2014127715A (ja) * | 2012-12-27 | 2014-07-07 | Toshiba Corp | 半導体装置 |
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WO2020070831A1 (ja) * | 2018-10-03 | 2020-04-09 | 三菱電機株式会社 | 電界効果トランジスタ |
JP2022051356A (ja) * | 2020-09-18 | 2022-03-31 | サンケン電気株式会社 | 半導体装置 |
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- 2007-11-28 US US12/300,795 patent/US8154079B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
EP2015353A1 (en) | 2009-01-14 |
TW200840045A (en) | 2008-10-01 |
EP2015353B1 (en) | 2015-11-18 |
EP2015353A4 (en) | 2010-03-31 |
US8154079B2 (en) | 2012-04-10 |
JP5072862B2 (ja) | 2012-11-14 |
KR101033388B1 (ko) | 2011-05-09 |
US20090256210A1 (en) | 2009-10-15 |
TWI363424B (ja) | 2012-05-01 |
JPWO2008069074A1 (ja) | 2010-03-18 |
KR20090013191A (ko) | 2009-02-04 |
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