WO2006059556A1 - 電子部品及びその製造方法 - Google Patents
電子部品及びその製造方法 Download PDFInfo
- Publication number
- WO2006059556A1 WO2006059556A1 PCT/JP2005/021762 JP2005021762W WO2006059556A1 WO 2006059556 A1 WO2006059556 A1 WO 2006059556A1 JP 2005021762 W JP2005021762 W JP 2005021762W WO 2006059556 A1 WO2006059556 A1 WO 2006059556A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ceramic
- electronic component
- covering member
- wiring board
- unfired
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 47
- 239000000919 ceramic Substances 0.000 claims abstract description 207
- 238000000034 method Methods 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims description 47
- 239000004020 conductor Substances 0.000 claims description 39
- 238000010304 firing Methods 0.000 claims description 27
- 230000001629 suppression Effects 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 22
- 239000010949 copper Substances 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 238000010030 laminating Methods 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 238000005245 sintering Methods 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 11
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 99
- 239000010408 film Substances 0.000 description 31
- 239000000843 powder Substances 0.000 description 15
- 239000002131 composite material Substances 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 13
- 229910010293 ceramic material Inorganic materials 0.000 description 11
- 238000007789 sealing Methods 0.000 description 11
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 8
- 238000007747 plating Methods 0.000 description 8
- 230000009467 reduction Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 239000007769 metal material Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000011049 filling Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000009966 trimming Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000004519 grease Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229910001252 Pd alloy Inorganic materials 0.000 description 2
- 229910001260 Pt alloy Inorganic materials 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000005672 electromagnetic field Effects 0.000 description 2
- 239000000395 magnesium oxide Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000011812 mixed powder Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- -1 zircoia Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 230000037237 body shape Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910052839 forsterite Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- HCWCAKKEBCNQJP-UHFFFAOYSA-N magnesium orthosilicate Chemical compound [Mg+2].[Mg+2].[O-][Si]([O-])([O-])[O-] HCWCAKKEBCNQJP-UHFFFAOYSA-N 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B18/00—Layered products essentially comprising ceramics, e.g. refractory products
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
- C04B35/622—Forming processes; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
- C04B35/626—Preparing or treating the powders individually or as batches ; preparing or treating macroscopic reinforcing agents for ceramic products, e.g. fibres; mechanical aspects section B
- C04B35/63—Preparing or treating the powders individually or as batches ; preparing or treating macroscopic reinforcing agents for ceramic products, e.g. fibres; mechanical aspects section B using additives specially adapted for forming the products, e.g.. binder binders
-
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- C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
- C04B35/622—Forming processes; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
- C04B35/626—Preparing or treating the powders individually or as batches ; preparing or treating macroscopic reinforcing agents for ceramic products, e.g. fibres; mechanical aspects section B
- C04B35/63—Preparing or treating the powders individually or as batches ; preparing or treating macroscopic reinforcing agents for ceramic products, e.g. fibres; mechanical aspects section B using additives specially adapted for forming the products, e.g.. binder binders
- C04B35/632—Organic additives
- C04B35/634—Polymers
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B37/00—Joining burned ceramic articles with other burned ceramic articles or other articles by heating
- C04B37/02—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles
- C04B37/023—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used
- C04B37/026—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used consisting of metals or metal salts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/4807—Ceramic parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
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- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
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- C04B2235/00—Aspects relating to ceramic starting mixtures or sintered ceramic products
- C04B2235/65—Aspects relating to heat treatments of ceramic bodies such as green ceramics or pre-sintered ceramics, e.g. burning, sintering or melting processes
- C04B2235/656—Aspects relating to heat treatments of ceramic bodies such as green ceramics or pre-sintered ceramics, e.g. burning, sintering or melting processes characterised by specific heating conditions during heat treatment
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/02—Aspects relating to interlayers, e.g. used to join ceramic articles with other articles by heating
- C04B2237/12—Metallic interlayers
- C04B2237/125—Metallic interlayers based on noble metals, e.g. silver
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- C—CHEMISTRY; METALLURGY
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
- C04B2237/32—Ceramic
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
- C04B2237/32—Ceramic
- C04B2237/34—Oxidic
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
- C04B2237/32—Ceramic
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- C04B2237/341—Silica or silicates
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
- C04B2237/32—Ceramic
- C04B2237/34—Oxidic
- C04B2237/343—Alumina or aluminates
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
- C04B2237/32—Ceramic
- C04B2237/34—Oxidic
- C04B2237/345—Refractory metal oxides
- C04B2237/348—Zirconia, hafnia, zirconates or hafnates
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
- C04B2237/40—Metallic
- C04B2237/403—Refractory metals
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
- C04B2237/40—Metallic
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
- C04B2237/40—Metallic
- C04B2237/405—Iron metal group, e.g. Co or Ni
- C04B2237/406—Iron, e.g. steel
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
- C04B2237/40—Metallic
- C04B2237/408—Noble metals, e.g. palladium, platina or silver
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- C04B2237/50—Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Definitions
- the present invention relates to an electronic component in which a surface-mounted component mounted on a wiring board is covered with a covering member and a manufacturing method thereof, and more particularly, to improve the structure of the covering member to promote downsizing and low profile.
- the present invention relates to an electronic component that can be used and a manufacturing method thereof.
- Patent Document 1 proposes an insulated IC in which a metal shield case is attached to a ceramic substrate.
- This hybrid IC has a ceramic substrate having a wiring pattern and electronic components such as a microcomputer, a transistor, and an IC surface-mounted on one or both sides of the ceramic substrate.
- the ceramic substrate has a plurality of connection terminals extending vertically downward from the outer peripheral edge.
- a metallic shield case formed by bending both ends of a rectangular plate is mounted on the upper surface of the ceramic substrate, and this shield case shields external noise.
- This shield case also serves as an adsorption surface when the hybrid is picked up on the mother board.
- Patent Document 2 proposes a ceramic package for a semiconductor chip having a ceramic covering member having a box shape.
- This ceramic package for a semiconductor chip comprises a ceramic package base on which a semiconductor chip is mounted, and a ceramic covering member attached to the package base! RU
- a copper plating layer is provided on the inner surface of the covering member, a sealing solder layer is provided on the sealing surface via the copper plating layer, and the copper plating layer on the sealing surface is electrically connected to the copper plating layer on the inner surface. It is connected. Then, when the ground electrode is provided on the sealing surface of the package base and the package base is sealed via the sealing solder layer of the covering member, the copper plating layer on the sealing surface of the covering member is connected to the ground electrode of the package base.
- Patent Document 3 proposes a sealing member for sealing a semiconductor device and a method for manufacturing the same.
- This sealing covering member is formed as a multilayer structure composed of a plurality of ceramic layers, and a shield layer is formed on the inner layer by solid printing of paste.
- the back surface and the substrate body opposite to the back surface are bonded by a bonding paste, thereby sealing the cavity of the substrate body.
- Chip parts can be mounted on both the front and back sides of the ceramic coated member.
- Patent Document 1 JP-A-6-350280
- Patent Document 2 JP-A-8-250615
- Patent Document 3 Japanese Patent Laid-Open No. 11-354663
- the upper surface of the shield case 2 may stagnate, which may cause the shield case 2 and the component parts 5 such as chip parts to come into contact with each other, causing a short circuit.
- the characteristic value of the element part 5 changes, and as a result, it is difficult to accurately measure the characteristic value of the electronic part 1.
- a good product may be removed as a defective product, or a defective product may be shipped to the market as a good product.
- the resin film since the resin film is formed, the manufacturing cost increases or the resin film There is a risk that the reliability of the electronic component may be reduced by peeling.
- the ceramic covering member is formed in a box shape. Therefore, if the ceramic thickness of the covering member is reduced to reduce the height of the electronic component, for example, as shown in FIGS. 18 (a) and 18 (b), the ceiling of the box-shaped covering member 2 during firing is shown. Due to the difference in shrinkage behavior in the surface direction between the part 2A and the outer peripheral wall part 2B, the ceiling part 2A is swelled. Due to this undulation, the substantial thickness of the ceiling portion 2A as the covering member 2 is not reduced, and thus the reduction of the height of the electronic component cannot be promoted.
- FIG. 18A is a partial cross-sectional view when a plurality of covering members are manufactured together
- FIG. 18B is a cross-sectional view when cutting into individual covering members.
- Patent Document 3 the technique described in Patent Document 3 is for sealing the cavity portion of an electronic component with a flat cover member, and can be applied to an electronic component having no cavity. Can not. That is, in this case, in order to use the covering member, it is necessary to form a cavity on the wiring board side, which complicates the manufacturing process and increases the cost. Furthermore, when a chip component is mounted on the covering member, it is necessary to perform soldering and reflow twice, when the chip component is mounted on the covering member and when the covering member is mounted on the wiring board.
- the chip component mounted on the covering member falls or breaks due to remelting of the solder, and in some cases, alloying or brittleness due to recrystallization of the solder occurs. As a result, the reliability of the solder connection portion is significantly reduced.
- the present invention has been made to solve the above-described problems, and is a covering member that can be manufactured thinly and with high accuracy and can be mounted on a wiring board with high accuracy and can promote a reduction in height. It is an object of the present invention to provide an electronic component equipped with the above and a method for manufacturing the same. Means for solving the problem
- An electronic component according to claim 1 of the present invention includes: a wiring board having a wiring pattern; a surface mounting component mounted on the main surface of the wiring board; and a covering member covering the surface mounting component.
- the covering member has a ceiling portion formed by a flat plate-like ceramic member and a leg portion formed by a columnar member having at least the same height as the surface mount component. It is what.
- the electronic component according to claim 2 of the present invention is the electronic component according to claim 1,
- the columnar member is a columnar metal, and the columnar metal is integrally formed with the plate-like ceramic member by simultaneous firing.
- the electronic component according to claim 3 of the present invention is the electronic component according to claim 2, wherein the ceiling portion has a multilayer structure in which a plurality of ceramic layers are laminated, and A shield electrode layer is disposed on the inner layer portion and the Z or outer surface portion, and the shield electrode layer is connected to the columnar metal via via conductors provided in the ceramic layer. To do.
- the shield electrode layer and the columnar metal are integrally formed by simultaneous firing. It is a sign.
- an electronic component according to claim 5 of the present invention is the portion according to claim 3 or claim 4, wherein at least one of the shield electrode layers faces the surface-mounted component. Is characterized in that an opening is formed.
- the ceiling portion is formed by laminating a plurality of ceramic layers. It has a multilayer structure, and a thick film resistor is disposed on the inner layer portion and Z or surface portion thereof, and the thick film resistor is formed in the columnar shape via via conductors provided in the ceramic layer. It is characterized by being connected to a metal.
- a shield electrode layer is disposed on the inner layer portion and Z or an outer surface portion of the ceiling portion. An opening is formed in a portion facing the thick film resistor.
- an electronic component according to claim 8 of the present invention is the electronic component according to any one of claims 1 to 7, wherein the ceiling portion includes a ceramic sintered body as a base body and a terminal.
- a chip-shaped ceramic electronic component having an electrode is provided, and at least a part of the chip-shaped ceramic electronic component is embedded in the ceiling portion.
- an electronic component according to claim 9 of the present invention is any one of claims 1 to 8.
- the wiring substrate is formed as a ceramic multilayer substrate formed by laminating a plurality of first low-temperature sintered ceramic layers, and has an inner layer having a wiring pattern mainly composed of silver or copper. It is a feature.
- the ceiling portion has a laminated structure in which a plurality of second low-temperature sintered ceramic layers are laminated.
- the second low temperature sintered ceramic layer and the first low temperature sintered ceramic layer have substantially the same material composition.
- the method for manufacturing an electronic component according to claim 11 of the present invention includes a step of manufacturing a wiring board having a wiring pattern, a flat ceiling portion, and the ceiling portion.
- the ceiling portion has a multilayer structure formed by laminating a plurality of ceramic layers.
- a shield electrode layer is disposed on the inner layer portion and the Z or surface portion, and the columnar member is a columnar metal integrally formed by simultaneous sintering with the shield electrode layer. It is.
- the step of producing the covering member includes a low-temperature sintered ceramic as a main component. And a ceramic unfired body for a ceiling portion having an unfired shield electrode layer on the inner layer portion and Z or surface portion, and a non-sintered flame that does not substantially sinter at the firing temperature of the low-temperature sintered ceramic.
- the ceramic unfired body for a ceiling portion is formed on an inner layer portion and a Z or surface portion thereof. It has an unfired thick film resistor.
- the method for manufacturing an electronic component according to claim 15 of the present invention is the method according to claim 13 or claim 14, wherein at least one of the unfired shield electrode layers is the surface-mounted component.
- the portion opposite to is characterized by having an opening.
- the electronic component manufacturing method according to claim 16 of the present invention is the invention according to any one of claims 13 to 15, wherein the ceramic unfired body for a ceiling part is:
- the main surface has a chip-like ceramic electronic component having a ceramic sintered body as a base and terminal electrodes.
- the columnar member is formed in a tapered cross-section. It is a life characterized by being.
- the method for manufacturing an electronic component according to claim 18 of the present invention is the invention according to any one of claims 11 to 17, wherein the columnar member of the covering member is a bonding material. And connecting to the wiring pattern provided on the surface of the wiring board.
- the method for manufacturing an electronic component according to claim 19 of the present invention is the method according to any one of claims 11 to 18, wherein the wiring board and the coating are provided. It is characterized by having a step of connecting the members in a collective substrate state and dividing them into individual electronic components.
- the electronic component manufacturing method according to claim 20 of the present invention is the invention according to claim 19, wherein the columnar member is also divided when dividing the assembly substrate state. An electronic component having a side electrode as a divided surface of the columnar member is obtained.
- the thin film can be manufactured with high accuracy. It is possible to provide an electronic component including a covering member that can increase the mounting accuracy with respect to the wiring board and can promote a reduction in height and a method for manufacturing the same.
- FIG. L are diagrams showing one embodiment of the electronic component of the present invention, (a) is a sectional view showing the whole electronic component, and (b) is a covering member of the electronic component. It is a perspective view shown.
- FIG. 2] (a) to (c) are process diagrams showing the main part of the manufacturing process of the wiring board of the electronic component shown in FIG.
- FIG. 3] (a) to (c) are process diagrams showing the main part of the manufacturing process of the covering member of the electronic component shown in FIG.
- FIG. 4] (a) to (c) are process diagrams showing an assembly process of the electronic component shown in FIG.
- FIG. 5 is a perspective view showing a collective substrate of the covering member shown in FIG. 1 (b).
- FIG. 6 is a cross-sectional view showing an assembly of electronic components assembled using the assembly substrate shown in FIG.
- FIG. 7 is a perspective view of a collective substrate of covering members used in another embodiment of the electronic component of the present invention.
- FIG. 8 is a cross-sectional view showing an assembly of electronic components assembled using the assembly substrate shown in FIG.
- FIG. 9 (a) and (b) are cross-sectional views showing the relationship between the covering member of the electronic component and the surface mounting component, respectively, and (a) is the covering member and the surface mounting component used for the electronic component shown in FIG.
- FIG. 5B is a diagram showing a relationship between a metal covering member used for a conventional electronic component and a surface mount component.
- FIG. 10 is a cross-sectional view showing still another embodiment of the electronic component of the present invention.
- FIGS. 11 (a) and 11 (b) are cross-sectional views showing a comparison between the leg portion of the covering member of the electronic component shown in FIG. 1 and the leg portion of the covering member of the electronic component of still another embodiment of the present invention. is there.
- 12 (a) and 12 (b) are cross-sectional views showing the main part of the manufacturing process of the covering member of still another embodiment of the electronic component of the present invention.
- FIGS. 13 (a) and 13 (b) are cross-sectional views showing still another embodiment of the electronic component of the present invention, each showing an assembly process of the electronic component.
- FIGS. 14] (a) to (d) are cross-sectional views showing the main parts of still another embodiment of the electronic component of the present invention.
- FIG. 15] (a) to (c) are cross-sectional views showing the main part of still another embodiment of the electronic component of the present invention.
- FIGS. 16 (a) and 16 (b) are cross-sectional views showing an electronic component to which the covering member shown in FIG. 15 (a) is applied.
- FIG. 17 (a) and (b) are cross-sectional views showing conventional electronic components, respectively.
- FIG. 18 (a) and (b) are cross-sectional views showing the main part of the manufacturing process of a covering member for another conventional electronic component.
- the electronic component 10 of the present embodiment includes a wiring board 11 having a predetermined wiring pattern and a plurality of surface mounting components mounted on the main surface (upper surface) of the wiring board. 12 and a covering member 13 that covers these surface-mounted components 12, and is configured to be mounted on a mounting board such as a mother board (not shown).
- the wiring substrate 11 is formed as a ceramic multilayer substrate in which a plurality of ceramic layers 11A are laminated, for example.
- the wiring pattern 14 includes an in-plane conductor 14A formed in a predetermined pattern at the interface between the upper and lower ceramic layers 11A and 11A and the ceramic layer 11A so as to electrically connect the upper and lower in-plane conductors 14A and 14A.
- the via conductor 14B is formed by penetrating and arranged in a predetermined pattern, and the surface electrodes (terminal electrodes) 14C and 14C are formed on the upper and lower surfaces of the wiring board 11 with predetermined patterns, respectively.
- chip-shaped active electronic components 12A such as silicon semiconductor elements and gallium arsenide semiconductor elements, and chip-shaped capacitors, inductors, resistors, and the like.
- Passive electronic parts 12B etc. are mounted.
- These surface-mounted components 12A and 12B are, for example, as shown in the figure, via a solder or conductive grease, or via a bonding wire such as Au, Al, Cu, etc. They are electrically connected to the wiring pattern 14 and are electrically connected to each other.
- the covering member 13 includes a ceiling portion 13A formed of a plate-shaped ceramic member and a vertically lower portion from the peripheral portion of the lower surface of the ceiling portion 13A. And a plurality of leg portions 13B formed by extending columnar members.
- the ceiling portion 13A has a laminated structure in which a plurality of ceramic layers are laminated.
- the leg portion 13B is formed higher than the height of the upper surface force of the wiring substrate 11 of the surface mount component 12 by, for example, a columnar metal, and the force is integrated with the ceiling portion 13A by sintering.
- a shield electrode layer 13C is formed in the surface direction, and a via conductor 13D that connects the peripheral portion of the shield electrode layer 13C and the leg portion 13B is formed.
- Leg 13B, shield electrode layer 13C, and via conductor 13D are preferably formed of the same conductive metal material.
- the shield electrode layer 13C in the ceiling part 13A is connected to the wiring board 11 of the wiring board 11 via the via conductor 13D and the leg part 13B. Connected to turn 14 to protect surface mount component 12 from the external electromagnetic environment.
- the shield electrode layer 13C is preferably grounded to the ground electrode provided on the wiring board 11 via the leg portion 13B made of columnar metal, but is not necessarily grounded!
- the ceramic layer 11A and the ceramic layer of the ceiling portion 13A of the covering member 13 are both formed of a ceramic material, and both of them are preferably formed of the same ceramic material.
- a ceramic material for example, a low temperature co-fired ceramic (LTCC) material can be used.
- the low-temperature sintered ceramic material is a ceramic material that can be sintered at a temperature of 1050 ° C or lower and can be fired simultaneously with silver, copper, or the like having a low specific resistance.
- low-temperature sintered ceramics are glass composite LTCC materials made by mixing borosilicate glass with ceramic powders such as alumina, zircoia, magnesia, and forsterite, ZnO-MgO-Al O-SiO-based.
- Examples include LTCC materials.
- the 13 shield electrode layers 13C, the via conductors 13D and the leg portions 13B of the covering member, and the wiring pattern 14 of the wiring board 11 are each formed of a conductive metal material as described above.
- a conductive metal material use a metal whose main component is at least one selected from Ag, Ag—Pt alloy, Ag—Pd alloy, Cu, Ni, Pt, Pd, W, Mo and Au. Can do.
- Ag, Ag—Pt alloy, Ag—Pd alloy and Cu are particularly preferable as wiring materials because of their low specific resistance.
- the conductive metal material has a low resistance of 1050 ° C or lower with a low resistance such as Ag or Cu. Metals with melting points are used, and these metal materials can be co-fired at low temperatures below 1050 ° C with low-temperature sintered ceramic materials.
- the ceramic material and the conductive metal material for the wiring pattern used for the wiring substrate 11 and the covering member 13 are substantially the same. If the materials of the wiring board 11 and the covering member 13 are different, There is a possibility that the covering member 13 may be peeled off from the wiring board 11 due to the difference in thermal expansion coefficient of these materials.
- the wiring board 11 and the covering member 13 are produced using a non-shrinkage method.
- the non-shrink method is a method in which the dimension in the plane direction of the ceramic substrate does not substantially change before and after firing the ceramic substrate.
- a shrinkage suppression sheet described later is used.
- the method of manufacturing an electronic component according to the present embodiment includes a step of manufacturing a wiring board 11 having a wiring pattern 14, a ceiling portion 13A formed of a flat ceramic member, and the ceiling portion.
- a low-temperature sintered ceramic powder for example, an alumina powder and a mixed powder having borosilicate glass power are prepared.
- This mixed powder is dispersed in an organic vehicle to prepare a slurry, and this is formed into a sheet by a casting method, whereby a ceramic green sheet 111A for a substrate shown in FIG. Make a certain number of sheets by thickness.
- the ceramic green sheet 111A has a thickness of 10 m after firing through a laminating process, a pressure-bonding process, and a firing process, which will be described later.
- a via hole is formed in a predetermined pattern on the ceramic green sheet 111A using a laser beam or a mold, for example, and then the via hole is filled with a conductive paste to form an unfired via conductor 114B.
- a conductive paste for example, a paste containing Ag as a main component is used.
- the same conductive paste is printed in a predetermined pattern on the ceramic green sheet for substrate 111A by, for example, a screen printing method to form the unfired in-plane conductor 114A.
- the ceramic green sheet 111A in which the unfired in-plane conductor 114A, the unfired via conductor 114B, and the unfired surface electrode 114C are formed in a predetermined pattern is manufactured. For example, a total of 5 ceramic green sheets 111 are formed. Prepare A.
- the ceramic green sheet for shrinkage suppression includes a hardly sinterable ceramic powder as a main component that does not sinter at the firing temperature of the low-temperature sintered ceramic material.
- a hardly sinterable ceramic powder is prepared as a hardly sinterable ceramic powder, and the alumina powder is dispersed in an organic vehicle to prepare a slurry, which is formed into a sheet by a casting method.
- a predetermined number of the ceramic green sheets 100, 100A for shrinkage suppression shown in the drawing are produced.
- the sintering temperature of these ceramic green sheets 100, 100A for shrinkage suppression is 1500-1600 ° C, which is much lower than the sintering temperature (1050 ° C or less) of ceramic green sheet 111A for low-temperature sintered ceramic powder. Since it has a high sintering temperature, it is substantially not sintered at the firing temperature of the ceramic ceramic sheet 111 A for substrates.
- These shrinkage-suppressing ceramic green sheets 100 and 100A are produced, for example, three by three as shown in FIG. 2 (a).
- the ceramic green sheets 100 and 100A for suppressing shrinkage are substantially the same.
- the hardly sinterable ceramic powder for example, ceramic powder such as zirconium, magnesia, etc. can be used in addition to alumina.
- These shrinkage-suppressing ceramic green sheets 100 and 100A preferably contain the same ceramic components as those contained in the substrate ceramic green sheet 111A.
- three ceramic green sheets 100A for shrinkage suppression are laminated, and the ceramic green sheet 111A for substrates having the unfired via conductor 114B and the unfired surface electrode 114C is laminated thereon.
- Three ceramic green sheets 111 A for a substrate having a non-fired in-plane conductor 114A and a non-fired via conductor 114B are laminated on the fired surface electrode 114C, and the unfired via conductor 114B is further laminated thereon.
- the ceramic green sheet 111A for substrate having the unfired surface electrode 114C is laminated with the unfired surface electrode 114C facing upward.
- each layer was pressed and pressure-bonded with a pressure of 0.2 to 1.5 MPa from the stacking direction (vertical direction).
- a composite laminate 110 shown in FIG. 2 (b) can be formed.
- the composite laminate 110 is fired at a predetermined temperature of, for example, 1050 ° C or lower (for example, 870 ° C).
- the ceramic green sheets 100 and 100A for suppressing shrinkage do not substantially sinter and do not substantially shrink in the surface direction. Therefore, the five ceramic green sheets 111A for substrate are sintered and integrated. Even with this, the ceramic green sheets 100 and 100A for suppressing shrinkage can be shrunk only in the laminating direction (thickness direction) without substantially shrinking in the surface direction, resulting in a highly accurate wiring pattern 14.
- the wiring board 11 shown in FIG. 2 (c) can be produced. Since the wiring substrate 11 contracts substantially only in the thickness direction, it can contribute to the reduction in the height of the electronic component 10.
- the shrinkage-suppressing ceramic green sheets 100 and 100A are burned off by the organic vehicle and become an aggregate of alumina powder.
- the aggregate of alumina powder can be easily removed by blasting or the like, and the wiring substrate 11 can be easily obtained by removing the alumina powder.
- a ceramic green sheet 111A for a substrate of 20 m has a thickness of 100 ⁇ m in 5 layers, but by firing, the wiring substrate 11 having a thickness of 50 ⁇ m can be obtained by shrinking in the height direction.
- the surface electrode 14C is subjected to a plating process such as gold plating to improve the wettability with a joining member such as solder.
- Ceramic green sheet for ceiling The covering member 12 is produced using the same material as the wiring board 11 in the same manner.
- a predetermined number for example, two
- ceramic green sheets 113A for the ceiling portion are produced. These ceramic green sheets 113A for the ceiling are formed to a thickness of 20 m.
- An unfired shield electrode layer 113C having a large area is formed on the upper surface of one ceramic green sheet 113A for the ceiling by solid printing of a conductive paste.
- a plurality of via holes arranged in a predetermined pattern are formed in the other ceramic green sheet 113A for ceilings, and a plurality of unfired via conductors 113D are formed by filling the via holes with a conductive paste.
- a plurality of unfired via conductors 113D are positioned at the periphery of the unfired shield electrode layer 113C.
- a predetermined number for example, 6
- the via holes are filled with conductive paste to form unfired legs 113B.
- the unfired leg 113B needs to have a height that is equal to or longer than the mounting height of the surface mounting component 12 after firing, and the height is adjusted according to the number of ceramic green sheets 200 for suppressing shrinkage. .
- the cross-sectional shape in the horizontal direction after firing of the unfired legs 113B may be either a circular shape or a polygonal shape, and the circular diameter (in the case of a polygonal shape, the maximum dimension passing through the center) is 0.1 to If it is about lmm.
- three ceramic green sheets 200 for suppressing shrinkage are produced as shown in FIGS. 3 (a) and 3 (b).
- three ceramic green sheets for restraining shrinkage 200A that do not include the unfired legs 113B are produced as shown in FIG.
- the columnar member via hole can be used as a leg by filling a ceramic paste (mainly low-temperature sintered ceramic). Even in this case, the columnar member made of the ceramic paste is integrated with the wiring substrate by simultaneous firing.
- FIG. 3 (a) Thereafter, as shown in FIG. 3 (a), three ceramic green sheets 200A for shrinkage suppression without unfired legs are laminated, and a ceiling section cell having an unfired shield electrode layer 113C is laminated thereon.
- Laminated green sheet 113A is laminated with unfired shield electrode layer 113C facing upward, and ceramic green sheet for ceiling portion 113A having unfired via conductor 113D is laminated thereon.
- three ceramic green sheets 200 for suppressing shrinkage having unfired legs 113B are laminated thereon. At this time, alignment of the unsintered leg 113B of the ceramic green sheet for shrinkage suppression 200 and the unsintered via conductor 113D of the ceramic green sheet for ceiling 113A is performed.
- a ceramic green sheet 200 for suppressing shrinkage is pressure-bonded at a predetermined pressure (for example, 0.2 to 1.5 MPa) to produce a composite laminate 130 shown in FIG.
- a predetermined pressure for example, 0.2 to 1.5 MPa
- a predetermined temperature for example, 870 ° C.
- the shield electrode layer 13C is formed as an inner layer of the ceiling portion 13A. Alternatively, it may be formed on the outer surface of the ceiling portion 13A. However, it is better not to form the shield electrode layer 13C so as to be the inner surface of the ceiling portion 13A (the inner surface of the covering member 13). If the shield electrode layer 13C is formed on the inner surface of the covering member 13, the ceiling 13A swells inward due to the pressing force of the jig when selecting characteristics, etc., and the surface mount component 12 mounted on the wiring board 11 There is a possibility that the characteristic selection with high accuracy cannot be performed due to contact. In other words, if the shield electrode layer 13C is formed on the inner layer or the outer surface of the covering member 13, the characteristic selection can be performed with high accuracy.
- the surface mount component 12 When mounting the surface mount component 12 on the wiring board 11, as shown in FIG. 4 (a), the surface mount component 12 is placed with the surface facing upward, for example, using a metal mask, After the bonding material P such as solder paste is applied to the surface electrode 14C for the surface mount component and the via conductor 14B to which the leg of the covering member 13 is connected, as shown in FIG.
- the surface mount component 12 is mounted on the wiring board 11 using a not-shown).
- the covering member 13 is mounted on the wiring board 11 using a mounter as shown in FIG. Subsequently, by subjecting the wiring board 11 to heat treatment such as reflow, the solder is melted and the surface mounting component 12 and the covering member 13 are mounted on the wiring board 11 as shown in FIG. To do.
- the metal mask is used at the time of mounting, the mounting surface is flat, so that the metal mask can be adhered to the mounting surface with high accuracy.
- the second assembly substrate 53 On the second assembly substrate 53, virtual dividing lines L that are divided into individual covering members 13 are formed, and legs 13B of the individual covering members 13 are arranged in a rectangular frame shape along both sides of the virtual dividing lines L. Then, after mounting the surface mount component 12 on each wiring board 11 of the first collective board 51 using the mounter, the second collective board 53 is mounted and heat-treated to integrate them.
- the electronic component assembly 50 shown in FIG. 6 can be produced. Thereafter, when the electronic component assembly 50 is diced according to the virtual dividing line L of the electronic component assembly 50, individual electronic components 10 can be obtained.
- first and second aggregate substrates may be formed as shown in FIG. That is, in the second collective substrate 53A shown in FIG. 7, the portions to be the leg portions 13B of the covering member 13 are arranged in a rectangular shape on the virtual dividing line L of the second collective substrate 53A. Further, the via conductors 14B of the wiring board 11 corresponding to the respective legs 13B are formed according to the virtual dividing line L of the first collective board 51A as shown in FIG. Then, after mounting the surface-mounted components on the individual wiring boards of the first aggregate board 51A using the mounter, the second aggregate board 53A is mounted and integrated, and the electronic component assembly 50A shown in FIG. Is made.
- the portion that becomes the leg portion 13B and the portion that becomes the via conductor 14B are divided into two parts by the virtual division line L, and individually The electronic component 10 can be obtained.
- the leg portions 13B of the covering member 13 and some in-plane conductors 14A and via conductors 14B of the wiring board 11 are aligned with the end face of the electronic component 10, and therefore the side surface when the electronic component 10 is mounted. It can also be used as an electrode.
- the covering member 13 covering the surface mounting component 12 on the wiring board 11 includes the ceiling portion 13A formed of a flat ceramic member and at least surface mounting. And a leg portion 13B formed by a columnar member having the height of the part, and the ceiling portion 13A is formed by a flat plate-like ceramic member, so that there are portions with different thicknesses as in the prior art. During firing, it shrinks uniformly in the thickness direction and sinters, so that it can be formed as a flat ceiling portion 13A without the occurrence of waviness and the like, and the height reduction of the electronic component 10 can be promoted. In addition, since the ceiling portion 13A of the covering member 13 is a ceramic member, even if the ceiling portion 13A stagnates when the characteristics of the electronic component 10 are selected, there is no short circuit between the surface mounting component 12. ,.
- the ceiling portion 13A is a ceramic member and the surface mount component 12 is hardly affected by the stagnation, the gap between the ceiling portion 13A and the surface mount component 12 can be narrowed, and the height can be reduced. It can be further promoted.
- a clearance of 50 ⁇ m corresponding to the thickness of the ceiling portion 13A may be provided between the surface mounting component 12 and the surface mounting component 12.
- the dimension from the upper surface of the surface-mounted component 12 to the outer surface of the ceiling portion 13A is 10 O / zm.
- the conventional metal covering member 2 has a limit of 100 m for the thickness of the covering member in consideration of the mechanical strength as shown in (b) of the figure, and the gap corresponding to the thickness of the covering member is 100 ⁇ m.
- the top surface force of the surface mount component is 200 m from the outer surface of the covering member. Therefore, the covering member 13 in the present embodiment can surely realize a reduction in the height of the electronic component 10.
- the ceiling portion 13A has a multilayer structure in which a plurality of ceramic layers are laminated, and the shield electrode layer 13C is disposed as an inner layer thereof, and also has a strong force. Since the shield electrode layer 13C is connected to the leg portion 13B made of columnar metal via the via conductor 13D provided in the ceramic layer, it becomes the ground potential of the wiring board 11!
- the covering member 13 connected to 14 can shield and protect the surface mounting component 12 on the wiring board 11 from the external electromagnetic field environmental force by the shield electrode layer 13C.
- the columnar metals of the shield electrode layer 13C and the leg portion 13B are integrated together by simultaneous firing, so that the solder for connection to the covering member 13 is mounted when the covering member 13 is mounted.
- the covering member 13 can be mounted on the wiring board 11 by the mounter in the same manner as the surface-mounted component 12 in which it is not necessary to separately form bumps, and the manufacturing process can be simplified.
- the wiring board 11 having the high-precision wiring pattern 14 without distortion is produced by producing the wiring board 11 by a non-shrinking method using the ceramic green sheets 100 and 100A for shrinkage suppression.
- 11 can be manufactured, and the force is also reduced by the shrinkage method in the non-shrinking method, so that the wiring board 11 can be formed thinner by shrinking greatly in the stacking direction (thickness direction).
- the covering member 13 by the non-shrinkage method using the shrinkable ceramic green sheets 200 and 200A, the ceiling 13A can be thinned without causing undulation as described above. It can be fired at the same time as the ceiling part 13A and integrated. Also, since the ceiling 13A of the covering member 13 is flat, use the mounter V and cover member 13 to the wiring board. 11 can be mounted with high accuracy.
- the electronic component of the present embodiment will be described by attaching the same reference numerals to the same or corresponding parts as in the first embodiment.
- the electronic component 10 that covers all of the plurality of surface-mounted components 12 with the shield electrode layer 13C of the covering member 13 has been described.
- the characteristics of the surface mount component 12 change depending on the distance from the shield electrode layer 13C, which is the ground potential of the covering member 13, such as a certain SAW filter package. There is.
- the ceiling portion 13A of the covering member 13 is pinched by the action of a jig or the like when the characteristics of the electronic component 10 are selected, the distance between the shield electrode layer 13C of the covering member 13 and the surface mounting component 12 changes, and the surface mounting component 12 The characteristics of can be affected.
- the electronic component 10A of the present embodiment does not affect the characteristics of the specific surface mounted component 12C shown by circles in FIG. 10 and the characteristics of the surface mounted component 12C.
- the configuration is the same as that of the above embodiment except that the coating member 13 is provided.
- an opening 13E is formed in a portion located directly above the specific surface mount component 12C as shown in the figure, and corresponds to the opening 13E of the ceiling portion 13A.
- the part is formed only of a ceramic material.
- the covering member 13 can be manufactured in the same manner as in the above embodiment, except that the unfired shield electrode layer having an opening on the ceiling ceramic green sheet is solid-printed.
- the top surface of the specific surface mount component 12C of the ceiling portion 13A of the covering member 13 is formed of the ceramic member, it is covered when the characteristics of the electronic component 10A are selected. Even if the ceiling 13A of the member 13 is stagnant, the specific characteristics of the specific surface mount component 12C that the specific surface mount component 12C is not electromagnetically affected by the shield electrode layer 13C can be measured. The quality of the electronic component 10A can be sorted with high accuracy. Therefore, non-defective products are not discarded and defective products are not shipped to the market. In addition, in this embodiment, the same effect as the above embodiment can be expected.
- the electronic component of the present embodiment has a shape of the leg portion 13B of the covering member 13.
- the configuration is the same as in the first embodiment except that the shapes are different. Therefore, the present embodiment will be described with the same reference numerals assigned to the same or corresponding parts as in the first embodiment.
- the force is such that the leg portion 13B of the covering member 13 has a straight body shape as shown in Fig. 11 (b).
- the leg portion 13B in this embodiment is shown in Fig. 11 (a).
- the cross section in the axial direction has a tapered shape, that is, an inverted truncated cone shape or an inverted quadrangular pyramid shape.
- the leg portion 13B can be formed by covering a via hole with a laser beam so that the cross-sectional shape of the shrinkage suppression sheet is tapered and filling the via hole with a conductive paste.
- each of the legs 13B having a straight cylindrical shape in the axial direction has a straight cylindrical shape formed by punching with a die or the like, and a conductive paste is applied to the via hole. It can be formed by filling.
- connection area of the leg portion 13B including the solder fillet F with the wiring board 11, that is, the diameter d ′ is as shown in FIG. Smaller than the diameter d in the case of the straight body shown in b). That is, the covering member 13 can be connected to the wiring substrate 11 with the same connection area on the upper end surface and the lower end surface (connection surface of the wiring substrate 11 to which the covering member 13 is connected) of the leg portion 13B.
- the leg portion 13B may have a plurality of tapered sections in the vertical direction.
- the covering member 13 does not have a shield electrode layer and does not require conduction between the covering member 13 and the wiring board 11.
- the configuration is the same as in the first embodiment. Therefore, also in this embodiment, the same reference numerals are given to the same or corresponding parts as in the first embodiment, and this embodiment will be described.
- the covering member 13 in the present embodiment can be manufactured as shown in FIG. That is, as shown in the figure, as the ceramic green sheet 113A for the ceiling portion, for example, two ceramic green sheets having a thickness of 20 ⁇ m are laminated, and there is no unfired leg portion having a thickness of, for example, 250 ⁇ m on the lower surface thereof.
- the ceramic layer 200A for shrinkage suppression is disposed, and the ceramic layer 200 for shrinkage suppression having an unfired leg 113B having a thickness of, for example, 250 m is disposed on the upper surface thereof.
- the ceiling 13A is 20 m thick.
- a ceramic paste mainly composed of a low-temperature sintered ceramic can be used.
- the covering member 13 can be mixed with non-conductive legs and conductive legs. In this case, a shield electrode layer is formed on the ceiling 13A.
- the covering member 13 that contributes to a reduction in height can be obtained as in the first embodiment.
- the electronic component of this embodiment includes a surface-mounted component 12 mounted on a wiring board 11 via a bonding wire 12D and sealed with a resin R.
- the configuration is the same as in the first embodiment. Therefore, also in this embodiment, the same reference numerals are given to the same or corresponding parts as in the first embodiment, and this embodiment will be described.
- the surface-mounted component 12 in this embodiment is mounted in a state of being grease-sealed on the wiring board 11, a via is formed using a metal mask when the covering member 13 is mounted on the wiring board 11. Solder paste cannot be applied directly to conductor 14B.
- a method of applying a bonding material to the front end surface of the leg portion 13B of the covering member 13 is used.
- a bonding material a solder paste or a conductive resin that is good if it is liquid or semi-liquid is preferably used. That is, for example, as shown in FIG. 13 (b), the leg portion 13B of the covering member 13 is brought into contact with the liquid bonding material P in the container A, and the bonding material P is directly transferred to the distal end surface of the leg portion 13B. Then, as shown in FIG.
- the covering member 13 is stacked on the wiring board 11 and subjected to heat treatment. By doing so, the covering member 13 can be mounted on the wiring board 11.
- the bonding material P is applied to the lower end of the leg portion 13B of the covering member 13.
- the covering member 13 can be easily mounted and fixed on the wiring board 11 by transferring You can.
- the same effects as those of the first embodiment can be expected.
- a thick film resistor 13F and its wiring pattern 13G are provided in the ceiling 13A of the covering member 13 in place of the shield electrode layer 13C.
- the configuration is the same as in the first embodiment except for the above. Therefore, the covering member 13 in the present embodiment can be manufactured in substantially the same manner as in the first embodiment. Therefore, also in this embodiment, the same reference numerals are given to the same or corresponding parts as in the first embodiment, and this embodiment will be described.
- a covering member 13 shown in FIG. 14 (a) has a thick film resistor 13F and its wiring pattern 13G in place of the shield electrode layer 13C.
- a predetermined number of ceramic green sheets (not shown) for the ceiling are prepared, via holes are formed in a predetermined pattern on the ceramic green sheets for the ceiling, and conductive materials are formed in the via holes.
- An unfired via conductor is formed on the ceramic green sheet by filling the conductive paste.
- a conductive paste is printed in a predetermined pattern to form an unfired in-plane conductor, and then a resistive paste is printed to form an unfired thick film resistor.
- the resistance paste for example, a conventionally known resistance material such as a resistance material mainly composed of ruthenium oxide can be used.
- the ceramic green for the ceiling portion in the same manner as in the first embodiment.
- the covering member 13 can be manufactured by laminating the sheet and the shrinkage suppression sheet to produce a composite laminate, and firing the composite laminate. As shown in FIG. 14A, the covering member 13 includes a thick film resistor 13F and a wiring pattern 13G. After firing, a desired resistance value can be obtained by irradiating the thick film resistor 13F of the covering member 13 with laser light for trimming.
- the resistor chip that is usually required to be mounted on the wiring board 11 is built in the covering member 13 as the thick film resistor 13F. Since it is not necessary to mount a resistor chip on the wiring board 11, the mounting area can be saved, and electronic components can be miniaturized and functions can be densified.
- the covering member 13 that contributes to a reduction in height can be obtained as in the fourth embodiment.
- FIG. 14 (a) the force described when the thick film resistor 13F and its wiring pattern 13G are provided in the ceiling 13A of the covering member 13 is shown in FIGS. 14 (b) to (d).
- the thick film resistor 13F and the wiring pattern 13G may be provided on the shield electrode layer 13C of the covering member 13.
- the thick film resistor 13F and its ceramic pattern sheet for forming the wiring pattern 13G are increased by one sheet.
- the covering member can be manufactured in the same manner as in the first embodiment. Therefore, the description of the manufacturing method of the covering member shown in FIGS. 14 (b) to (d) is omitted.
- a shield electrode layer 13C, a thick film resistor 13F and its wiring pattern 13G are formed in the ceiling portion 13A of the covering member 13 shown in FIG. 14B, and the thick film resistor 13F and its wiring pattern are formed. 13G is formed so as to be disposed above shield electrode layer 13C.
- the trimming of the thick film resistor 13F can be performed by applying a laser beam to the thick film resistor 13F also with the upward force of the ceiling portion 13A.
- the shield electrode layer 13C is formed on the upper surface of the ceiling portion 13A, and the thick film resistor 13F and its wiring pattern are formed inside the ceiling portion 13A. 13G is formed. Trimming opening 13E is formed in shield electrode layer 13C so as to be positioned directly above thick film resistor 13F. Thick film resistor 13F is trimmed well by irradiating the upper force laser beam on ceiling 13A. Can be done.
- the shield electrode layer 13C, the thick film resistor 13F, and the wiring pattern 13G thereof are formed in the ceiling portion 13A, and the thick film resistor 13F and the thick film resistor 13F are formed.
- the wiring pattern 13G is disposed below the shield electrode layer 13C.
- a trimming opening 13E is formed in the shield electrode layer 13C so as to be positioned immediately above the thick film resistor 13F, and the thick film resistor 13F is trimmed by irradiating laser light from above the ceiling 13A. It can be done well.
- the electronic component can be reduced in size and increased in functionality, and the same operational effects as in the first embodiment can be achieved. Can be expected. [0080] Seventh Embodiment
- the electronic component of the present embodiment is provided with a chip-like ceramic electronic component 13H in place of the thick film resistor 13F of the sixth embodiment.
- FIG. 14 is configured in accordance with the embodiment shown in (a), (c), and (d).
- the chip-like ceramic electronic component 13H is made of a ceramic sintered body and has external terminal electrodes at both ends thereof. Examples of the chip-like ceramic electronic component 13H include passive electronic components such as a multilayer ceramic capacitor and a multilayer inductor. Therefore, the covering member 13 in the present embodiment can be manufactured in substantially the same manner as in the first embodiment. Therefore, also in this embodiment, the same reference numerals are given to the same or corresponding parts as in the first embodiment, and this embodiment will be described.
- a covering member 13 shown in FIG. 15 (a) has a chip-like ceramic electronic component 13H instead of the thick film resistor 13F shown in FIG. 14 (a).
- the chip-shaped ceramic electronic component 13H is connected to the internal wiring pattern 13G from the lower surface side of the ceiling portion 13A of the covering member 13.
- a predetermined unfired wiring pattern (unfired in-plane conductors and unfired via conductors) is formed on the ceramic green sheet for the ceiling, as in the sixth embodiment.
- a predetermined number of ceiling ceramic green sheets are laminated on a shrinkage-suppressing ceramic green sheet, and a laminated body in which unfired land portions are exposed in a predetermined pattern is formed on the upper surface of the laminated body.
- an organic adhesive is applied to the upper surface of the laminate using a spray or the like to form an organic adhesive layer, and then a chip-like ceramic electronic is formed on the unfired land using a mounter (not shown).
- a shrinkage-suppressing ceramic green sheet having unfired legs is laminated and pressed to produce a composite laminate. By this crimping, the chip-like ceramic electronic component 13H is slightly buried in the upper surface force of the laminate together with the unfired land portion.
- the external terminal electrodes of the chip-like ceramic electronic component 13H are sintered integrally with the land portion 131, and the covering member 13 in which the chip-like ceramic electronic component 13H is partially embedded is formed.
- the embedding amount of the chip-like ceramic electronic component 13H in the ceiling portion 13A is preferably 1 ⁇ m or more, particularly 1 to 200 ⁇ m. According to the present embodiment, since the chip-like ceramic electronic component 13H mounted on the covering member 13 is embedded in the lower surface force of the ceiling portion 13A, the covering member 13 is mounted on the wiring board 11 and fixed. Even if heat treatment such as reflow is performed, the connection reliability between the chip-like ceramic electronic component 13 H and the land can be ensured for a long time without deterioration. The same effect as the form can be expected.
- a shield electrode layer 13C is formed on the upper surface of the ceiling portion 13A, and a wiring pattern 13G is formed inside the ceiling portion 13A.
- a chip-shaped ceramic electronic component 13H is connected to the screen 13G in the same manner as shown in FIG.
- the shield electrode layer 13C and the wiring pattern 13G for the chip-like ceramic electronic component 13H are formed in the ceiling portion 13A, and the wiring pattern 13G becomes the shield electrode.
- a chip-shaped ceramic electronic component 13H is connected to the wiring pattern 13G in the same manner as shown in FIG.
- connection reliability of the chip-like ceramic electronic component 13H can be ensured for a long time, and the external electromagnetic field environment cable can be secured. In addition to ensuring protection, it is possible to achieve the same effects as the first embodiment.
- the present invention can be suitably used as an electronic component used in various electronic devices.
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- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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EP05809664A EP1818979B1 (en) | 2004-12-02 | 2005-11-28 | Electronic component and fabrication method thereof |
JP2006547890A JP4677991B2 (ja) | 2004-12-02 | 2005-11-28 | 電子部品及びその製造方法 |
US11/755,108 US7557307B2 (en) | 2004-12-02 | 2007-05-30 | Electronic component and its manufacturing method |
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JP2004350485 | 2004-12-02 | ||
JP2004-350485 | 2004-12-02 |
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US11/755,108 Continuation US7557307B2 (en) | 2004-12-02 | 2007-05-30 | Electronic component and its manufacturing method |
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WO2006059556A1 true WO2006059556A1 (ja) | 2006-06-08 |
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US (1) | US7557307B2 (ja) |
EP (1) | EP1818979B1 (ja) |
JP (1) | JP4677991B2 (ja) |
CN (1) | CN100485910C (ja) |
WO (1) | WO2006059556A1 (ja) |
Cited By (12)
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---|---|---|---|---|
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Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8959762B2 (en) | 2005-08-08 | 2015-02-24 | Rf Micro Devices, Inc. | Method of manufacturing an electronic module |
KR101046134B1 (ko) * | 2007-12-27 | 2011-07-01 | 삼성전기주식회사 | 세라믹 기판 및 그 제조방법과 이를 이용한 전기장치 |
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US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
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US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
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JP5682548B2 (ja) * | 2011-12-14 | 2015-03-11 | 株式会社村田製作所 | 積層型インダクタ素子およびその製造方法 |
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US8987872B2 (en) * | 2013-03-11 | 2015-03-24 | Qualcomm Incorporated | Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages |
US9461025B2 (en) | 2013-03-12 | 2016-10-04 | Taiwan Semiconductor Manfacturing Company, Ltd. | Electric magnetic shielding structure in packages |
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US9807890B2 (en) * | 2013-05-31 | 2017-10-31 | Qorvo Us, Inc. | Electronic modules having grounded electromagnetic shields |
JP6294020B2 (ja) * | 2013-07-16 | 2018-03-14 | セイコーインスツル株式会社 | 蓋体部、この蓋体部を用いた電子デバイス用パッケージ及び電子デバイス |
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US9252127B1 (en) | 2014-07-10 | 2016-02-02 | Invensas Corporation | Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture |
JP5869631B2 (ja) * | 2014-07-24 | 2016-02-24 | 浜松ホトニクス株式会社 | 電子部品の製造方法 |
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US11127689B2 (en) | 2018-06-01 | 2021-09-21 | Qorvo Us, Inc. | Segmented shielding using wirebonds |
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US11114363B2 (en) | 2018-12-20 | 2021-09-07 | Qorvo Us, Inc. | Electronic package arrangements and related methods |
US10779395B1 (en) | 2019-04-25 | 2020-09-15 | Microsoft Technology Licensing, Llc | Electromagnetic interference shield with integrated decoupling |
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TWI752820B (zh) * | 2021-02-08 | 2022-01-11 | 欣興電子股份有限公司 | 電路板結構及其製作方法 |
US11594497B2 (en) * | 2021-03-31 | 2023-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electromagnetic shielding structure for a semiconductor device and a method for manufacturing the same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0334445A (ja) * | 1989-06-30 | 1991-02-14 | Hitachi Ltd | 半導体集積回路装置およびその封止構造 |
JPH08153822A (ja) * | 1994-11-29 | 1996-06-11 | Kyocera Corp | 半導体装置 |
JPH11354663A (ja) * | 1998-06-10 | 1999-12-24 | Nec Corp | 半導体装置の封止用キャップ及びその製造方法 |
JP2000236045A (ja) * | 1999-02-16 | 2000-08-29 | Mitsubishi Electric Corp | 高周波パッケージ |
JP2003163304A (ja) | 2001-11-29 | 2003-06-06 | Mitsubishi Electric Corp | 高周波パッケージ |
JP2004031745A (ja) * | 2002-06-27 | 2004-01-29 | Kyocera Corp | 電子部品装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0186269U (ja) | 1987-11-30 | 1989-06-07 | ||
JPH06350280A (ja) | 1993-06-11 | 1994-12-22 | Matsushita Electric Ind Co Ltd | ハイブリッドic |
JPH07142630A (ja) * | 1993-11-16 | 1995-06-02 | Matsushita Electric Ind Co Ltd | 半導体実装用セラミック基板の製造方法 |
JP2646989B2 (ja) | 1993-12-27 | 1997-08-27 | 日本電気株式会社 | チップキャリア |
JP3188086B2 (ja) | 1993-12-29 | 2001-07-16 | 松下電器産業株式会社 | セラミック配線基板とその製造方法及びその実装構造 |
JPH08250615A (ja) | 1995-03-13 | 1996-09-27 | Sumitomo Kinzoku Electro Device:Kk | 半導体チップ用セラミックパッケージ |
US6552264B2 (en) * | 1998-03-11 | 2003-04-22 | International Business Machines Corporation | High performance chip packaging and method |
JP2000058691A (ja) * | 1998-08-07 | 2000-02-25 | Sharp Corp | ミリ波半導体装置 |
US6297551B1 (en) * | 1999-09-22 | 2001-10-02 | Agere Systems Guardian Corp. | Integrated circuit packages with improved EMI characteristics |
US6462271B2 (en) * | 2000-12-27 | 2002-10-08 | International Business Machines Corporation | Capping structure for electronics package undergoing compressive socket actuation |
JP3890947B2 (ja) * | 2001-10-17 | 2007-03-07 | 松下電器産業株式会社 | 高周波半導体装置 |
US6660562B2 (en) * | 2001-12-03 | 2003-12-09 | Azimuth Industrial Co., Inc. | Method and apparatus for a lead-frame air-cavity package |
JP2004135001A (ja) * | 2002-10-09 | 2004-04-30 | Toyo Commun Equip Co Ltd | 圧電振動子 |
JP2004193404A (ja) * | 2002-12-12 | 2004-07-08 | Alps Electric Co Ltd | 回路モジュール、及びその製造方法 |
US6971162B2 (en) * | 2003-05-13 | 2005-12-06 | Motorola, Inc. | Localized enhancement of multilayer substrate thickness for high Q RF components |
-
2005
- 2005-11-28 JP JP2006547890A patent/JP4677991B2/ja active Active
- 2005-11-28 CN CNB2005800407411A patent/CN100485910C/zh active Active
- 2005-11-28 WO PCT/JP2005/021762 patent/WO2006059556A1/ja active Application Filing
- 2005-11-28 EP EP05809664A patent/EP1818979B1/en active Active
-
2007
- 2007-05-30 US US11/755,108 patent/US7557307B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0334445A (ja) * | 1989-06-30 | 1991-02-14 | Hitachi Ltd | 半導体集積回路装置およびその封止構造 |
JPH08153822A (ja) * | 1994-11-29 | 1996-06-11 | Kyocera Corp | 半導体装置 |
JPH11354663A (ja) * | 1998-06-10 | 1999-12-24 | Nec Corp | 半導体装置の封止用キャップ及びその製造方法 |
JP2000236045A (ja) * | 1999-02-16 | 2000-08-29 | Mitsubishi Electric Corp | 高周波パッケージ |
JP2003163304A (ja) | 2001-11-29 | 2003-06-06 | Mitsubishi Electric Corp | 高周波パッケージ |
JP2004031745A (ja) * | 2002-06-27 | 2004-01-29 | Kyocera Corp | 電子部品装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1818979A4 * |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4957723B2 (ja) * | 2006-06-02 | 2012-06-20 | 株式会社村田製作所 | 多層セラミック基板およびその製造方法ならびに電子部品 |
JP2008244289A (ja) * | 2007-03-28 | 2008-10-09 | Mitsubishi Electric Corp | 電磁シールド構造 |
JP2012009611A (ja) * | 2010-06-24 | 2012-01-12 | Murata Mfg Co Ltd | 回路モジュール |
WO2012105394A1 (ja) * | 2011-02-01 | 2012-08-09 | 株式会社村田製作所 | 電子部品モジュール、及び該電子部品モジュールを備える多機能カード |
JP2012190960A (ja) * | 2011-03-10 | 2012-10-04 | Nec Corp | 半導体装置の製造方法及び半導体装置 |
JP2012227213A (ja) * | 2011-04-15 | 2012-11-15 | Nec Access Technica Ltd | 電磁波シールド構造 |
WO2013099194A1 (ja) * | 2011-12-28 | 2013-07-04 | パナソニック株式会社 | 半導体装置およびその製造方法 |
JP2016511939A (ja) * | 2013-02-08 | 2016-04-21 | クアルコム,インコーポレイテッド | 磁気抵抗ランダムアクセスメモリ(mram)のためのスモールフォームファクタ磁気シールド |
US10674596B2 (en) | 2018-01-25 | 2020-06-02 | Nec Corporation | Electronic component, electronic component manufacturing method, and mechanical component |
JP7371348B2 (ja) | 2019-05-20 | 2023-10-31 | 三菱電機株式会社 | 回路基板用バリア構造 |
WO2021085378A1 (ja) * | 2019-10-29 | 2021-05-06 | 京セラ株式会社 | 蓋体、電子部品収納用パッケージ及び電子装置 |
JPWO2021085378A1 (ja) * | 2019-10-29 | 2021-05-06 | ||
JP7260662B2 (ja) | 2019-10-29 | 2023-04-18 | 京セラ株式会社 | 蓋体、電子部品収納用パッケージ及び電子装置 |
US11744019B2 (en) | 2020-11-18 | 2023-08-29 | Murata Manufacturing Co., Ltd. | Component mounted on circuit board |
Also Published As
Publication number | Publication date |
---|---|
EP1818979A1 (en) | 2007-08-15 |
EP1818979A4 (en) | 2011-01-26 |
US7557307B2 (en) | 2009-07-07 |
CN100485910C (zh) | 2009-05-06 |
JPWO2006059556A1 (ja) | 2008-06-05 |
CN101065842A (zh) | 2007-10-31 |
JP4677991B2 (ja) | 2011-04-27 |
US20070221399A1 (en) | 2007-09-27 |
EP1818979B1 (en) | 2012-07-04 |
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