WO2005025230A1 - Dispositif de traitement d'images - Google Patents

Dispositif de traitement d'images Download PDF

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Publication number
WO2005025230A1
WO2005025230A1 PCT/JP2003/010977 JP0310977W WO2005025230A1 WO 2005025230 A1 WO2005025230 A1 WO 2005025230A1 JP 0310977 W JP0310977 W JP 0310977W WO 2005025230 A1 WO2005025230 A1 WO 2005025230A1
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WO
WIPO (PCT)
Prior art keywords
simd
image processing
processors
type computer
computers
Prior art date
Application number
PCT/JP2003/010977
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English (en)
Japanese (ja)
Inventor
Hiroshi Takayanagi
Nobuhiro Seki
Osamu Mouri
Akihiro Makino
Masahiro Miura
Original Assignee
Hitachi Ulsi Systems Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ulsi Systems Co., Ltd. filed Critical Hitachi Ulsi Systems Co., Ltd.
Priority to PCT/JP2003/010977 priority Critical patent/WO2005025230A1/fr
Priority to JP2005508742A priority patent/JP4516020B2/ja
Publication of WO2005025230A1 publication Critical patent/WO2005025230A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation

Definitions

  • the present invention relates to an image processing apparatus, and more particularly to a technique that is effective when applied to MPEG image compression / decompression.
  • Huffman coding is performed by dividing a digital image into blocks and detecting motion vector for each block, discrete cosine transform (DCT), quantization, and ACZDC prediction. And compress the image data.
  • DCT discrete cosine transform
  • ACZDC prediction ACZDC prediction
  • motion vector detection is based on the difference between the current frame and the macroblock of the 16x16 pixel macroblock (shift block) in the image frame from the macroblock range of the previous or next image frame. Detects the position of the smallest 16 x 16 pixel. Then, by using the position vector and the difference (frame difference) to perform DCT, quantization, AC / DC prediction, and Huffman coding, high moving image compression becomes possible.
  • the expansion processing of the compressed data is realized by a procedure reverse to the above-described compression, that is, by generating a compensation image from Huffman decoding, AC / DC prediction, inverse quantization, inverse DCT, and motion vector information. .
  • SIMD Single Instruction Multi-Datastream
  • An example of the realization of the S IMD type parallel computing architecture is a general-purpose computer.
  • the architecture of this computer consists of multiple processors and one control system, and the control system operates by broadcasting common instructions and data to all processors.
  • Each processor has a local memory and an arithmetic unit (multiplier, ALU, shifter, etc.).
  • the control system has rewritable program memory and global memory.
  • a broadcast data bus for transmitting data from the control system to all processors and a common bus for transmitting data to the control system via a tri-state buffer by any one of the processors specified by the address signal are used between the control system and the processors. Is transmitted and received.
  • the data transmitted by the control system to all processors via the broadcast data path can be either data on the memory in the control system or data received by the control system from any one processor via a common bus. Can be selected.
  • Instructions from the control system can be executed by specifying only one processor specified by the address signal.
  • the control system can initialize the local memory of each processor, and it is possible to transmit 1-to-N (N is an arbitrary natural number) data between the control system and the processor.
  • each of multiple processors controlled by a single instruction broadcast from a control system is a unit that mimics a neuron (neural cell). Then, the operation of the neural network is imitated by calculating the weight value data in the local memory of each processor with respect to the input data broadcast to all the processors via the control system.
  • the control system program it is possible to perform general-purpose parallel computation of the Euro algorithm, other neuro-algorithms, and other non-neuro-algorithms, as typified by pack propagation (error reverse propagation). Become.
  • a plurality of processors can be used as a calculation unit of a shift block. That is, the shift block (a plurality of 16 x 16 pixels) in the motion vector detection range on the image one frame before is initialized in the local memory of the processor (the plurality).
  • the motion vector detection image (a macroblock of 16 x 16 pixels) of the current frame is broadcast from the control system to all processors.
  • Each processor calculates the frame difference between the broadcast data and the data in the local memory.
  • the control system can detect the image position of the shift block set to the minimum processor as the motion vector position by comparing the frame differences of all processors. Disclosure of the invention
  • motion detection and DCT processing are realized by only one SIMD type parallel computer, it is necessary to move the difference block information result of the processor that detected the motion to another processor for DCT processing. Occurs, and the overall processing performance decreases.
  • motion detection requires a difference absolute value calculator in the processor, and DCT requires a multiplier. Therefore, if motion detection and DCT are processed by a single SIMD parallel computer, both the absolute difference calculator and the multiplier must be built into the processor, increasing the overall gate size.
  • an object of the present invention is to provide an image processing apparatus which has a small circuit configuration and can be operated at high speed in image processing such as MPEG image compression / expansion.
  • At least a plurality of processors including a difference calculator and a local memory operate with a single instruction from the first control unit, and all the processors from the first control unit to all the processors.
  • the first S IMD type computer is connected to an S IMD type computer, and the first S IMD type computer performs motion detection processing in image processing, and one or more second S IMD type computers are used for DCT, inverse DCT, and quantum in image processing. Or quantization processing.
  • the operation result of the first SIMD type computer is transmitted in parallel to the processor in the second SIMD type computer via a buffer, and the processor performs the processing in parallel for each image block unit. Perform processing.
  • header information (block) indicating the attribute of the block.
  • each processor of the second S IMD type computer can determine each header information and efficiently perform the processing suitable for the block. It can be configured to be able to be performed.
  • Performance can be improved because motion detection and DCT / quantization can be performed by pipeline operation for each process.
  • An SIMD computer with a relatively small number of processors enables real-time image processing, such as MPEG compression and decompression, as represented by MPEG.
  • Semiconductor integrated circuits (electronic components) that can be mounted on low-power-consumption portable home appliances can realize image processing functions with a higher pixel density than before.
  • FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.
  • FIG. 2 is a block diagram showing an internal configuration of the SIMD type computer 100 included in the image processing apparatus according to one embodiment of the present invention.
  • FIG. 3 is an explanatory diagram showing a motion detection processing procedure in the SIMD computer 100 in the image processing apparatus according to the embodiment of the present invention.
  • FIG. 4 is an explanatory diagram showing a DCT / quantization processing procedure in the SIMD type computer 200 in the image processing apparatus according to the embodiment of the present invention.
  • FIG. 5 is an explanatory diagram showing an inverse DCT / inverse quantization procedure in the SIMD type computer 300 in the image processing apparatus according to the embodiment of the present invention.
  • FIG. 6 is a block diagram showing a configuration of a viewer V to which the image processing device according to one embodiment of the present invention is applied.
  • FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.
  • the image processing apparatus according to the present embodiment is, for example, an image compression system, and includes a SIMD-type computer 100, a SIMD-type computer 200, a SIMD-type computer 300, and buffers 401 to 400. , 501 to 506, 601 to 606, and the like.
  • the SIMD type computer 100 is composed of a processor array 130 composed of a plurality of processors 101 to 116 including an arithmetic unit (for example, a difference arithmetic unit) and a local memory, a control unit 140, and the like. It is configured.
  • the SIMD type computer 200 is composed of a processor array 230 consisting of a plurality of processors 201 to 206 including an arithmetic unit (for example, a multiplier) and a local memory, and a control unit 240. It is configured.
  • a processor array 230 consisting of a plurality of processors 201 to 206 including an arithmetic unit (for example, a multiplier) and a local memory, and a control unit 240. It is configured.
  • the SIMD type computer 300 includes a processor array 330 composed of a plurality of processors 301 to 360 including an arithmetic unit (for example, a multiplier) and a local memory, and a control unit 340. It is composed of
  • the SI MD computer 100 and the SI MD computer 200 are electrically connected to each other via a plurality of buffers 40:! To 406, and the control unit in the SI MD computer 100
  • the output of the host 140 is input in parallel to the plurality of buffers 401 to 406, and the output of the buffer 40 :! to 406 is output to the plurality of processors 200 in the SIMD type computer 200.
  • ⁇ 206 are input in parallel.
  • the SI MD type computer 200 and the SI MD type computer 300 are electrically connected to each other via a plurality of buffers 501 to 506, and a plurality of The outputs of the processors 201 to 206 are input in parallel to a plurality of buffers 50 :!
  • the outputs of the buffers 501 to 506 are output to a plurality of buffers in the SIMD type computer 300.
  • the signals are input to the processors 301 to 303 in parallel.
  • SI MD type Calculator 3 0 0 Multiple processors 3 0 1 to 3 6 Outputs multiple buffers 6 Enter 01 to 606.
  • the output of the buffers 501 to 506 is AC /
  • the outputs are transmitted to the DC prediction and the Huffman processing, and the outputs 601 to 606 are transmitted to the compensation image generation processing.
  • each processor 101 to 116 in the processor array 130 and the control unit 140 are electrically connected by an instruction bus 150, a broadcast data bus 160, a processor data output common bus 170, and the like. ing.
  • the processors 201 to 206 and the control unit 240 are electrically connected by an instruction bus 250 or the like.
  • the processors 301 to 306 and the control unit 340 are electrically connected to each other by an instruction bus 350 or the like.
  • the SIMD computers 100 to 300 have three stages, but may have two or four or more stages.
  • the number of processors 101 to 116 in the SIMD type computer 100 is 16, but any number is acceptable.
  • the processors 201 to 206 and 301 to 306 and the buffers 401 to 406, 501 to 506, and 601 to 606 in the 310-type computers 200 and 300 are respectively six in parallel, but how many are in parallel? You may.
  • FIG. 2 shows a detailed configuration of the SIMD type computer 100.
  • the SMDD computer 100 includes a plurality of memory units 121 to 129 in addition to the control unit 140 and the processor array 130.
  • Local memory and memory cut 12 in processors 101-116! 129 are composed of RAM (memory).
  • the processors 101 to 116 are arranged in a matrix, and the local memory in each processor 1 to 1 to 116 is connected to other processors in the upper, lower, left, and right directions, and can shift arithmetic data forward, backward, left, and right It is as follows.
  • the local memories of the processors 104, 108, 1 12, 1 13, 1 14, 1 15, and 1 16 located at the end of the processor array 130 include a memory unit 121 arranged around the processor array 130. To 129, and the arithmetic units can shift the operation data with the memory units 121 to 129.
  • the control unit 140 and the arithmetic units in all the processors 101 to 116 are connected to the instruction bus 150 and the A command and data are output from the control unit 140 to all the processors 101 to 116 via a broadcast data path 160.
  • the outputs of the arithmetic units in all the processors 101 to 116 are connected to the control unit 140 via a tri-state buffer and a processor data output common bus 170, and the arithmetic data of the arithmetic units in each of the processors 101 to 116 are output. Is output to the control unit 140.
  • Each of the memory units 121 to 129 is connected to another adjacent memory cut, so that data can be shifted between the memory units. Further, each of the memory units 121 to 129 and the control unit 140 are connected via a memory common bus 180.
  • control unit 140 is connected to an external control (main CPU) and an external memory (image data).
  • the SIMD computer 100 performs a motion detection process in image processing. Then, the SMDD computer 10.0 outputs the difference information and the motion vector information for each block, which are the result of the motion detection processing, to the buffers 401 to 406 in units of blocks. After outputting the difference information and the motion vector information to the buffers 401 to 406, the SIMD computer 100 performs a motion detection process for the next macroblock.
  • the processors 201 to 206 perform the DCT operation in the image processing in parallel.
  • the processors 201 to 206 take in the difference information for each block in the buffers 401 to 406 and perform a DCT operation.
  • the SIMD type computer 200 performs the quantization process in parallel by the processors 201-206.
  • the processors 201 to 2 ⁇ 6 output the processing results to the buffers 501 to 506 in parallel with the motion vector information.
  • the motion vector information of each block in the buffers 501 to 506 and the data after quantization processing are subjected to AC / DC processing and Huffman processing, and output as compressed data.
  • the motion vector information of each block in the buffers 501 to 506 and the data after the quantization processing are output to the SIMD type computer 300 for generating a compensation image.
  • the processors 301 to 306 perform inverse quantization on each block in parallel.
  • the processors 301 to 306 perform the inverse DCT operation in parallel.
  • the processors 301 to 306 output the processing results to the buffers 601 to 606 in parallel with the motion vector information.
  • the motion vector information of each block in the buffers 601 to 606 and the data after the inverse DCT calculation are used for the compensation image generation processing.
  • each processing motion detection, DCT operation, quantization, inverse quantization, inverse DCT operation
  • DCT calculation and quantization processing are performed by the S IMD computer 200, and inverse quantization processing and inverse DCT calculation are performed by the S IMD computer 300.
  • DCT operation, quantization processing, inverse quantization processing, and inverse DCT operation may be performed by a type computer, or each processing may be shared and executed by three or more SIMD type computers. Good.
  • the notifiers 401 to 406, 501 to 506, and 601 to 606 include not only the calculation processing results and the vector information of the block, but also the attributes of each block, such as whether or not the difference processing was performed with the comparison image. Information can be written, and each processor can determine the information and execute different arithmetic processing.
  • Fig. 3 (a) shows the order of motion detection processing in macroblock units for the entire image
  • Fig. 3 (b) shows the processing flow for each macroblock.
  • the whole image (current image) is divided into macroblocks (16 x 16 pixels) and processed for each macroblock.
  • the macro block is composed of luminance (Y0, Y1, Y2, Y3) and color difference (U, V).
  • Each of Y0, ⁇ 1, ⁇ 2, Y3, U, and V is composed of 8 ⁇ 8 color elements.
  • motion detection processing is performed for each macro block. The motion detection processing is performed by detecting a difference from the comparative image.
  • the information after the motion detection processing with the comparative image is the difference value information ( ⁇ ', Y1, Y, Y2, Y3, U, V') for each block Y0, Y1, Y2, Y3, U, V. ) And motion vector information.
  • the above block information is output to the buffers 401 to 406.
  • the difference value information (YO,, ⁇ 1 ', ⁇ 2,, Y3', U,, V,) and motion vector information of each block Y0, Yl, ⁇ 2, Y3, U, V are obtained from buffers 401 to 406.
  • the signals are input to the processors 201 to 206 in parallel, processed in parallel, and the processing results are output to the buffers 501 to 506 in parallel.
  • the processing results and motion vector information of each block ⁇ 0, ⁇ 1, ⁇ 2, , 3, U, V are input in parallel from the buffers 501 to 506 to the processors 301 to 306, and are processed in parallel, and the processing results are buffered. Output to 601 to 606 in parallel.
  • FIG. 6 shows an example in which the image processing apparatus according to the present embodiment is applied to a viewer system.
  • the system includes, for example, an image processing device 700, an ACZDC prediction Huffman 701, an image memory 702, a display circuit 703, a monitor 704, a ROM 705, a RAM 706, a CPU 707, an IF (interface) circuit 708 of the present embodiment. It is configured.
  • the image processing device 700 is connected to the image memory 702 and the AC / DC prediction Huffman 701, the image memory 702 is connected to the display circuit 703, and the display circuit 703 is connected to the monitor 704.
  • the ACZDC prediction Huffman 701, ROM 705, RAM 706, CPU 707, and IF circuit 708 are connected via paths, respectively.
  • the IF circuit 708 is connected to the memory card 709. This system monitors MPEG images taken with digital movie cameras, etc. And a system to display on TV.
  • This system processes dequantization and inverse DCT with only the SIMD type computer 300 among the image processing devices of the embodiment shown in FIG. 1 for processing only MPEG expansion. I do. Since the processing of motion detection, DCT, quantization, inverse quantization and inverse DCT are processed separately by each SIMD computer, the image processing device can be configured with only the necessary parts of the SIMD computer. Smaller size and lower power consumption are possible.
  • image processing such as video compression and decompression, such as MPEG
  • the processing function can be realized by a semiconductor integrated circuit device (electronic component) that can be mounted on a portable home appliance driven by low power consumption such as a digital video camera.
  • the present invention is not limited to this.
  • the image processing apparatus is suitable for use in electronic devices that perform moving image compression / expansion, such as digital video cameras, VCRs, and information terminals.
  • the present invention can be applied to all electronic devices that process calculation algorithms including matrix operations such as image processing and audio processing.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

Dans cette invention, un premier ordinateur SIMD (simple instruction/flot de données multiples) (100) comprend plusieurs processeurs (101 à 116) contenant au moins un calculateur différentiel et une mémoire locale, ces processeurs étant activés par une simple instruction provenant d'une première unité de commande (140) et par un bus de diffusion (160) destiné à transmettre les données provenant de la première unité de commande (140) à tous les processeurs (101 à116). Le premier ordinateur SIMD (100) est connecté à un ou plusieurs seconds ordinateurs SIMD (200) contenant plusieurs processeurs (201 à 206) équipés d'au moins un multiplicateur, ces processeurs étant activés par une simple instruction provenant d'une seconde unité de commande (240). Le premier ordinateur SIMD (100) exécute la détection du mouvement dans le traitement des images et le ou les seconds ordinateurs SIMD (200) exécutent les opérations de transformation en cosinus discrets, de transformation en cosinus discrets inverse, de quantification ou de déquantification dans le traitement des images.
PCT/JP2003/010977 2003-08-28 2003-08-28 Dispositif de traitement d'images WO2005025230A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/JP2003/010977 WO2005025230A1 (fr) 2003-08-28 2003-08-28 Dispositif de traitement d'images
JP2005508742A JP4516020B2 (ja) 2003-08-28 2003-08-28 画像処理装置

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JP2007166192A (ja) * 2005-12-13 2007-06-28 Toshiba Corp 情報処理装置、制御方法およびプログラム
KR100863515B1 (ko) * 2006-10-13 2008-10-15 연세대학교 산학협력단 비디오 신호의 디코딩 방법 및 장치
US11893474B2 (en) 2015-10-23 2024-02-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device

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JPH06292178A (ja) * 1993-03-31 1994-10-18 Sony Corp 適応形ビデオ信号演算処理装置
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007166192A (ja) * 2005-12-13 2007-06-28 Toshiba Corp 情報処理装置、制御方法およびプログラム
KR100863515B1 (ko) * 2006-10-13 2008-10-15 연세대학교 산학협력단 비디오 신호의 디코딩 방법 및 장치
US11893474B2 (en) 2015-10-23 2024-02-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device

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