WO2005022625A1 - 基本セル、端部セル、配線形状、配線方法、シールド配線構造 - Google Patents
基本セル、端部セル、配線形状、配線方法、シールド配線構造 Download PDFInfo
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- WO2005022625A1 WO2005022625A1 PCT/JP2004/012803 JP2004012803W WO2005022625A1 WO 2005022625 A1 WO2005022625 A1 WO 2005022625A1 JP 2004012803 W JP2004012803 W JP 2004012803W WO 2005022625 A1 WO2005022625 A1 WO 2005022625A1
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- WIPO (PCT)
- Prior art keywords
- wiring
- wirings
- basic
- cell
- terminals
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
- G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
- G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a shield wiring technique for making physical analysis of a semiconductor chip difficult and preventing unauthorized reading and falsification of security information.
- circuit information and internal information of semiconductor devices have been required to have a remarkable degree of confidentiality.
- semiconductor devices in the field of IC force are characterized by their safety, it is necessary to protect important information from unauthorized analysis and prevent tampering and copying of internal information.
- one end of a plurality of wirings each having a wiring path formed at 90 degrees is disposed on one of the opposite sides, and the other end of the plurality of wirings is disposed on the other of the opposite sides.
- Each of the one ends of the plurality of wirings is located at a point-symmetric position with respect to any one of the other ends of the plurality of wirings and the center of the outer frame, and the paths of the plurality of wirings are arranged so as not to cross each other. It is characterized by.
- a plurality of wirings each having a wiring path formed at 45 degrees and 90 degrees are arranged, and one end of each of the plurality of wirings is provided in addition to the plurality of wirings. It is characterized by being located at a point-symmetric position with respect to any one of the ends and the center of the outer frame, and wherein the paths of the plurality of wirings are arranged so as not to cross each other.
- a plurality of basic cells having different wiring routes are prepared, and one or the other ends of a plurality of wirings of one basic cell among the prepared basic cells are provided.
- the basic cell is arranged so that one end or the other end of the plurality of wirings of one of the basic cells is connected to form a wiring.
- the wiring pattern may be inverted with respect to the origin of the basic cell.
- the column direction means the direction in which the connection point of each cell is in contact with the connection point of an adjacent cell when the basic cells are arranged in that direction.
- the wiring when one end and the other end of the plurality of wirings are used at a symmetrical position on one side of the opposite side and on the other side, when any of the arranged basic cells is used, Alternatively, the wiring may be turned around the origin of the basic cell and the Y-turn may be inverted on the Y axis.
- the end cell according to the present invention is a pattern for folded connection at the end of the wiring path, and the terminal is provided only on one side at the same position as the terminal position when the basic cells to be connected are arranged side by side.
- the terminals are arranged, and the terminals are associated one by one from both ends of the arranged terminals toward the center, and the associated terminals are wired in a 90-degree route.
- the end of the wiring path be connected back using the end cell.
- the wiring shape according to the present invention includes a step-like wiring path formed at least in part by a wiring in a horizontal and vertical direction on a wiring path wired in an oblique direction. Become a temple symbol.
- a wiring structure of a shielded wire according to the present invention includes a first shielded wire almost completely overlapped on a wire to be protected, and a second shield formed on an upper layer of the first shielded wire. And a lead line.
- the wiring structure of another shield line according to the present invention is formed on the uppermost layer of a semiconductor device.
- the connection between the cable and the lower layer wiring, and making a wiring bridge in some places, are four temples.
- one end of a plurality of wirings whose wiring paths are formed at 45 degrees or 90 degrees is disposed on one of the opposite sides, and the other end of the plurality of wirings is disposed on the other of the opposite sides.
- Each of the plurality of wirings is arranged in a straight line between one end and the other end thereof, and the plurality of wirings are arranged in parallel with each other.
- Another wiring method according to the present invention is to prepare a plurality of the above basic cells, and to provide one end or the other end of a plurality of wirings of one basic cell among the prepared basic cells, and the other of the prepared basic cells.
- a wiring is formed by arranging a basic cell so that one end or the other end of a plurality of wirings of another basic cell is connected.
- Another wiring structure according to the present invention is a plurality of wirings each having a wiring path formed at 45 degrees or 90 degrees, wherein the plurality of wirings are arranged in parallel by a straight line without folding.
- Another end cell according to the present invention is a pattern for folded connection at the end of the wiring path, and a terminal is provided only on one side at the same position as the terminal position when the above basic cells are arranged side by side.
- Each of the arranged and arranged terminals is characterized in that it is connected to any one of the arranged other terminals other than the terminal arranged next to itself.
- the end portions of the wiring path are connected back using a plurality of end cells having different connection relationships between terminals.
- Another wiring structure according to the present invention is a plurality of wirings folded back at a path end, wherein each of the plurality of wirings is adjacent to a wiring of a path different from its own path among the plurality of wirings. Are combined.
- a plurality of small-area wiring patterns can be easily selected, By randomizing the number, it is possible to generate a less regular shielded wiring that is different from a simple array layout.
- the conventional shielded wire uses the shield Since the same path is adjacent at the turn-back part of the area, it was possible to analyze the area of two or more paths of the shield wiring in one processing time as the processing time to connect the cut shield wire with another path.
- a probe for circuit wiring in a shield wiring removal area is provided. In comparison with conventional circuit analysis, the processing time for the analysis of two or more paths of the shielded wiring can be doubled or more than before, and the processing difficulty can be increased.
- the top layer wiring has a regular pattern, but generates a shield line path with less regularity, which makes circuit analysis difficult. The degree can be increased.
- FIG. 1 is a diagram showing a schematic procedure of a method of wiring a shield line according to the first embodiment.
- FIG. 2 is a diagram illustrating an example of a basic cell.
- FIG. 3 is a diagram for explaining the rules for determining the terminal positions of the basic cells of the 90-degree wiring type (1).
- FIG. 4 is a diagram showing an example of a basic cell of the 90-degree wiring type (1).
- FIG. 5 is a diagram showing an example of a basic cell of the 90-degree wiring type (1).
- FIG. 6 is a diagram showing an example of a basic cell of the 90-degree wiring type (1).
- FIG. 7 is a diagram for explaining the rules for determining the terminal positions of the basic cells of the 90-degree wiring type (2).
- FIG. 8 is a diagram showing an example of a basic cell of the 90-degree wiring type (2).
- FIG. 9 is a diagram showing an example of a basic cell of the 90-degree wiring type (2).
- FIG. 10 is a diagram showing an example of an end cell.
- FIG. 11 is a diagram for explaining a rule for determining a terminal position of an end cell.
- FIG. 12 is a diagram showing an example of an end cell for the 90-degree wiring type (1).
- FIG. 13 is a diagram showing an example of an end cell for the 90-degree wiring type (2).
- FIG. 14 is a diagram for explaining a rule for determining a terminal position of a 45-degree wiring type basic cell.
- FIG. 15 is a diagram illustrating an example of a 45-degree wiring type basic cell.
- FIG. 16 is a diagram showing an example of a 45-degree wiring type basic cell.
- FIG. 17 is a diagram showing an example of an end cell for a 45-degree wiring type.
- FIG. 18 is a diagram for explaining a method of arranging the basic cells and the end cells of the 90-degree wiring type (1).
- FIG. 19 is a diagram showing an example of shielded wires wired according to a method of arranging 90-degree wiring type (1) basic cells and end cells.
- FIG. 20 is a diagram for explaining a method of arranging a basic cell and a partial cell of the 90-degree wiring type (2).
- FIG. 21 is a diagram showing an example of shielded wires wired according to the method of arranging the 90-degree wiring type (2) basic cells and end cells.
- FIG. 22 is a diagram for explaining a method of arranging a 45-degree wiring type basic cell and end cells.
- FIG. 23 is a diagram showing an example of shielded wires wired by a method of arranging a 45-degree wiring type basic cell and end cells.
- FIG. 24 is a diagram showing an example of a wiring path that can be realized by devising the insertion position of the end pattern (end cell).
- FIG. 25 is a diagram illustrating an example of a wiring path that can be realized by devising the insertion position of the end pattern (end cell).
- FIG. 26 is a diagram illustrating an example of a basic cell.
- FIG. 27 is a diagram illustrating an example of the i3 ⁇ 4 part cell.
- FIG. 28 is a diagram illustrating an example of a cell row arranged by the method of arranging the basic cells and the end cells according to the second embodiment.
- FIG. 29 shows an example of a shielded well path arranged according to the arrangement method of the basic cells and the end cells according to the second embodiment.
- FIG. 30 is a diagram showing a structure of a basic cell according to the third embodiment.
- FIG. 31 is a diagram showing a shield wiring structure according to the fourth embodiment.
- FIG. 32 is a diagram showing a shield wiring structure according to the fifth embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 shows a schematic procedure of a shielded wiring method according to the first embodiment.
- the shield line is wired on the top layer of the wiring so as to hide the mask pattern in order to prevent reading of the mask pattern for duplication and falsification of the semiconductor chip, and to prevent circuit analysis by a probe on the wiring.
- a plurality of small-area wiring patterns (basic cells) are prepared, and the selection and arrangement of the wiring patterns are made random. It should be noted that the same battery (basic cell) may be adjacent to each other. This makes it possible to generate shield wiring with less regularity, which is different from a simple array arrangement. This will be specifically described below.
- the design rules for the wiring pattern (basic cell), which is the basic unit of shield wiring, will be described.
- An example of a basic cell is shown in Fig. 2 to facilitate understanding of the design rules.
- the design rules are determined as follows in order to make the wiring density uniform. -The outer frame of the pattern (basic cell) is rectangular.
- the distance between the wiring and the pattern outer frame is 1/2 of the wiring distance.
- the rule values are determined based on the wiring rules and the capability of the wiring prober based on the design rules.
- a basic cell is created according to the above rules. Here, the following three types of basic cells are created.
- the 90-degree wiring type (1) consists of 90-degree wiring paths (so that the wiring path is 90 degrees to any one side around the LSI chip). ), And the terminal positions are not symmetrical. The position of the terminal is determined according to the following rules.
- the 90-degree wiring type (2) has a 90-degree wiring path as shown in Figs. 7 (a) and (b). 90 degrees), and the terminal positions are symmetrical. Terminal positions are determined according to the following rules.
- the entry and exit of the wiring are located on opposite sides of the pattern outer frame.
- the terminal position for each side is at the ⁇ axis target centered on the origin of the pattern (marked by X in Fig. 7).
- Figs. 8 to 9 show examples of basic cells of the 90-degree wiring type (2) created in this way.
- end cells for the 90-degree wiring types (1) and (2) are created.
- the lower cell is a pattern for the folded connection at the end of the wiring path in the shield wiring, and FIG. 10 shows an example thereof.
- Edge cells are created according to the following rules to equalize the density of wiring ⁇
- the outer frame of the pattern shall be two wiring patterns (basic cells) arranged side by side. -Make all wiring intervals the same.
- the distance between the wiring and the pattern outer frame is 1 / of the wiring distance.
- the rule values are determined based on the wiring rules and the capability of the wiring prober based on the design rules.
- the terminal positions of the end cells are determined according to the following rules.
- the 45-degree wiring type as shown in Fig. 14, has a wiring thread route of 45 degrees and 90 degrees (the wiring route is 45 degrees to any one side around the LSI chip). Or 90 degrees).
- the positions of the terminals are determined according to the following rules.
- the next step is to select the type of basic cell to be used for shielded wiring.
- Basic cells and end cells are arranged according to different arrangement rules according to the selected basic cell type. This will be specifically described below.
- the end patterns are arranged in a row in the horizontal direction at the pitch of the end pattern outer frame. At this time, an end pattern is randomly selected. Top and bottom at the top of the placement area The inverted end patterns are arranged in a row in the horizontal direction at the pitch of the end pattern outer frame. At this time, the end pattern is selected at random. If the wiring pattern has an even number of steps, the upper end pattern is shifted by one outer frame size of the wiring pattern (see Fig. 18 (c)). If there are an odd number of steps, the outer pattern size of the wiring pattern is 1.5. (See Fig. 18 (d).)
- Fig. 19 shows an example of the shielded wires wired as described above.
- the end patterns are arranged in a line in the horizontal direction at the pitch of the end pattern outer frame. At this time, the end pattern is selected at random.
- the end patterns inverted upside down are arranged at a pitch of the end pattern outer frame, and are shifted in the horizontal direction by a distance equal to one outside of the wiring pattern. At this time, an end pattern is selected at random (see FIG. 20 (b)).
- Fig. 21 shows an example of shielded wires wired as described above.
- Wiring patterns are arranged in the shield area at the pitch of the wiring pattern outer frame. At this time, a wiring pattern is selected at random, and the Y axis is inverted at random around the origin of the pattern (see Fig. 22 (a)).
- the placement start position is shifted from the position of (1) above to the vertical and horizontal size of the wiring pattern outer frame by half and the wiring pattern is arranged by the same number of wiring pattern outer frame pitches as in (1). ⁇ ⁇ axis reversal is performed randomly around the origin of. At this time, run the wiring pattern Choose to a dam. After placement, multiple vertical wiring routes are created (see Figure 22 (b)).
- the placement start position is shifted from the position (1) by half the size of the placement pattern outer frame, and the end patterns are arranged in a row at the pitch of the end pattern outer frame. At this time, the end pattern is selected at random.
- the end patterns that are turned upside down are arranged in a row in the horizontal direction at the pitch of the outer frame of the end patterns. At this time, the end pattern is randomly selected.
- the placement position is shifted in the horizontal direction according to the number of wiring pattern steps (see Fig. 22 (c)).
- Figure 23 shows an example of a shielded wire wired as described above.
- the wiring route can be complicated as shown in FIGS. 24 and 25.
- the schematic procedure of the shielded wiring method according to the second embodiment is the same as the procedure shown in FIG.
- basic cells of a plurality of paths that are always parallel, and end cells for the return connection where the same path is not adjacent are arranged.
- the processing time for the analysis of the area of two or more paths of the shield wiring is more than doubled compared to the circuit analysis by the probe to the circuit wiring in the shield wiring removal area, and the processing difficulty is increased.
- a specific description will be given.
- the design rules of the basic cell which is the basic unit of the shielded wire, will be described.
- the design rules are defined as follows in order to make the wiring density uniform.
- -Wiring is the uppermost layer of wiring, and is arranged in parallel with other wiring in a straight line.
- the distance between the wiring and the outer frame of the basic cell shall be 1/2 of the wiring distance.
- -Terminals are placed on the opposite side of the pattern outer frame, and the terminals placed on one side and the other side Arrange them at the positions where they are connected to the terminals by wiring.
- the wiring interval is determined based on the wiring rule and the capability of the wiring prober based on the design rules.
- a basic cell is created according to the above rules.
- two types of basic cells type (1) and type (2), are created.
- Type (1) is as shown in Fig. 26 (a).
- the wiring route to the chip is configured at 90 degrees (the wiring route is configured to be 90 degrees to any one side around the LSI chip), and the type (2) As shown in Fig. 26 (b), the wiring route to the chip is configured at 45 degrees (so that the wiring route is 45 degrees to any one side around the LSI chip). Configured).
- the end cell is a pattern for folded connection at the end of the wiring route, and the design rule is determined as follows. -The outer frame of the end cell shall be the size of two basic cells arranged side by side.
- -Wiring is arranged so that the same route is not folded back and adjacent using contacts that connect the wiring top layer, the wiring bottom layer, and the wiring top layer and the wiring bottom layer.
- the distance between the top layer of wiring and the outer frame of the basic cell is 1 / of the wiring distance in the top layer of wiring.
- -Terminals should be placed only on one side at the same location as the terminal positions when two basic cells are arranged side by side.
- the wiring interval is determined based on the wiring rule and the capability of the wiring probe based on the design rules.
- FIGS. 27 (a) to (c) Examples of edge cells created according to the above rules are shown in Figs. 27 (a) to (c).
- each terminal is connected to one of the other terminals other than the terminal arranged next to itself by a wiring lower layer and a contact.
- the correspondence of connection between terminals is different from each other.
- FIG. 28 shows an example of a cell row arranged in this manner.
- Fig. 28 (a) shows an example in which basic cells and partial cells of type (1) are arranged
- Fig. 28 (b) shows an example in which basic cells and end cells of type (2) are arranged. is there.
- Fig. 29 (a) shows an example of the shield line route wired as described above.
- the area of the shielded wiring removal area can be reduced to two or more paths of the shielded wiring for the circuit analysis by the probe to the circuit wiring.
- the processing time for the analysis of the workpiece can be more than doubled, and the processing difficulty can be increased.
- Fig. 29 (a) only the end cells (here, the type shown in Fig. 27 (a)) that have the same connection relation between the terminals are used.
- the wiring in the upper layer is regular as path 1, path 2, path 3, path 4 'path 1, path 2, path 3, path 4,--.
- the end cells in which the correspondences between the terminals are different here, the type shown in Fig. 27 (a), The type shown in Fig. 27 and the type shown in Fig. 27 (c)
- the wiring in the uppermost layer is route 1, route 2, route 3, route 4, route 3, route 4, route 1, and route 2 , ⁇ ⁇ ⁇ irregular.
- the top layer wiring has a regular pattern (a pattern in which a plurality of straight wirings are arranged in parallel). Nevertheless, it is possible to generate a shielded wire path with less regularity, thereby increasing the difficulty of circuit analysis.
- FIG. 30 shows the structure of a basic cell according to the third embodiment.
- This basic cell is obtained by realizing a 45-degree path in a normal 45-degree wiring type basic cell as shown in the first and second embodiments by a 90-degree step-like path. Edge processing and machining difficulties This eases the difficulty.
- the finish of the stepped portion of P is crushed and becomes almost 45-degree wiring.
- the exposed area of the lower layer is smaller than that of the normal 45-degree path by the step-like shape.
- Shield wiring can be realized by laying the basic cells shown in FIG. 30 in the shield region in the same manner as in the first and second embodiments.
- FIG. 31 shows a shield wiring structure according to the fourth embodiment.
- the lower-layer shield line is completely overlapped with the protective wiring and wired.
- the direction of the upper shield wire does not matter.
- FIG. 32 shows a shield wiring structure according to the fifth embodiment.
- the uppermost layer is a shield wiring layer, and circuit wiring is partially mixed (covers up to the upper limit of the area ratio). Automatically insert dummy wiring into the empty area of the middle layer (up to the upper limit of the area ratio of each layer). Connect each dummy wiring and the wiring in the lower layer, and make a wiring bridge in some places.
- the present invention can be used for a shield wiring arrangement for protecting a semiconductor chip that requires high confidentiality / confidentiality in circuit information and internal information from duplication and tampering.
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Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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EP04772752A EP1670050A4 (en) | 2003-08-28 | 2004-08-27 | ELEMENTARY CELL, EXTREMITY SECTION CELL, WIRING FORM AND WIRING METHOD, PROTECTION WIRING STRUCTURE |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2003305392 | 2003-08-28 | ||
JP2003-305392 | 2003-08-28 | ||
JP2004183810A JP4758621B2 (ja) | 2003-08-28 | 2004-06-22 | 基本セル、端部セル、配線形状、配線方法、シールド線の配線構造 |
JP2004-183810 | 2004-06-22 |
Publications (1)
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WO2005022625A1 true WO2005022625A1 (ja) | 2005-03-10 |
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Family Applications (1)
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PCT/JP2004/012803 WO2005022625A1 (ja) | 2003-08-28 | 2004-08-27 | 基本セル、端部セル、配線形状、配線方法、シールド配線構造 |
Country Status (5)
Country | Link |
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US (2) | US7194719B2 (ja) |
EP (2) | EP1670050A4 (ja) |
JP (1) | JP4758621B2 (ja) |
TW (1) | TW200511503A (ja) |
WO (1) | WO2005022625A1 (ja) |
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WO2007091210A2 (en) * | 2006-02-09 | 2007-08-16 | Nxp B.V. | Circuit arrangement, data processing device comprising such circuit arrangement as well as method for identifying an attack on such circuit arrangement |
JP4969426B2 (ja) * | 2007-12-07 | 2012-07-04 | 東プレ株式会社 | 破壊検知用パターン板 |
US9117052B1 (en) | 2012-04-12 | 2015-08-25 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns |
US9003349B1 (en) | 2013-06-28 | 2015-04-07 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks |
US8984465B1 (en) | 2013-06-28 | 2015-03-17 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for automatically assigning track patterns to regions for physical implementation of an electronic design |
US9251299B1 (en) * | 2013-06-28 | 2016-02-02 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs |
US9213793B1 (en) | 2012-08-31 | 2015-12-15 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks |
US9104830B1 (en) | 2013-06-28 | 2015-08-11 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design |
US9183343B1 (en) | 2012-08-31 | 2015-11-10 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs |
US9817941B2 (en) | 2012-12-04 | 2017-11-14 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs |
US9165103B1 (en) | 2013-06-28 | 2015-10-20 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for tessellating and labeling routing space for routing electronic designs |
JP6274970B2 (ja) * | 2014-05-26 | 2018-02-07 | 日本電産サンキョー株式会社 | プリント基板およびカードリーダ |
ES2877773T3 (es) * | 2017-01-27 | 2021-11-17 | Aselsan Elektronik Sanayi Ve Ticaret Anonim Sirketi | Un sistema de protección de zona sensible electrónico |
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- 2004-08-27 EP EP04772752A patent/EP1670050A4/en not_active Withdrawn
- 2004-08-27 EP EP16186182.8A patent/EP3154076A1/en not_active Ceased
- 2004-08-27 WO PCT/JP2004/012803 patent/WO2005022625A1/ja active Application Filing
- 2004-08-27 TW TW093125770A patent/TW200511503A/zh unknown
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2007
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Also Published As
Publication number | Publication date |
---|---|
US20050050507A1 (en) | 2005-03-03 |
US20070162884A1 (en) | 2007-07-12 |
US7376928B2 (en) | 2008-05-20 |
JP4758621B2 (ja) | 2011-08-31 |
EP1670050A4 (en) | 2011-06-15 |
TW200511503A (en) | 2005-03-16 |
JP2005101526A (ja) | 2005-04-14 |
EP1670050A1 (en) | 2006-06-14 |
US7194719B2 (en) | 2007-03-20 |
EP3154076A1 (en) | 2017-04-12 |
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