WO2003019649A8 - Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung - Google Patents
Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnungInfo
- Publication number
- WO2003019649A8 WO2003019649A8 PCT/DE2002/002946 DE0202946W WO03019649A8 WO 2003019649 A8 WO2003019649 A8 WO 2003019649A8 DE 0202946 W DE0202946 W DE 0202946W WO 03019649 A8 WO03019649 A8 WO 03019649A8
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- conductor arrangement
- strip conductor
- producing
- buffer layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02754521A EP1419525A2 (de) | 2001-08-20 | 2002-08-09 | Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung |
US10/487,190 US7033926B2 (en) | 2001-08-20 | 2002-08-09 | Strip conductor arrangement and method for producing a strip conductor arrangement |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10140754A DE10140754A1 (de) | 2001-08-20 | 2001-08-20 | Leiterbahnanordnung und Verfahren zum Herstellen einer Leiterbahnanordnung |
DE10140754.8 | 2001-08-20 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2003019649A2 WO2003019649A2 (de) | 2003-03-06 |
WO2003019649A3 WO2003019649A3 (de) | 2003-08-07 |
WO2003019649A8 true WO2003019649A8 (de) | 2003-11-13 |
Family
ID=7696008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2002/002946 WO2003019649A2 (de) | 2001-08-20 | 2002-08-09 | Leiterbahnanordnung und verfahren zum herstellen einer leiterbahnanordnung |
Country Status (5)
Country | Link |
---|---|
US (1) | US7033926B2 (de) |
EP (1) | EP1419525A2 (de) |
DE (1) | DE10140754A1 (de) |
TW (1) | TW571422B (de) |
WO (1) | WO2003019649A2 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7361991B2 (en) * | 2003-09-19 | 2008-04-22 | International Business Machines Corporation | Closed air gap interconnect structure |
US7071532B2 (en) * | 2003-09-30 | 2006-07-04 | International Business Machines Corporation | Adjustable self-aligned air gap dielectric for low capacitance wiring |
DE102004003337A1 (de) * | 2004-01-22 | 2005-08-18 | Infineon Technologies Ag | Plasmaangeregtes chemisches Gasphasenabscheide-Verfahren, Silizium-Sauerstoff-Stickstoff-haltiges Material und Schicht-Anordnung |
DE102004050391B4 (de) | 2004-10-15 | 2007-02-08 | Infineon Technologies Ag | Verfahren zum Herstellen einer Schicht-Anordnung und Schicht-Anordnung |
DE102005039323B4 (de) * | 2005-08-19 | 2009-09-03 | Infineon Technologies Ag | Leitbahnanordnung sowie zugehöriges Herstellungsverfahren |
US20070090433A1 (en) * | 2005-10-26 | 2007-04-26 | International Business Machines Corporation | Isolation collar void and methods of forming the same |
US7649239B2 (en) * | 2006-05-04 | 2010-01-19 | Intel Corporation | Dielectric spacers for metal interconnects and method to form the same |
US7772702B2 (en) * | 2006-09-21 | 2010-08-10 | Intel Corporation | Dielectric spacers for metal interconnects and method to form the same |
US7973409B2 (en) | 2007-01-22 | 2011-07-05 | International Business Machines Corporation | Hybrid interconnect structure for performance improvement and reliability enhancement |
US7871923B2 (en) * | 2007-01-26 | 2011-01-18 | Taiwan Semiconductor Maufacturing Company, Ltd. | Self-aligned air-gap in interconnect structures |
US20090081862A1 (en) * | 2007-09-24 | 2009-03-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Air gap structure design for advanced integrated circuit technology |
US8399350B2 (en) * | 2010-02-05 | 2013-03-19 | International Business Machines Corporation | Formation of air gap with protection of metal lines |
US8497203B2 (en) | 2010-08-13 | 2013-07-30 | International Business Machines Corporation | Semiconductor structures and methods of manufacture |
CN104025263B (zh) | 2011-12-30 | 2018-07-03 | 英特尔公司 | 自封闭的非对称互连结构 |
US8772938B2 (en) | 2012-12-04 | 2014-07-08 | Intel Corporation | Semiconductor interconnect structures |
TWI493754B (zh) * | 2013-07-18 | 2015-07-21 | Univ Nat Cheng Kung | Luminescent diodes with interfacial periodic structure |
US10157778B2 (en) * | 2016-05-31 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and manufacturing method thereof |
JP6685945B2 (ja) * | 2017-01-31 | 2020-04-22 | キオクシア株式会社 | 半導体装置およびその製造方法 |
US11302662B2 (en) | 2020-05-01 | 2022-04-12 | Nanya Technology Corporation | Semiconductor package with air gap and manufacturing method thereof |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5324683A (en) | 1993-06-02 | 1994-06-28 | Motorola, Inc. | Method of forming a semiconductor structure having an air region |
US5908318A (en) * | 1995-12-08 | 1999-06-01 | Advanced Micro Devices, Inc. | Method of forming low capacitance interconnect structures on semiconductor substrates |
US5792706A (en) * | 1996-06-05 | 1998-08-11 | Advanced Micro Devices, Inc. | Interlevel dielectric with air gaps to reduce permitivity |
US6242336B1 (en) * | 1997-11-06 | 2001-06-05 | Matsushita Electronics Corporation | Semiconductor device having multilevel interconnection structure and method for fabricating the same |
JP3328931B2 (ja) * | 1999-02-05 | 2002-09-30 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6888247B2 (en) * | 1999-09-03 | 2005-05-03 | United Microelectronics Corp. | Interconnect structure with an enlarged air gaps disposed between conductive structures or surrounding a conductive structure within the same |
JP2002026016A (ja) * | 2000-07-13 | 2002-01-25 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6472266B1 (en) * | 2001-06-18 | 2002-10-29 | Taiwan Semiconductor Manufacturing Company | Method to reduce bit line capacitance in cub drams |
-
2001
- 2001-08-20 DE DE10140754A patent/DE10140754A1/de not_active Ceased
-
2002
- 2002-08-09 WO PCT/DE2002/002946 patent/WO2003019649A2/de not_active Application Discontinuation
- 2002-08-09 US US10/487,190 patent/US7033926B2/en not_active Expired - Fee Related
- 2002-08-09 EP EP02754521A patent/EP1419525A2/de not_active Withdrawn
- 2002-08-20 TW TW091118796A patent/TW571422B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US7033926B2 (en) | 2006-04-25 |
WO2003019649A3 (de) | 2003-08-07 |
EP1419525A2 (de) | 2004-05-19 |
US20050079700A1 (en) | 2005-04-14 |
TW571422B (en) | 2004-01-11 |
DE10140754A1 (de) | 2003-03-27 |
WO2003019649A2 (de) | 2003-03-06 |
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