WO1999027376A1 - Procede de test de circuits integres et appareil de test de circuits integres utilisant ce procede - Google Patents

Procede de test de circuits integres et appareil de test de circuits integres utilisant ce procede Download PDF

Info

Publication number
WO1999027376A1
WO1999027376A1 PCT/JP1997/004228 JP9704228W WO9927376A1 WO 1999027376 A1 WO1999027376 A1 WO 1999027376A1 JP 9704228 W JP9704228 W JP 9704228W WO 9927376 A1 WO9927376 A1 WO 9927376A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
terminal
voltage
under test
switch
Prior art date
Application number
PCT/JP1997/004228
Other languages
English (en)
Japanese (ja)
Inventor
Yoshihiro Hashimoto
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to US09/319,898 priority Critical patent/US6404220B1/en
Priority to DE19782244T priority patent/DE19782244T1/de
Priority to JP52143599A priority patent/JP3426254B2/ja
Priority to CNB971814333A priority patent/CN1141593C/zh
Priority to GB9912919A priority patent/GB2335280B/en
Priority to PCT/JP1997/004228 priority patent/WO1999027376A1/fr
Priority to TW086118710A priority patent/TW356526B/zh
Publication of WO1999027376A1 publication Critical patent/WO1999027376A1/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test

Definitions

  • the present invention when performing a functional test and a DC test of a semiconductor device such as a memory configured by a semiconductor integrated circuit, a leak test of the items of the functional test and the DC test is performed in a short time.
  • the present invention relates to an IC test method capable of performing the above-mentioned steps and an IC test apparatus using the method.
  • the C tester uses a functional test to ask whether the semiconductor device functions properly.
  • a DC test is performed to determine whether or not the IC has an IC, and ICs that are determined to be normal in both tests are determined to be non-defective.
  • Fig. 3 shows the schematic configuration of the IC test equipment.
  • TES indicates the reference numeral assigned to the entire IC test apparatus.
  • the inside of the 1C test equipment TES is roughly divided into a main controller MAIN, a functional test equipment 100, and a DC test equipment 200.
  • the main controller MAIN is constituted by a computer system, and controls the function test apparatus 100 and the DC test apparatus 200 through the bus line BUS.
  • the function test apparatus 100 is composed of a pattern generator 102, an evening generator 104 and a function test unit 106, 106, 106, 106. Be composed.
  • Functional test Yuni' DOO 1 0 6 ⁇ 1 0 6 ⁇ provided corresponding to each terminal of the DUT IC 3 0 0, sweep rate pitch SM ⁇ S ln ON, functional test and off control Yuni' sheet 1 0 It is configured so that 6 A-106 N can be controlled to be connected to each terminal of the DUT under test C 300 and to be disconnected.
  • the switch S ⁇ Sh is turned on, the function test unit 106 A to 100 ⁇ is connected to each terminal of the IC 300 under test, and IC 30 A test pattern signal is applied to each terminal of 0 to execute a function test.
  • one to several DC test devices 200 are provided for the terminal of the IC 300 under test (the example in FIG. 3 shows a case where one DC test device 200 is prepared). sequentially connecting the DC test device 0 0 by controlling to turn on the switching sweep rate Tutsi S 2 1 ⁇ S sequentially one by one for each terminal of the DUT IC 3 0 0, sequential testing DC characteristics of the identified terminal Configuration.
  • 4 0 0 indicates these sweep rate pitch 3, 1-3 1 "and 3 2 1 controller for controlling to 3 2 n.
  • Fig. 4 shows the internal configuration of one of the functional test units 106 ⁇ , and outlines the functional test.
  • the function test unit 106 A (which has the same configuration as other function test units) has a waveform formatter i 1, a driver 12, a voltage comparator 13, a logic comparator 14, and a failure analysis memory i 5 It is constituted by and.
  • the waveform window 11 receives the test pattern data supplied from the pattern generator 102 and generates a test pattern signal having an actual waveform.
  • the timing generator 104 supplies the waveform formatter # 1 with a timing signal that defines the rising timing and the falling timing of the test pattern signal.
  • the test pattern signal output from the waveform format 11 is shaped into a waveform having an amplitude having a predetermined logical value by the driver 12 and the IC under test 30 is switched through the switches S,,. 0 is supplied to a predetermined terminal, and the data is stored in the IC under test 300.
  • this terminal is an I / O terminal (input / output terminal)
  • each terminal of the IC under test 300 is controlled to the input mode, and the write operation is completed.
  • the mode is switched to the output mode at the point in time.
  • the contents stored in the IC under test 300 are read out at the timing when the mode is switched to the output mode, and input to the logic comparator 14 via the voltage comparator 13.
  • the output terminal of the driver 12 is set to the high impedance mode. Then, a comparison is made as to whether the logic of the signal read from the IC under test 300 maintains a normal voltage value. In other words, it is determined whether the L delirium and the H logic have, for example, 0.8 volts or less and 2.4 volts or more, and the power of a normal logic value is determined. If there is a voltage, the logical value is input to the logical comparator 14.
  • the logical comparator 14 receives the expected value from the pattern generator 102 and compares the expected value with the logical value input from the voltage comparator 13 to detect the occurrence of a mismatch. If a mismatch occurs, it is determined that there is a defect in the memory cell of the written address and stored in that address of the defect analysis memory 15, and the number of defective cells is counted from the defect analysis memory 15 after the test is completed. Read and count to determine if relief is possible.
  • FIG. 5 shows an example of the configuration of the DC test apparatus 200. The illustrated configuration shows a configuration in which the DC test apparatus 200 operates in the voltage applied current measurement mode. To the non-inverting input terminal of the operational amplifier 16, a voltage or V H having a logical value to be supplied from the DA converter 17 to the terminal of the IC under test 300 is applied.
  • the switch S b connected in parallel with the current detection resistor R 1 is a range switch for switching the current measurement range.
  • the sweep rate Tsu resistance by controlling to turn on the switch S B is small ie, connect a resistor R 2 to measure a large current (current at the output mode one de the tested IC 3 0 0), the large current measurement Switch to range.
  • the operational amplifier 16 since the operational amplifier 16 operates so that the voltage at the non-inverting input terminal and the voltage at the inverting input terminal become equal, if, for example, VL is applied to the non-inverting input terminal of the operational amplifier 16, the voltage (voltage (Same as the voltage of the detection terminal T v). Therefore, the voltage or V is applied to the IC Is given.
  • each terminal P i of the IC under test 300 is set to the input mode shown in FIG.
  • the terminal P is connected to the terminal P i by measuring the current flowing through the current detection resistor R 1 with V L (voltage giving L logic) or V U (voltage giving H logic) applied.
  • the respective leakage currents I and I k 2 of the active device can be measured.
  • Reference numeral 18 denotes a subtraction circuit for extracting the voltage generated in the current detection resistor R i
  • reference numeral 19 denotes an AD converter that AD-converts the voltage obtained by the subtraction circuit 18 and outputs a digital value. Is shown.
  • the switching switch S b When measuring the leak currents I Rekl and I described above, the switching switch S b is turned off, and is generated in the current detection resistor R 1 having a relatively high resistance value of about 100 k ⁇ . that the voltage is measured, and measuring the re one leakage current I Kek l and I Rek ;! flowing to the input terminals of the DUT IC 3 0 0.
  • the protective resistor R 3 is constituted by a resistor ratio ⁇ a small resistance value (about several 1 0 Omega) resistance, as Suitsuchi S al and S 2 during production is controlled to be turned off at the same time This is also a resistor for securing a closed feedback loop for the inverting input terminal of the operational amplifier 16 and protecting the operational amplifier 16 so that the operation of the operational amplifier 16 does not reach a saturation state.
  • the DC test apparatus 200 is disconnected from the terminal of the IC under test 300, and the switches S, ,, ⁇ S, and n are all controlled to the on state.
  • a test is performed. That is, since the output impedance of the DC test apparatus 200 is relatively low, on the order of several ⁇ , it is assumed that the DC test apparatus 200 is electrically connected as a load of the functional test apparatus 100 during the function test. , Functional test equipment 100 to IC under test The waveform of the test pattern signal supplied to 300 is degraded, which causes a problem that a normal function test cannot be performed.
  • an initialization pattern for setting the mode of that terminal to the input mode is used as the function test equipment 100 Enter from.
  • the terminals to be tested for DC are set to the input mode, disconnect all the functional test units 106 to ⁇ from the terminals to be tested for DC from terminals of IC 300 under test. Perform control.
  • the DC test measures the leakage currents I and I Rek2 (see Fig. 6) flowing through the terminals when the logic values of H logic and L logic are given to the terminals of the IC under test 300, respectively. If the peak current value is less than the expected value, it is determined to be good.
  • An object of the present invention is to propose an IC test method capable of shortening the Ic test time and testing a large number of ICs in a short time, and an IC test apparatus using this test method. Disclosure of the invention
  • the DC test apparatus is connected to the terminal of the IC under test via a resistor, and the connection of the resistor is devised so that the DC test apparatus does not become a large load as viewed from the functional test apparatus.
  • the feature is that the DC test equipment can be kept connected to the terminal of the IC under test even during the functional test.
  • the DC test can be executed by controlling the output terminal of the driver of the functional test device to the high-impedance mode even during the functional test, and the switch for disconnecting the functional test device even during the DC test is executed. It proposes an IC test method that eliminates the need for control and executes the leak test in the DC test items during the function test.
  • the leak test of the DC test item is completed at the same time as the completion of the functional test, and the leak test does not need to be performed with a special time. As a result, there is an advantage that the time required for the test can be significantly reduced.
  • the present invention further proposes an IC test apparatus using the above-described IC test method.
  • the IC test apparatus is a functional test that applies a test pattern signal to each terminal of an IC under test by a driver capable of setting the state of an output terminal to a high impedance mode, and executes a 1C functional test under test.
  • a DC test device for measuring a leak current flowing through each terminal of the IC under test while a predetermined voltage is applied to each terminal of the IC under test;
  • a resistor connected between the sensing point of the DC tester and the terminal of the IC under test;
  • First control means for outputting a predetermined voltage to a sensing point of the DC test apparatus while the function test apparatus is performing the function test;
  • Second control means for controlling the output terminal of the driver of the functional test device to a high impedance mode when the control operation of the first control means is completed;
  • the DC test can be executed during the execution of the function test without passing through the time required for switching the switch.
  • FIG. 1 is a block diagram showing an embodiment of an IC test apparatus ffl employing the IC test method according to the present invention.
  • FIG. 2 is a timing chart for explaining the IC test method according to the present invention.
  • FIG. 3 is a block diagram for explaining the outline of a conventional IC test apparatus.
  • FIG. 4 is a block diagram for explaining a configuration of a functional test device used in the IC test device shown in FIG.
  • FIG. 5 is a connection diagram for explaining the configuration of a DC test device used in the IC test device shown in FIG.
  • Fig. 6 is a connection diagram explaining the state of the IC terminals under test when performing a leak test in the DC test items.
  • Figure 6 shows a timing chart for explaining the state of a conventional DC test.
  • FIG. 1 shows an embodiment of an IC test apparatus for testing an IC under test 300 according to the IC test method proposed in the present invention.
  • 100 is a functional test device
  • 200 is a DC test device, which is the same configuration as that described in FIG.
  • the switches S i, to S ln are all turned on, and all the functional test units 106 A to 106 N are connected to the IC under test 300. It is executed by connecting to each terminal.
  • the DC test apparatus 200 controls the switching switches S i S ⁇ one by one sequentially in an on state, selectively connects the DC test apparatus 200 to each terminal of the IC under test 300, Perform a DC test for each terminal one by one.
  • a plurality of DC test devices 200 are provided, and the number of terminals for the test is reduced so that the DC test can be completed in a short time. The description will be made assuming that the DC test apparatus 200 executes the test.
  • a feature of the IC test apparatus according to the present invention is that in the DC test apparatus 200, a resistor R4 is connected in series with the switch S2 between the voltage detection terminal Tv and the sensing point S ⁇ .
  • the second switch S1 is connected in parallel to the protection resistor R3 connected between the current output terminal and the voltage detection terminal ⁇ , and the voltage detection terminal ⁇
  • the second switch S 2 and the resistor R 4 are connected in series between the point S ⁇ ⁇ .
  • a third switch S3 is connected between the current output terminal and the sensing point S ⁇ .
  • the impedance when the DC test apparatus 200 is viewed from the functional test unit to which the DC test apparatus 200 is connected can be viewed as the resistance value of the resistor R4.
  • the resistance value of resistor R4 By selecting the resistance value of resistor R4 to be about 10 k ⁇ , the impedance of DC test apparatus 200 as viewed from functional test unit 106 A to 106 N is about 1 O k Q It can be seen as
  • the transmission line is generally matched to a characteristic impedance of 50 ⁇ . Therefore, even if a load of 100 k ⁇ (DC test equipment 200) is connected to each output side of the functional test unit 106 A to 106 N, the impedance of the line fluctuates significantly. And the waveform of the test pattern signal supplied from the functional test unit 106A to 106N to the IC under test 300 is not disturbed by the connection of the DC test apparatus 200. . In other words, even if the DC test apparatus 200 is kept connected to any of the ICs 300 under test even during the functional test, the test signal applied to the terminal to which the DC test apparatus 200 is connected is not changed. The waveform of the one signal is not disturbed, and the function test can be executed normally.
  • a DC test (leak test) is performed while the function test units 106A to 106N are still connected to the respective terminals of the IC under test 300 during the execution of the function test. It suggests a way to do it.
  • a method is proposed in which the leakage current flowing through the terminal of the device under test C 300 is measured without controlling the switches S 1 ,.
  • the method is that the DC test equipment 200 is connected to the terminal at which the leakage current is to be measured at the timing when a predetermined voltage (voltage that gives ⁇ logic or L logic) is applied to that terminal.
  • the state of the output of the driver 12 of the test unit is controlled to the high impedance mode, and while the driver 12 is controlled to the high impedance mode, the DC test apparatus 200 is operated by the IC under test 300. Measure the leakage current flowing to the 0 terminal.
  • the main controller MAI ⁇ ⁇ ⁇ gives a command signal to the DC test equipment 200 to generate the specified voltage ( ⁇ logic or L logic) during the function test.
  • a digital signal value for generating a predetermined voltage is given to the DA converter 17.
  • the D ⁇ converter 17 converts the digital value to DA, outputs a voltage V i ⁇ or V H, and supplies the voltage VL or V H to the non-inverting input terminal of the operational amplifier 16 constituting the DC test apparatus 200.
  • VH the voltage
  • the operational amplifier 16 is configured so that the voltage of the voltage detection terminal T v is applied to the non-inverting input terminal. Operate to be equal to As a result, a voltage equal to the voltage VL or VH given from the DA converter 17 is generated at the voltage detection terminal T v, and this voltage is applied to the sensing point SEN through the second switch S 2 and the resistor R 4. given, is supplied to the DUT IC 3 0 0 terminal through one of the switching sweep rate Tutsi S 2 1 ⁇ S 2 n.
  • the timing for the DC test is set in advance as shown in Fig. 2A.
  • the time required for the DC test is set, and the driver connected to all the drivers 12 of the function test units 106 A to 106 N or the terminals to be used for the DC test at the timing of the DC test Generates a control signal HIP for controlling 1 2 to high impedance mode (see Fig. 2D), controls driver 12 to high impedance state, and instructs DC test equipment 200 to generate voltage.
  • Control can be performed such that a predetermined voltage is generated from 200 and the leak current is measured in a state where the voltage is applied.
  • the timing immediately after the test pattern signal is written to the IC under test 300 can be set.
  • a resistor R1 having a high resistance value (about 100) for measuring a small current (leakage current) and a small resistance value (1) for measuring a large current (output current of the IC 300 under test) are used.
  • the resistor R 2 with a resistance of about 0 ⁇ is connected in series and the range switching switch S faced in Fig. 5 is omitted.
  • D1 and D2 are connected in parallel.When measuring a large current, these diodes D1 and D2 are turned on, and a large current is bypassed to the diode D1 or D2.
  • the leakage current flowing through the terminal of the IC under test 300 can be measured. That is, the voltage generated in the resistor R 1 is taken out by subtraction circuit 1 8 A, applied to the AD varying equipment 1 9 The retrieved voltage through sweep rate pitch S 4, the AD conversion by the AD converter 1 9 Then, the signal is input to the main controller MA IN and compared with the reference value to judge pass / fail.
  • the switches S to S1 ⁇ are controlled to be off, and the function test apparatus 100 is controlled by the IC 300 under test. Is disconnected from the DC test apparatus 200 and only the DC test apparatus 200 is connected to the IC under test 300. In the DC test apparatus 200, the first switch S1 is turned off, and the second and third switches are turned off. With the switches S 2 and S 3 on, switch S 4 off, and switch S 5 on, a DC test is performed.
  • the driver in the middle of the function test DC test by controlling 1 2 to high impedance mode (Leak test)
  • the function test is performed by adding the net time required for the DC test (not including the time required for switch switching) to the time required for the functional test. Can be terminated.
  • This has the advantage of significantly reducing the overall test time. As a result, the effect is exhibited when, for example, a large number of ICs must be tested in a short time in an IC manufacturer.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Cette invention concerne un dispositif de test de circuits intégrés qui permet d'effectuer un test des fonctions ainsi qu'un test du CC. Une résistance de forte valeur est connectée au côté sortie du dispositif de test de CC de sorte que le dispositif de test des fonctions puisse fonctionner normalement même lorsque ledit dispositif de test de CC est connecté au dispositif de test des fonctions. Un test des fonctions et un test du CC peuvent ainsi être effectués en parallèle en réalisant de force le test du CC lors de la conduite du test des fonctions. De plus, le temps de commutation d'un commutateur ne s'ajoute pas à la durée du test lorsque l'on exécute des commandes prenant du temps sur le dispositif de test du CC, comme la commutation du commutateur lors du test des fonctions, ce qui permet de réduire la durée du test.
PCT/JP1997/004228 1997-11-20 1997-11-20 Procede de test de circuits integres et appareil de test de circuits integres utilisant ce procede WO1999027376A1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US09/319,898 US6404220B1 (en) 1997-11-20 1997-11-20 IC testing method and IC testing device using the same
DE19782244T DE19782244T1 (de) 1997-11-20 1997-11-20 IC-Testverfahren und unter Anwendung dieses IC-Testverfahrens arbeitendes IC-Testgerät
JP52143599A JP3426254B2 (ja) 1997-11-20 1997-11-20 Ｉｃ試験方法及びこの試験方法を用いたｉｃ試験装置
CNB971814333A CN1141593C (zh) 1997-11-20 1997-11-20 集成电路测试方法和采用该测试方法的集成电路测试装置
GB9912919A GB2335280B (en) 1997-11-20 1997-11-20 Ic testing method and ic testing device using the same
PCT/JP1997/004228 WO1999027376A1 (fr) 1997-11-20 1997-11-20 Procede de test de circuits integres et appareil de test de circuits integres utilisant ce procede
TW086118710A TW356526B (en) 1997-11-20 1997-12-11 An IC testing method and IC testing device using the same method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CNB971814333A CN1141593C (zh) 1997-11-20 1997-11-20 集成电路测试方法和采用该测试方法的集成电路测试装置
PCT/JP1997/004228 WO1999027376A1 (fr) 1997-11-20 1997-11-20 Procede de test de circuits integres et appareil de test de circuits integres utilisant ce procede

Publications (1)

Publication Number Publication Date
WO1999027376A1 true WO1999027376A1 (fr) 1999-06-03

Family

ID=25744427

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1997/004228 WO1999027376A1 (fr) 1997-11-20 1997-11-20 Procede de test de circuits integres et appareil de test de circuits integres utilisant ce procede

Country Status (4)

Country Link
CN (1) CN1141593C (fr)
DE (1) DE19782244T1 (fr)
GB (1) GB2335280B (fr)
WO (1) WO1999027376A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102609A (ja) * 1999-09-28 2001-04-13 Kanegafuchi Chem Ind Co Ltd 光電変換装置の特性測定装置
JP2003098234A (ja) * 2001-09-27 2003-04-03 Advantest Corp 半導体試験装置
WO2007007658A1 (fr) * 2005-07-07 2007-01-18 Advantest Corporation Appareil d'essai
WO2011132225A1 (fr) * 2010-04-22 2011-10-27 株式会社アドバンテスト Carte à broches et dispositif de test l'utilisant

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT412242B (de) * 2000-03-02 2004-11-25 Siemens Ag Oesterreich Verfahren und anordnung zum testen eines prüflings
DE112006003430T5 (de) * 2005-12-15 2008-10-02 Advantest Corp. Prüfvorrichtung und Stiftelektronikkarte
JP4726679B2 (ja) * 2006-03-31 2011-07-20 ルネサスエレクトロニクス株式会社 半導体試験方法および半導体装置
KR101184312B1 (ko) 2007-05-14 2012-09-21 가부시키가이샤 어드밴티스트 시험 장치
CN101995534B (zh) * 2009-08-10 2013-08-28 宏正自动科技股份有限公司 漏电检测装置及方法
CN102540055B (zh) * 2011-12-22 2015-07-29 深圳创维数字技术有限公司 一种检测逻辑电平极限值的方法及装置
US9448274B2 (en) * 2014-04-16 2016-09-20 Teradyne, Inc. Circuitry to protect a test instrument
CN105044536B (zh) * 2015-03-20 2018-11-13 深圳康姆科技有限公司 一种新型的封装缺陷检测方法和***

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923676U (ja) * 1982-08-04 1984-02-14 株式会社アドバンテスト 自己診断機能を持つｉｃ試験装置
JPS6329277A (ja) * 1986-07-23 1988-02-06 Nec Corp 論理集積回路の試験装置
JPS63190975U (fr) * 1987-05-29 1988-12-08

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923676U (ja) * 1982-08-04 1984-02-14 株式会社アドバンテスト 自己診断機能を持つｉｃ試験装置
JPS6329277A (ja) * 1986-07-23 1988-02-06 Nec Corp 論理集積回路の試験装置
JPS63190975U (fr) * 1987-05-29 1988-12-08

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102609A (ja) * 1999-09-28 2001-04-13 Kanegafuchi Chem Ind Co Ltd 光電変換装置の特性測定装置
JP2003098234A (ja) * 2001-09-27 2003-04-03 Advantest Corp 半導体試験装置
JP4729212B2 (ja) * 2001-09-27 2011-07-20 株式会社アドバンテスト 半導体試験装置
WO2007007658A1 (fr) * 2005-07-07 2007-01-18 Advantest Corporation Appareil d'essai
US7679372B2 (en) 2005-07-07 2010-03-16 Advantest Corporation Test apparatus
KR100989588B1 (ko) 2005-07-07 2010-10-25 가부시키가이샤 어드밴티스트 시험 장치
JP5087398B2 (ja) * 2005-07-07 2012-12-05 株式会社アドバンテスト 試験装置及びデバイスインターフェイス装置
WO2011132225A1 (fr) * 2010-04-22 2011-10-27 株式会社アドバンテスト Carte à broches et dispositif de test l'utilisant
US8547124B2 (en) 2010-04-22 2013-10-01 Advantest Corporation Pin card
JP5629680B2 (ja) * 2010-04-22 2014-11-26 株式会社アドバンテスト ピンカードおよびそれを用いた試験装置

Also Published As

Publication number Publication date
GB2335280B (en) 2002-01-16
CN1141593C (zh) 2004-03-10
GB2335280A (en) 1999-09-15
DE19782244T1 (de) 2000-01-05
GB9912919D0 (en) 1999-08-04
CN1244925A (zh) 2000-02-16

Similar Documents

Publication Publication Date Title
US7797591B2 (en) Semiconductor integrated circuit, design support software system, and automatic test pattern generation system
US7859268B2 (en) Method of testing driving circuit and driving circuit for display device
US6404220B1 (en) IC testing method and IC testing device using the same
US7427870B2 (en) Test system for testing integrated circuits and a method for configuring a test system
WO1999027376A1 (fr) Procede de test de circuits integres et appareil de test de circuits integres utilisant ce procede
US5554941A (en) Self-testing method for irregular CMOS switching structures with high defect detection
US7317324B2 (en) Semiconductor integrated circuit testing device and method
KR100561557B1 (ko) 누설 전류 보상회로를 구비하는 테스터 모듈, 집적회로 테스터 및 그 조작 방법
US11587634B2 (en) Integrated circuit test apparatus
CN101646954B (zh) 测试装置及电子器件
US7409615B2 (en) Test apparatus and test method
US6744271B2 (en) Internal generation of reference voltage
US20030030446A1 (en) Method for providing compensation current and test device using the same
KR100363936B1 (ko) Ｉｃ 시험방법 및 이 시험방법을 이용한 ｉｃ 시험장치
JP3426254B2 (ja) Ｉｃ試験方法及びこの試験方法を用いたｉｃ試験装置
US6393593B1 (en) Tester and method for testing LSI designed for scan method
JP4314096B2 (ja) 半導体集積回路検査装置および半導体集積回路検査方法
JP4061533B2 (ja) Ｉｃテスタ
CN112666379A (zh) 在线电源电流监测
JP2010002315A (ja) 半導体試験装置とそのｄｃ特性試験方法
JP3353288B2 (ja) Ｌｓｉ試験装置
JP4173229B2 (ja) Ｉｃ試験装置
JP3553509B2 (ja) 半導体集積回路及びその検査方法
US6396256B1 (en) Power supply slew time testing of electronic circuits
JP3089193B2 (ja) Ｉｃ試験装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 97181433.3

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): CN DE GB JP KR US

ENP Entry into the national phase

Ref document number: 9912919

Country of ref document: GB

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 09319898

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 1019997006281

Country of ref document: KR

RET De translation (de og part 6b)

Ref document number: 19782244

Country of ref document: DE

Date of ref document: 20000105

WWE Wipo information: entry into national phase

Ref document number: 19782244

Country of ref document: DE

WWP Wipo information: published in national office

Ref document number: 1019997006281

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1019997006281

Country of ref document: KR