WO1999027376A1 - Ic testing method and ic testing device using the same - Google Patents

Ic testing method and ic testing device using the same Download PDF

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Publication number
WO1999027376A1
WO1999027376A1 PCT/JP1997/004228 JP9704228W WO9927376A1 WO 1999027376 A1 WO1999027376 A1 WO 1999027376A1 JP 9704228 W JP9704228 W JP 9704228W WO 9927376 A1 WO9927376 A1 WO 9927376A1
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WO
WIPO (PCT)
Prior art keywords
test
terminal
voltage
under test
switch
Prior art date
Application number
PCT/JP1997/004228
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French (fr)
Japanese (ja)
Inventor
Yoshihiro Hashimoto
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to GB9912919A priority Critical patent/GB2335280B/en
Priority to PCT/JP1997/004228 priority patent/WO1999027376A1/en
Priority to JP52143599A priority patent/JP3426254B2/en
Priority to CNB971814333A priority patent/CN1141593C/en
Priority to DE19782244T priority patent/DE19782244T1/en
Priority to US09/319,898 priority patent/US6404220B1/en
Priority to TW086118710A priority patent/TW356526B/en
Publication of WO1999027376A1 publication Critical patent/WO1999027376A1/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test

Definitions

  • the present invention when performing a functional test and a DC test of a semiconductor device such as a memory configured by a semiconductor integrated circuit, a leak test of the items of the functional test and the DC test is performed in a short time.
  • the present invention relates to an IC test method capable of performing the above-mentioned steps and an IC test apparatus using the method.
  • the C tester uses a functional test to ask whether the semiconductor device functions properly.
  • a DC test is performed to determine whether or not the IC has an IC, and ICs that are determined to be normal in both tests are determined to be non-defective.
  • Fig. 3 shows the schematic configuration of the IC test equipment.
  • TES indicates the reference numeral assigned to the entire IC test apparatus.
  • the inside of the 1C test equipment TES is roughly divided into a main controller MAIN, a functional test equipment 100, and a DC test equipment 200.
  • the main controller MAIN is constituted by a computer system, and controls the function test apparatus 100 and the DC test apparatus 200 through the bus line BUS.
  • the function test apparatus 100 is composed of a pattern generator 102, an evening generator 104 and a function test unit 106, 106, 106, 106. Be composed.
  • Functional test Yuni' DOO 1 0 6 ⁇ 1 0 6 ⁇ provided corresponding to each terminal of the DUT IC 3 0 0, sweep rate pitch SM ⁇ S ln ON, functional test and off control Yuni' sheet 1 0 It is configured so that 6 A-106 N can be controlled to be connected to each terminal of the DUT under test C 300 and to be disconnected.
  • the switch S ⁇ Sh is turned on, the function test unit 106 A to 100 ⁇ is connected to each terminal of the IC 300 under test, and IC 30 A test pattern signal is applied to each terminal of 0 to execute a function test.
  • one to several DC test devices 200 are provided for the terminal of the IC 300 under test (the example in FIG. 3 shows a case where one DC test device 200 is prepared). sequentially connecting the DC test device 0 0 by controlling to turn on the switching sweep rate Tutsi S 2 1 ⁇ S sequentially one by one for each terminal of the DUT IC 3 0 0, sequential testing DC characteristics of the identified terminal Configuration.
  • 4 0 0 indicates these sweep rate pitch 3, 1-3 1 "and 3 2 1 controller for controlling to 3 2 n.
  • Fig. 4 shows the internal configuration of one of the functional test units 106 ⁇ , and outlines the functional test.
  • the function test unit 106 A (which has the same configuration as other function test units) has a waveform formatter i 1, a driver 12, a voltage comparator 13, a logic comparator 14, and a failure analysis memory i 5 It is constituted by and.
  • the waveform window 11 receives the test pattern data supplied from the pattern generator 102 and generates a test pattern signal having an actual waveform.
  • the timing generator 104 supplies the waveform formatter # 1 with a timing signal that defines the rising timing and the falling timing of the test pattern signal.
  • the test pattern signal output from the waveform format 11 is shaped into a waveform having an amplitude having a predetermined logical value by the driver 12 and the IC under test 30 is switched through the switches S,,. 0 is supplied to a predetermined terminal, and the data is stored in the IC under test 300.
  • this terminal is an I / O terminal (input / output terminal)
  • each terminal of the IC under test 300 is controlled to the input mode, and the write operation is completed.
  • the mode is switched to the output mode at the point in time.
  • the contents stored in the IC under test 300 are read out at the timing when the mode is switched to the output mode, and input to the logic comparator 14 via the voltage comparator 13.
  • the output terminal of the driver 12 is set to the high impedance mode. Then, a comparison is made as to whether the logic of the signal read from the IC under test 300 maintains a normal voltage value. In other words, it is determined whether the L delirium and the H logic have, for example, 0.8 volts or less and 2.4 volts or more, and the power of a normal logic value is determined. If there is a voltage, the logical value is input to the logical comparator 14.
  • the logical comparator 14 receives the expected value from the pattern generator 102 and compares the expected value with the logical value input from the voltage comparator 13 to detect the occurrence of a mismatch. If a mismatch occurs, it is determined that there is a defect in the memory cell of the written address and stored in that address of the defect analysis memory 15, and the number of defective cells is counted from the defect analysis memory 15 after the test is completed. Read and count to determine if relief is possible.
  • FIG. 5 shows an example of the configuration of the DC test apparatus 200. The illustrated configuration shows a configuration in which the DC test apparatus 200 operates in the voltage applied current measurement mode. To the non-inverting input terminal of the operational amplifier 16, a voltage or V H having a logical value to be supplied from the DA converter 17 to the terminal of the IC under test 300 is applied.
  • the switch S b connected in parallel with the current detection resistor R 1 is a range switch for switching the current measurement range.
  • the sweep rate Tsu resistance by controlling to turn on the switch S B is small ie, connect a resistor R 2 to measure a large current (current at the output mode one de the tested IC 3 0 0), the large current measurement Switch to range.
  • the operational amplifier 16 since the operational amplifier 16 operates so that the voltage at the non-inverting input terminal and the voltage at the inverting input terminal become equal, if, for example, VL is applied to the non-inverting input terminal of the operational amplifier 16, the voltage (voltage (Same as the voltage of the detection terminal T v). Therefore, the voltage or V is applied to the IC Is given.
  • each terminal P i of the IC under test 300 is set to the input mode shown in FIG.
  • the terminal P is connected to the terminal P i by measuring the current flowing through the current detection resistor R 1 with V L (voltage giving L logic) or V U (voltage giving H logic) applied.
  • the respective leakage currents I and I k 2 of the active device can be measured.
  • Reference numeral 18 denotes a subtraction circuit for extracting the voltage generated in the current detection resistor R i
  • reference numeral 19 denotes an AD converter that AD-converts the voltage obtained by the subtraction circuit 18 and outputs a digital value. Is shown.
  • the switching switch S b When measuring the leak currents I Rekl and I described above, the switching switch S b is turned off, and is generated in the current detection resistor R 1 having a relatively high resistance value of about 100 k ⁇ . that the voltage is measured, and measuring the re one leakage current I Kek l and I Rek ;! flowing to the input terminals of the DUT IC 3 0 0.
  • the protective resistor R 3 is constituted by a resistor ratio ⁇ a small resistance value (about several 1 0 Omega) resistance, as Suitsuchi S al and S 2 during production is controlled to be turned off at the same time This is also a resistor for securing a closed feedback loop for the inverting input terminal of the operational amplifier 16 and protecting the operational amplifier 16 so that the operation of the operational amplifier 16 does not reach a saturation state.
  • the DC test apparatus 200 is disconnected from the terminal of the IC under test 300, and the switches S, ,, ⁇ S, and n are all controlled to the on state.
  • a test is performed. That is, since the output impedance of the DC test apparatus 200 is relatively low, on the order of several ⁇ , it is assumed that the DC test apparatus 200 is electrically connected as a load of the functional test apparatus 100 during the function test. , Functional test equipment 100 to IC under test The waveform of the test pattern signal supplied to 300 is degraded, which causes a problem that a normal function test cannot be performed.
  • an initialization pattern for setting the mode of that terminal to the input mode is used as the function test equipment 100 Enter from.
  • the terminals to be tested for DC are set to the input mode, disconnect all the functional test units 106 to ⁇ from the terminals to be tested for DC from terminals of IC 300 under test. Perform control.
  • the DC test measures the leakage currents I and I Rek2 (see Fig. 6) flowing through the terminals when the logic values of H logic and L logic are given to the terminals of the IC under test 300, respectively. If the peak current value is less than the expected value, it is determined to be good.
  • An object of the present invention is to propose an IC test method capable of shortening the Ic test time and testing a large number of ICs in a short time, and an IC test apparatus using this test method. Disclosure of the invention
  • the DC test apparatus is connected to the terminal of the IC under test via a resistor, and the connection of the resistor is devised so that the DC test apparatus does not become a large load as viewed from the functional test apparatus.
  • the feature is that the DC test equipment can be kept connected to the terminal of the IC under test even during the functional test.
  • the DC test can be executed by controlling the output terminal of the driver of the functional test device to the high-impedance mode even during the functional test, and the switch for disconnecting the functional test device even during the DC test is executed. It proposes an IC test method that eliminates the need for control and executes the leak test in the DC test items during the function test.
  • the leak test of the DC test item is completed at the same time as the completion of the functional test, and the leak test does not need to be performed with a special time. As a result, there is an advantage that the time required for the test can be significantly reduced.
  • the present invention further proposes an IC test apparatus using the above-described IC test method.
  • the IC test apparatus is a functional test that applies a test pattern signal to each terminal of an IC under test by a driver capable of setting the state of an output terminal to a high impedance mode, and executes a 1C functional test under test.
  • a DC test device for measuring a leak current flowing through each terminal of the IC under test while a predetermined voltage is applied to each terminal of the IC under test;
  • a resistor connected between the sensing point of the DC tester and the terminal of the IC under test;
  • First control means for outputting a predetermined voltage to a sensing point of the DC test apparatus while the function test apparatus is performing the function test;
  • Second control means for controlling the output terminal of the driver of the functional test device to a high impedance mode when the control operation of the first control means is completed;
  • the DC test can be executed during the execution of the function test without passing through the time required for switching the switch.
  • FIG. 1 is a block diagram showing an embodiment of an IC test apparatus ffl employing the IC test method according to the present invention.
  • FIG. 2 is a timing chart for explaining the IC test method according to the present invention.
  • FIG. 3 is a block diagram for explaining the outline of a conventional IC test apparatus.
  • FIG. 4 is a block diagram for explaining a configuration of a functional test device used in the IC test device shown in FIG.
  • FIG. 5 is a connection diagram for explaining the configuration of a DC test device used in the IC test device shown in FIG.
  • Fig. 6 is a connection diagram explaining the state of the IC terminals under test when performing a leak test in the DC test items.
  • Figure 6 shows a timing chart for explaining the state of a conventional DC test.
  • FIG. 1 shows an embodiment of an IC test apparatus for testing an IC under test 300 according to the IC test method proposed in the present invention.
  • 100 is a functional test device
  • 200 is a DC test device, which is the same configuration as that described in FIG.
  • the switches S i, to S ln are all turned on, and all the functional test units 106 A to 106 N are connected to the IC under test 300. It is executed by connecting to each terminal.
  • the DC test apparatus 200 controls the switching switches S i S ⁇ one by one sequentially in an on state, selectively connects the DC test apparatus 200 to each terminal of the IC under test 300, Perform a DC test for each terminal one by one.
  • a plurality of DC test devices 200 are provided, and the number of terminals for the test is reduced so that the DC test can be completed in a short time. The description will be made assuming that the DC test apparatus 200 executes the test.
  • a feature of the IC test apparatus according to the present invention is that in the DC test apparatus 200, a resistor R4 is connected in series with the switch S2 between the voltage detection terminal Tv and the sensing point S ⁇ .
  • the second switch S1 is connected in parallel to the protection resistor R3 connected between the current output terminal and the voltage detection terminal ⁇ , and the voltage detection terminal ⁇
  • the second switch S 2 and the resistor R 4 are connected in series between the point S ⁇ ⁇ .
  • a third switch S3 is connected between the current output terminal and the sensing point S ⁇ .
  • the impedance when the DC test apparatus 200 is viewed from the functional test unit to which the DC test apparatus 200 is connected can be viewed as the resistance value of the resistor R4.
  • the resistance value of resistor R4 By selecting the resistance value of resistor R4 to be about 10 k ⁇ , the impedance of DC test apparatus 200 as viewed from functional test unit 106 A to 106 N is about 1 O k Q It can be seen as
  • the transmission line is generally matched to a characteristic impedance of 50 ⁇ . Therefore, even if a load of 100 k ⁇ (DC test equipment 200) is connected to each output side of the functional test unit 106 A to 106 N, the impedance of the line fluctuates significantly. And the waveform of the test pattern signal supplied from the functional test unit 106A to 106N to the IC under test 300 is not disturbed by the connection of the DC test apparatus 200. . In other words, even if the DC test apparatus 200 is kept connected to any of the ICs 300 under test even during the functional test, the test signal applied to the terminal to which the DC test apparatus 200 is connected is not changed. The waveform of the one signal is not disturbed, and the function test can be executed normally.
  • a DC test (leak test) is performed while the function test units 106A to 106N are still connected to the respective terminals of the IC under test 300 during the execution of the function test. It suggests a way to do it.
  • a method is proposed in which the leakage current flowing through the terminal of the device under test C 300 is measured without controlling the switches S 1 ,.
  • the method is that the DC test equipment 200 is connected to the terminal at which the leakage current is to be measured at the timing when a predetermined voltage (voltage that gives ⁇ logic or L logic) is applied to that terminal.
  • the state of the output of the driver 12 of the test unit is controlled to the high impedance mode, and while the driver 12 is controlled to the high impedance mode, the DC test apparatus 200 is operated by the IC under test 300. Measure the leakage current flowing to the 0 terminal.
  • the main controller MAI ⁇ ⁇ ⁇ gives a command signal to the DC test equipment 200 to generate the specified voltage ( ⁇ logic or L logic) during the function test.
  • a digital signal value for generating a predetermined voltage is given to the DA converter 17.
  • the D ⁇ converter 17 converts the digital value to DA, outputs a voltage V i ⁇ or V H, and supplies the voltage VL or V H to the non-inverting input terminal of the operational amplifier 16 constituting the DC test apparatus 200.
  • VH the voltage
  • the operational amplifier 16 is configured so that the voltage of the voltage detection terminal T v is applied to the non-inverting input terminal. Operate to be equal to As a result, a voltage equal to the voltage VL or VH given from the DA converter 17 is generated at the voltage detection terminal T v, and this voltage is applied to the sensing point SEN through the second switch S 2 and the resistor R 4. given, is supplied to the DUT IC 3 0 0 terminal through one of the switching sweep rate Tutsi S 2 1 ⁇ S 2 n.
  • the timing for the DC test is set in advance as shown in Fig. 2A.
  • the time required for the DC test is set, and the driver connected to all the drivers 12 of the function test units 106 A to 106 N or the terminals to be used for the DC test at the timing of the DC test Generates a control signal HIP for controlling 1 2 to high impedance mode (see Fig. 2D), controls driver 12 to high impedance state, and instructs DC test equipment 200 to generate voltage.
  • Control can be performed such that a predetermined voltage is generated from 200 and the leak current is measured in a state where the voltage is applied.
  • the timing immediately after the test pattern signal is written to the IC under test 300 can be set.
  • a resistor R1 having a high resistance value (about 100) for measuring a small current (leakage current) and a small resistance value (1) for measuring a large current (output current of the IC 300 under test) are used.
  • the resistor R 2 with a resistance of about 0 ⁇ is connected in series and the range switching switch S faced in Fig. 5 is omitted.
  • D1 and D2 are connected in parallel.When measuring a large current, these diodes D1 and D2 are turned on, and a large current is bypassed to the diode D1 or D2.
  • the leakage current flowing through the terminal of the IC under test 300 can be measured. That is, the voltage generated in the resistor R 1 is taken out by subtraction circuit 1 8 A, applied to the AD varying equipment 1 9 The retrieved voltage through sweep rate pitch S 4, the AD conversion by the AD converter 1 9 Then, the signal is input to the main controller MA IN and compared with the reference value to judge pass / fail.
  • the switches S to S1 ⁇ are controlled to be off, and the function test apparatus 100 is controlled by the IC 300 under test. Is disconnected from the DC test apparatus 200 and only the DC test apparatus 200 is connected to the IC under test 300. In the DC test apparatus 200, the first switch S1 is turned off, and the second and third switches are turned off. With the switches S 2 and S 3 on, switch S 4 off, and switch S 5 on, a DC test is performed.
  • the driver in the middle of the function test DC test by controlling 1 2 to high impedance mode (Leak test)
  • the function test is performed by adding the net time required for the DC test (not including the time required for switch switching) to the time required for the functional test. Can be terminated.
  • This has the advantage of significantly reducing the overall test time. As a result, the effect is exhibited when, for example, a large number of ICs must be tested in a short time in an IC manufacturer.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

An IC testing device which performs a function test and a DC test. A high-resistance resistor is connected to the output side of a DC testing device so that a function testing device can operate normally even when the DC testing device is connected to the function testing device. Thus a function test and a DC test are conducted in parallel by forcedly performing the DC test during the execution of the function test, and the switching time of a switch is not added to the testing time by executing time-consuming controls on the DC testing device such as the switching of the switch during the function test, thereby shortening the testing time.

Description

明 細 書  Specification
I C試験方法及びこの試験方法を用いた I C試験装置 技術分野 IC test method and IC test equipment using this test method
この発明は、 半導体集積回路で構成されるメモリ のような半導体ディバイ スの 機能試験と直流試験を行なう場合に、 短時間に機能試験と直流試験の項目のリ― クテス 卜を短時間に行なうことができる I C試験方法と、 この方法を用いた I C 試験装置に関する。 背景技術  According to the present invention, when performing a functional test and a DC test of a semiconductor device such as a memory configured by a semiconductor integrated circuit, a leak test of the items of the functional test and the DC test is performed in a short time. The present invention relates to an IC test method capable of performing the above-mentioned steps and an IC test apparatus using the method. Background art
従来より、 メモリのような半導体ディバイスを試験する 【 C試験装置では、 半 導体ディバィスの機能が正常に動作するか否かを問う機能試験と、 半導体ディバ イスの各端子が予定している直流特性を持っているか否かを問う直流試験とを実 行し、 双方の試験で正常と判定された I Cを良品と判定している。  Conventionally, semiconductor devices such as memories have been tested. [The C tester uses a functional test to ask whether the semiconductor device functions properly. A DC test is performed to determine whether or not the IC has an IC, and ICs that are determined to be normal in both tests are determined to be non-defective.
第 3図に I C試験装置の概略の構成を示す。 図中 T E Sは I C試験装置の全体 に付した符号を示す。 1 C試験装置 T E Sの内部は大きく分けて主制御器 M A I Nと、 機能試験装置 1 0 0と直流試験装置 2 0 0に分類される。  Fig. 3 shows the schematic configuration of the IC test equipment. In the figure, TES indicates the reference numeral assigned to the entire IC test apparatus. The inside of the 1C test equipment TES is roughly divided into a main controller MAIN, a functional test equipment 100, and a DC test equipment 200.
主制御器 M A I Nはコンピュータシステムによって構成され、 バスライ ン BU Sを通じて機能試験装置 1 0 0と直流試験装置 2 0 0を制御する。 機能試験装置 1 0 0はパターン発生器 1 0 2と、 夕イ ミ ング発生器 1 0 4と機能試験ュニッ 卜 1 0 6 Α、 1 0 6 Β · · · · 1 0 6 Νとによつて構成される。  The main controller MAIN is constituted by a computer system, and controls the function test apparatus 100 and the DC test apparatus 200 through the bus line BUS. The function test apparatus 100 is composed of a pattern generator 102, an evening generator 104 and a function test unit 106, 106, 106, 106. Be composed.
機能試験ュニッ ト 1 0 6 Α〜 1 0 6 Νは被試験 I C 3 0 0の各端子に対応して 設けられ、 スィ ッチ S M〜Slnをオン、 オフ制御して機能試験ュニッ ト 1 0 6 A - 1 0 6 Nを被試験〗 C 3 0 0の各端子に接続した状態と、 切離した状態に制御 できる構成とされる。 Functional test Yuni' DOO 1 0 6 Α~ 1 0 6 Ν provided corresponding to each terminal of the DUT IC 3 0 0, sweep rate pitch SM～S ln ON, functional test and off control Yuni' sheet 1 0 It is configured so that 6 A-106 N can be controlled to be connected to each terminal of the DUT under test C 300 and to be disconnected.
つまり、 機能試験はスィ ツチ S ^ S hをオンの状態に制御して機能試験ュニ ッ ト 1 0 6 A〜 1 0 ΰ Νを被試験 I C 3 0 0の各端子に接続し、 被試験 I C 3 0 0の各端子に試験パターン信号を与え機能試験を実行する。 In other words, in the function test, the switch S ^ Sh is turned on, the function test unit 106 A to 100 ΰ is connected to each terminal of the IC 300 under test, and IC 30 A test pattern signal is applied to each terminal of 0 to execute a function test.
一方直流試験装置 2 0 0は被試験 I C 3 0 0の端子に対して 1台乃至数台 （第 3図の例では直流試験装置 2 0 0を 1台用意した場合を示す） が用意され、 切替 スィ ツチ S 2 1〜 S を順次 1個ずつオンに制御することにより直流試験装置 0 0を被試験 I C 3 0 0の各端子に順次接続し、 この特定した端子の直流特性を順 次試験する構成とされる。 尚、 4 0 0はこれらスィ ッチ 3 , 1〜3 1„及び3 2 1〜3 2 nを制御する制御器を示す。 On the other hand, one to several DC test devices 200 are provided for the terminal of the IC 300 under test (the example in FIG. 3 shows a case where one DC test device 200 is prepared). sequentially connecting the DC test device 0 0 by controlling to turn on the switching sweep rate Tutsi S 2 1 ~ S sequentially one by one for each terminal of the DUT IC 3 0 0, sequential testing DC characteristics of the identified terminal Configuration. Incidentally, 4 0 0 indicates these sweep rate pitch 3, 1-3 1 "and 3 2 1 controller for controlling to 3 2 n.
第 4図に機能試験ュニッ 卜の- つ 1 0 6 Λの内部構成を示し、 機能試験の概要 を説明する。 機能試験ュニッ ト 1 0 6 A (他の機能試験ュニッ 卜も同じ構成とさ れる） は波形フォーマッタ i 1 と、 ドライバ 1 2、 電圧比較器 1 3、 論理比較器 1 4、 不良解析メモリ i 5とによって構成される。  Fig. 4 shows the internal configuration of one of the functional test units 106Λ, and outlines the functional test. The function test unit 106 A (which has the same configuration as other function test units) has a waveform formatter i 1, a driver 12, a voltage comparator 13, a logic comparator 14, and a failure analysis memory i 5 It is constituted by and.
波形フォ一マツ夕 1 1 はパ夕一ン発生器 1 0 2から与えられる試験パターンデ —夕を受けて実波形を持つ試験パターン信号を生成する。 タイ ミ ング発生器 1 0 4は波形フォ一マッタ 〗 1 に対して試験パターン信号の立上りのタイ ミ ングと立 下りのタイ ミ ングを規定するタイ ミ ング信号を与える。  The waveform window 11 receives the test pattern data supplied from the pattern generator 102 and generates a test pattern signal having an actual waveform. The timing generator 104 supplies the waveform formatter # 1 with a timing signal that defines the rising timing and the falling timing of the test pattern signal.
波形フォ一マツ夕 1 1から出力された試験パ夕一ン信号はドラィバ 1 2 によつ て所定の論理値を持つ振幅の波形に整形され、 スィ ッチ S , ,を通じて被試験 I C 3 0 0の所定の端子に供給され、 被試験 I C 3 0 0にデータが記憶される。 ここ でこの端子が I / O端子 （入力兼出力端子） の場合は試験パターン信号を入力す る場合は被試験 I C 3 0 0の各端子は入力モー ドに制御され、 書込動作が終了し た時点で出力モードに切替られる。 出力モ一ドに切替られたタイ ミ ングで被試験 I C 3 0 0に記憶した内容を読み出し、 電圧比較器 1 3を介して論理比較器 1 4 に入力する。 尚、 電圧比較器 1 3が被試験 I C 3 0 0から出力されるデ一夕を読 み取る際にはドライバ 1 2の出力端子は高インピ一ダンスのモードに設定される 電圧比較器 1 3では被試験 I C 3 0 0から読み出された信号の論理が正規の電 圧値を維持しているかを比較判定する。 つまり L譫理と H論理が例えば 0 . 8ボ ルト以下と 2 . 4ボル卜以上を具備しているか否かを判定し、 正常な論理値の電 圧を持っている場合にその論理値を論理比較器 1 4に入力する。 The test pattern signal output from the waveform format 11 is shaped into a waveform having an amplitude having a predetermined logical value by the driver 12 and the IC under test 30 is switched through the switches S,,. 0 is supplied to a predetermined terminal, and the data is stored in the IC under test 300. Here, when this terminal is an I / O terminal (input / output terminal), when inputting a test pattern signal, each terminal of the IC under test 300 is controlled to the input mode, and the write operation is completed. The mode is switched to the output mode at the point in time. The contents stored in the IC under test 300 are read out at the timing when the mode is switched to the output mode, and input to the logic comparator 14 via the voltage comparator 13. When the voltage comparator 13 reads the data output from the IC under test 300, the output terminal of the driver 12 is set to the high impedance mode. Then, a comparison is made as to whether the logic of the signal read from the IC under test 300 maintains a normal voltage value. In other words, it is determined whether the L delirium and the H logic have, for example, 0.8 volts or less and 2.4 volts or more, and the power of a normal logic value is determined. If there is a voltage, the logical value is input to the logical comparator 14.
論理比較器 1 4ではパターン発生器 1 0 2から期待値が入力され、 この期待値 と電圧比較器 1 3から入力される論理値とを比較し、 不一致の発生を検出する。 不一致が発生した場合は書込んだァドレスのメモリセルに不良が存在するものと して不良解析メモリ 1 5のそのア ドレスに記憶し、 試験終了後に不良セルの数を この不良解析メモリ 1 5から読み出して計数し、 救済が可能か否かを判定する。 第 5図は直流試験装置 2 0 0の構成の一例を示す。 図示する構成は直流試験装 置 2 0 0が電圧印加電流測定モードで動作する場合の構成を示す。 演算増幅器 1 6の非反転入力端子には D A変換器 1 7から被試験 I C 3 0 0の端子に与えるベ き論理値を持つ電圧 又は V H を与える。  The logical comparator 14 receives the expected value from the pattern generator 102 and compares the expected value with the logical value input from the voltage comparator 13 to detect the occurrence of a mismatch. If a mismatch occurs, it is determined that there is a defect in the memory cell of the written address and stored in that address of the defect analysis memory 15, and the number of defective cells is counted from the defect analysis memory 15 after the test is completed. Read and count to determine if relief is possible. FIG. 5 shows an example of the configuration of the DC test apparatus 200. The illustrated configuration shows a configuration in which the DC test apparatus 200 operates in the voltage applied current measurement mode. To the non-inverting input terminal of the operational amplifier 16, a voltage or V H having a logical value to be supplied from the DA converter 17 to the terminal of the IC under test 300 is applied.
演算増幅器 i 6の出力端子と電流出力端子 との間に電流検出用抵抗器 R 1 を接続し、 電流出力端子 Τ ι とセンシング点 S E Nの間にスィ ッチ を接続し 、 電流出力端子 と電圧検出端子 T v との間に保護抵抗器 R 3を接続し、 電圧 検出端子 Τ ν をスィ ッチ S A Lを通じてセンシング点 S E Nに接続する。 センシン グ点 S E Nは切替スィツチ S 2 Iを通じて被試験 I C 3 0 0の端子に接続する。 電 圧検出端子 T V に演算増幅器 1 6の反転入力端子を接続する。 Connect the current detection resistor R 1 between the output terminal of the operational amplifier i 6 and the current output terminal, connect a switch between the current output terminal ιι and the sensing point SEN, and connect the current output terminal and the voltage. connect a protective resistor R 3 between the detection terminal T v, it connects the voltage detection terminal T [nu through sweep rate pitch S AL to the sensing point SEN. Sensing grayed point SEN is connected to a terminal of the switching Suitsuchi S 2 to be tested through the I IC 3 0 0. Voltage Detection connecting the inverting input terminal of the operational amplifier 1 6 to the terminal T V.
尚、 電流検出用抵抗器 R 1 と並列接続したスィ ッチ S b は電流測定レンジを切 替るレンジ切替スィ ッチを示す。 このスィ ッチ S B をオンに制御することにより 抵抗値が小さいつまり、 大電流 （被試験 I C 3 0 0の出力モ一ドにおける電流） を測定する抵抗器 R 2を接続し、 大電流測定レンジに切替る。 The switch S b connected in parallel with the current detection resistor R 1 is a range switch for switching the current measurement range. The sweep rate Tsu resistance by controlling to turn on the switch S B is small ie, connect a resistor R 2 to measure a large current (current at the output mode one de the tested IC 3 0 0), the large current measurement Switch to range.
この直流試験装置 2 0 0の構成によれば、 スィ ッチ S A L , と切替スイ ッチAccording to the configuration of the DC test apparatus 200, the switch S AL , and the switch
S 2 Iをオンの状態に制御することにより、 被試験 I C 3 0 0の端子に、 D A変換 器 1 7から演算増幅器 1 6の非反転入力端子に与えた電圧 V L 又は V H が印加さ れる。 By controlling S 2 I to the ON state, the voltage VL or VH given from the DA converter 17 to the non-inverting input terminal of the operational amplifier 16 is applied to the terminal of the IC under test 300. .
つまり、 演算増幅器 1 6は非反転入力端子と反転入力端子の電圧が等しくなる ように動作するから、 演算増幅器 1 6の非反転入力端子に例えば V L を与えたと すると、 反転入力端子の電圧 （電圧検出端子 T v の電圧と同じ） も となるよ うに出力電圧が制御される。 よって被試験 I C 3 0 0の端子に電圧 または V が与ん れる。 That is, since the operational amplifier 16 operates so that the voltage at the non-inverting input terminal and the voltage at the inverting input terminal become equal, if, for example, VL is applied to the non-inverting input terminal of the operational amplifier 16, the voltage (voltage (Same as the voltage of the detection terminal T v). Therefore, the voltage or V is applied to the IC Is given.
被試験 I C 3 0 0はこの直流試験モ一 ドでは各端子 P i は第 6図に示す入力モ —ドに設定される。 端子 P； に V L ( L論理を与える電圧） 又は VU ( H論理を 与える電圧） を印加した状態で電流検出用抵抗器 R 1 に流れる電流を測定するこ とにより端子 P i に接続された能動素子 と の各リーク電流 I と I k 2を測定することができる。 1 8は電流検出用抵抗器 R i に発生する電圧を取り 出すための引算回路、 1 9はその引算回路 1 8で求めた電圧を A D変換してディ ジタル値を出力する A D変換器を示す。 In this DC test mode, each terminal P i of the IC under test 300 is set to the input mode shown in FIG. The terminal P; is connected to the terminal P i by measuring the current flowing through the current detection resistor R 1 with V L (voltage giving L logic) or V U (voltage giving H logic) applied. The respective leakage currents I and I k 2 of the active device can be measured. Reference numeral 18 denotes a subtraction circuit for extracting the voltage generated in the current detection resistor R i, and reference numeral 19 denotes an AD converter that AD-converts the voltage obtained by the subtraction circuit 18 and outputs a digital value. Is shown.
上述したリーク電流 I Rek l, I を測定する場合には切替スィ ッチ S b はォ フとされ、 比較的抵抗値が高い 1 0 0 k Ω程度の電流検出用抵抗器 R 1 に発生す る電圧を測定し、 被試験 I C 3 0 0の各入力端子に流れるリ一ク電流 I Kek lと I Rek;!を測定する。 尚、 保護抵抗器 R 3は比较的抵抗値が小さい （数 1 0 Ω程度） 抵抗値の抵抗器で構成され、 実動中にスィツチ Sa lと S 2が同時にオフの状態に 制御されたとしても演算増幅器 1 6の反転入力端子に対する閉帰還ループを確保 し、 演算増幅器 1 6が飽和状態に至る動作が生じないように演算増幅器 1 6を保 護するための抵抗器である。 When measuring the leak currents I Rekl and I described above, the switching switch S b is turned off, and is generated in the current detection resistor R 1 having a relatively high resistance value of about 100 kΩ . that the voltage is measured, and measuring the re one leakage current I Kek l and I Rek ;! flowing to the input terminals of the DUT IC 3 0 0. The protective resistor R 3 is constituted by a resistor ratio较的a small resistance value (about several 1 0 Omega) resistance, as Suitsuchi S al and S 2 during production is controlled to be turned off at the same time This is also a resistor for securing a closed feedback loop for the inverting input terminal of the operational amplifier 16 and protecting the operational amplifier 16 so that the operation of the operational amplifier 16 does not reach a saturation state.
以上により I C試験装置における機能試験と直流試験の概要が理解されよう。 ここで従来は上述した機能試験と直流試験は全く異なるタイ ミ ングで実施されて いる。 つまり、 何れか一方の試験を実施した後で他方の試験を実施している。 特 に直流試験では切替スィツチ S21, S 22 - · · · S 2 Dを切替る制御と、 第 3図に 示すスィツチ S u〜S lnを切替る制御を行なう必要がある。 その様子を第 7図を 用いて説明する。 From the above, the outline of the functional test and the DC test in the IC test equipment will be understood. Here, conventionally, the functional test and the DC test described above are performed at completely different timings. In other words, after performing one of the tests, the other test is performed. Switching Suitsuchi S 21 in DC test in JP, S 22 - a control · · · S Ru switched 2 D, it is necessary to Suitsuchi S u~S ln shown in Figure 3 performs the control toggle its. This will be described with reference to FIG.
機能試験を実施する場合には第 3図に示したスィ ツチ S と Sa2及び切替スィ ツチ S2 I〜S 2。を全てオフの状態に切替え、 直流試験装置 2 0 0は被試験 I C 3 0 0の端子から切離され、 、 スィ ッチ S , ,~S ,nが全てォンの状態に制御されて 機能試験が実施される。 つまり、 直流試験装置 2 0 0の出力イ ンピーダンスが数 Ω程度と比較的低いため、 機能試験中に直流試験装置 2 0 0が機能試験装置 1 0 0の負荷として電気的に接続されていると、 機能試験装置 1 0 0から被試験 I C 3 0 0に供給される試験パターン信号の波形を劣化させ、 正常な機能試験を行な うことができない不都合が生じる。 Sweep rate Tutsi S and S a2 and the switching sweep rate shown in FIG. 3 in the case of performing the functional test Tutsi S 2 I to S 2. Are switched off, the DC test apparatus 200 is disconnected from the terminal of the IC under test 300, and the switches S, ,, ~ S, and n are all controlled to the on state. A test is performed. That is, since the output impedance of the DC test apparatus 200 is relatively low, on the order of several Ω, it is assumed that the DC test apparatus 200 is electrically connected as a load of the functional test apparatus 100 during the function test. , Functional test equipment 100 to IC under test The waveform of the test pattern signal supplied to 300 is degraded, which causes a problem that a normal function test cannot be performed.
このため、 切替スィ ツチ S2 l〜S2nの全て、 及びスィ ッチ Sa Sa2をオフの 状態に制御し、 直流試験装置 2 0 0を被試験 I C 3 0 0の何れの端子にも接続さ れていない状態に制御し、 機能試験を実施する。 Therefore, all switching sweep rate Tutsi S 2 l to S 2n, and controls the sweep rate pitch S a S a2 to off, also the DC test device 2 0 0 to any of the terminals of the test IC 3 0 0 Control to a state where it is not connected, and perform a functional test.
一方、 直流試験を実施する場合は、 先ずスィ ッチ S , ,〜 S 1πを全てオンの状態 に制御し、 被試験 I C 3 0 0の全ての端子に機能試験ュニッ ト 1 0 6 A〜 L 0 6 Νを接続する。 この状態で被試験 I C 3 0 0に直流試験を行なうための初期化パ タ一ンを与える。 On the other hand, when the DC test is performed, first, all the switches S ,, to S1π are turned on, and the function test units 106A to L are connected to all the terminals of the IC 300 under test. 0 6 Connect Ν. In this state, an initialization pattern for performing a DC test is given to the IC under test 300.
つまり、 直流試験を行なうべき端子が I /0端子である場合は、 その端子のモ — ドを入力モー ドに設定するための初期化パターン （第 7図 C参照） を機能試験 装置 1 0 0から入力する。 直流試験を行なうべき端子が入力モー ドに設定された 状態で直流試験を行なうべき端子から機能試験ュニッ ト 1 0 6 Α〜】 0 6 Νを全 て被試験 I C 3 0 0の端子から切離す制御を行なう。  In other words, if the terminal on which the DC test is to be performed is the I / 0 terminal, an initialization pattern (see Fig. 7C) for setting the mode of that terminal to the input mode is used as the function test equipment 100 Enter from. With the terminals to be tested for DC are set to the input mode, disconnect all the functional test units 106 to】 from the terminals to be tested for DC from terminals of IC 300 under test. Perform control.
この状態で切替スィ ッチ S2 Iをオンに制御し、 直流試験を実施する。 直流試験 は H論理と L論理の各論理値を被試験 I C 3 0 0の端子に与えた状態で端子に流 れるリ一ク電流 I と I Rek2 (第 6図参照） を測定し、 そのり—ク電流値が予 め予定した値以下であれば良、 以上であれば不良と判定する。 Controlled to turn on the switching sweep rate pitch S 2 I in this state to perform the DC test. The DC test measures the leakage currents I and I Rek2 (see Fig. 6) flowing through the terminals when the logic values of H logic and L logic are given to the terminals of the IC under test 300, respectively. If the peak current value is less than the expected value, it is determined to be good.
このように直流試験を各端子毎に実施するから、 試験すべき端子毎に、 初期化 パターンを与えるためにスィッチ S l l〜S ,Dのオン、 オフ制御する時間 Tswl と 、 切替スィ ッチ S S を切替制御する時間 Tsw2 を加えた時間 Tp i (第 7図 D参照） を必要とする。 初期化パターンを与える時間 TS< と切替スィ ッチ S = 〜S2„を切替制御する時間 Tswi! はスィ ッチ （リ レー） を切替る時間 （数 m s ) に相当し、 電流を測定する時間 TIM (第 7図 E) が短時間であってもこれを加え た時間 Tpiは比較的長い時間となる。 よってこれを全ての端子毎にスィツチ S - S lnと切替スィツチ S S の切替制御を実行すると、 直流試験に要する時 間が長くなる不都合がある。 このために多量の I Cを試験する場合に大きな障害 になつている。 この発明の目的は I cの試験時間を短く し、 短時間に多量の I Cを試験するこ とができる I C試験方法と、 この試験方法を利用した I C試験装置を提案しょう とするものである。 発明の開示 Since the DC test is performed for each terminal in this manner, for each terminal to be tested, a time T swl for controlling the on / off of the switches S ll to S and D to provide an initialization pattern, and a switching switch A time T pi (see Fig. 7D), which is the sum of the time Tsw 2 for switching control of SS, is required. The time T S <for giving the initialization pattern and the time T Swi! For controlling the switching of the switch S = ~ S 2 „correspond to the time (a few ms) for switching the switch ( relay ). Even if the measurement time T IM (Fig. 7E) is short, the added time T pi is a relatively long time, so that the switch S-S ln and the switching switch SS are used for all terminals. When switching control is performed, the time required for DC testing becomes longer, which is a major obstacle when testing a large number of ICs. An object of the present invention is to propose an IC test method capable of shortening the Ic test time and testing a large number of ICs in a short time, and an IC test apparatus using this test method. Disclosure of the invention
この発明では、 直流試験装置を抵抗器を介して被試験 I Cの端子に接続し、 こ の抵抗器の接続によって機能試験装置から見て、 直流試験装置が大きな負荷にな らないように工夫を施すことにより、 機能試験中でも直流試験装置を被試験 I C の端子に接続したままの状態に維持できるように構成した点を特徵とするもので ある。  In the present invention, the DC test apparatus is connected to the terminal of the IC under test via a resistor, and the connection of the resistor is devised so that the DC test apparatus does not become a large load as viewed from the functional test apparatus. The feature is that the DC test equipment can be kept connected to the terminal of the IC under test even during the functional test.
この構成により機能試験中でも機能試験装置のドライバの出力端子を高ィンピ —ダンスモードに制御することにより、 直流試験を実行できるようにし、 直流試 験の実行中も機能試験装置を切離すためのスィッチ制御を不要とし、 機能試験中 に直流試験項目の中のリークテス トを実行してしまう I C試験方法を提案するも のである。  With this configuration, the DC test can be executed by controlling the output terminal of the driver of the functional test device to the high-impedance mode even during the functional test, and the switch for disconnecting the functional test device even during the DC test is executed. It proposes an IC test method that eliminates the need for control and executes the leak test in the DC test items during the function test.
従って、 この発明による I C試験方法によれば機能試験の終了と同時に直流試 験項目のリークテス 卜も完了し、 リークテス 卜を特別に時間をとつて実行しなく てよい。 この結果試験に要する時間を大幅に短縮することができる利点が得られ る。  Therefore, according to the IC test method of the present invention, the leak test of the DC test item is completed at the same time as the completion of the functional test, and the leak test does not need to be performed with a special time. As a result, there is an advantage that the time required for the test can be significantly reduced.
この発明では更に、 上述した I C試験方法を用いた I C試験装置を提案するも のである。  The present invention further proposes an IC test apparatus using the above-described IC test method.
この発明による I C試験装置は出力端子の状態を高ィンピ一ダンスモードに設 定できる ドライバにより、 被試験 I Cの各端子に試験パターン信号を印加し、 被 試験 1 Cの機能試験を実行する機能試験装置と、  The IC test apparatus according to the present invention is a functional test that applies a test pattern signal to each terminal of an IC under test by a driver capable of setting the state of an output terminal to a high impedance mode, and executes a 1C functional test under test. Equipment and
被試験 I Cの各端子に所定の電圧を印加した状態で被試験 I Cの各端子に流れ るリーク電流を測定する直流試験装置と、  A DC test device for measuring a leak current flowing through each terminal of the IC under test while a predetermined voltage is applied to each terminal of the IC under test;
この直流試験装置のセンシング点と被試験 I Cの端子との間に接続した抵抗器 と、 機能試験装置が機能試験を実行中に、 直流試験装置のセンシング点に所定の電 圧を出力させる第 1制御手段と、 A resistor connected between the sensing point of the DC tester and the terminal of the IC under test; First control means for outputting a predetermined voltage to a sensing point of the DC test apparatus while the function test apparatus is performing the function test;
この第 1制御手段の制御動作が完了した時点で機能試験装置のドライバの出力 端子を高ィンピーダンスモー ドに制御する第 2制御手段と、  Second control means for controlling the output terminal of the driver of the functional test device to a high impedance mode when the control operation of the first control means is completed;
ドライバの出力端子が高ィンピ一ダンスモ一 ドに制御された状態で被試験 I C の端子に流れるリ一ク電流を測定する電流測定手段と、  Current measuring means for measuring a leakage current flowing through the terminal of the IC under test while the output terminal of the driver is controlled in the high impedance mode;
によって構成するものである。 It is constituted by.
この発明による I C試験装置によれば機能試験の実行中は元より直流試験の実 行中でも機能試験装置と直流試験装置の相互を互に切離す必要がない。 従ってス ィツチの切替に要する時間を介することなく、 機能試験の実行中に直流試験を実 行することができる。  According to the IC test apparatus according to the present invention, it is not necessary to disconnect the functional test apparatus and the DC test apparatus from each other during the execution of the functional test and also during the execution of the DC test. Therefore, the DC test can be executed during the execution of the function test without passing through the time required for switching the switch.
この結果、 機能試験の実行中に直流試験を実行させたとしても、 機能試験と直 流試験を混在させて複合化し、 この複合化した試験に要する時間は本来の機能試 験だけに要する時間より大幅に長くなることはなく、 機能試験とリークテス トと を短時間に済ませることができる利点が得られる。 図面の簡単な説明  As a result, even if the DC test is executed during the execution of the function test, the function test and the DC test are mixed and combined, and the time required for the combined test is longer than the time required for the original function test alone. The advantage is that the function test and the leak test can be performed in a short time without significantly increasing the length. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 この発明による I C試験方法を採 fflした I C試験装置の一実施例を 示すプロック図。 第 2図はこの発明による I C試験方法を説明するためのタイ ミ ングチャート。 第 3図は従来の I C試験装置の概要を説明するためのプロック図 。 第 4図は第 3図に示した I C試験装置に用いられる機能試験装置の構成を説明 するためのブロック図。 第 5図は第 3図に示した I C試験装置に用いられる直流 試験装置の構成を説明するための接続図。 第 6図は直流試験項目の中のリークテ ス トを実行する場合の被試験 I Cの端子の様子を説明する接続図。 第了図は従来 の直流試験の様子を説明するためのタイ ミ ングチヤ一卜を示す。 発明を実施するための最良の形態  FIG. 1 is a block diagram showing an embodiment of an IC test apparatus ffl employing the IC test method according to the present invention. FIG. 2 is a timing chart for explaining the IC test method according to the present invention. FIG. 3 is a block diagram for explaining the outline of a conventional IC test apparatus. FIG. 4 is a block diagram for explaining a configuration of a functional test device used in the IC test device shown in FIG. FIG. 5 is a connection diagram for explaining the configuration of a DC test device used in the IC test device shown in FIG. Fig. 6 is a connection diagram explaining the state of the IC terminals under test when performing a leak test in the DC test items. Figure 6 shows a timing chart for explaining the state of a conventional DC test. BEST MODE FOR CARRYING OUT THE INVENTION
この発明をより詳細に説明するために、 添付の図面に従ってこれを説明する。 第 1図はこの発明で提案する I C試験方法に従って被試験 I C 3 0 0を試験す る I C試験装置の実施例を示す。 図中 1 0 0は機能試験装置、 2 0 0は直流試験 装置を示すことは第 3図で説明した内容と同じ構成である。 また、 機能試験を行 なう場合はスイッチ S i ,〜 S l nを全てオンの状態に制御し、 全ての機能試験ュニ ッ 卜 1 0 6 A〜 1 0 6 Nを被試験 I C 3 0 0の各端子に接続して実行される。 直流試験装置 2 0 0 は切替スィ ツチ S i S ^を順次 1個ずつオンの状態に制 御し、 直流試験装置 2 0 0を被試験 I C 3 0 0の各端子に選択的に接続し、 各端 子を 1個ずつ直流試験を行なう。 尚、 実際には直流試験装置 2 0 0を複数設け、 試験を受け持つ端子の数を少数化して直流試験を短時間に済ませる構成とされる が、 ここでは直流試験装置 2 0 0を 1台の直流試験装置 2 0 0で実行するものと して説明する。 In order to explain the present invention in more detail, the present invention will be described with reference to the accompanying drawings. FIG. 1 shows an embodiment of an IC test apparatus for testing an IC under test 300 according to the IC test method proposed in the present invention. In the figure, 100 is a functional test device, and 200 is a DC test device, which is the same configuration as that described in FIG. When a functional test is performed, the switches S i, to S ln are all turned on, and all the functional test units 106 A to 106 N are connected to the IC under test 300. It is executed by connecting to each terminal. The DC test apparatus 200 controls the switching switches S i S ^ one by one sequentially in an on state, selectively connects the DC test apparatus 200 to each terminal of the IC under test 300, Perform a DC test for each terminal one by one. In practice, a plurality of DC test devices 200 are provided, and the number of terminals for the test is reduced so that the DC test can be completed in a short time. The description will be made assuming that the DC test apparatus 200 executes the test.
この発明による I C試験装置の特徴は直流試験装置 2 0 0において、 電圧検出 端子 T v とセンシング点 S Ε Νとの間にスィ ツチ S 2と直列に抵抗器 R 4を接続 した点である。  A feature of the IC test apparatus according to the present invention is that in the DC test apparatus 200, a resistor R4 is connected in series with the switch S2 between the voltage detection terminal Tv and the sensing point SΕ.
つまり、 直流試験装置 2 0 0 において、 電流出力端子 と電圧検出端子 Τ ν の間に接続した保護抵抗器 R 3には並列に第〗 スィ ッチ S 1を接続し、 電圧検出 端子 Τ とセンシング点 S Ε Νとの間に第 2スィ ッチ S 2と抵抗器 R 4を直列接 続する。 更に電流出力端子 とセンシング点 S Ε Νとの間に第 3スィ ツチ S 3 を接続する。  That is, in the DC test apparatus 200, the second switch S1 is connected in parallel to the protection resistor R3 connected between the current output terminal and the voltage detection terminal Τν, and the voltage detection terminal Τ The second switch S 2 and the resistor R 4 are connected in series between the point S Ε 点. Further, a third switch S3 is connected between the current output terminal and the sensing point SΕ.
機能試験を実行する場合、 第 1 スィ ッチ S 1 と第 2 スィ ッチ S 2をオン、 第 3 スィ ッチ S 3をオフの伏態に設定する。 この状態ではセンシング点 S Ε Νと電流 出力端子 及び電圧検出端子 Τ ν との間には抵抗器 R 4が直列に接続される。 従って直流試験装置 2 0 0が接続されている機能試験ュニッ 卜から直流試験装置 2 0 0を見たィンピ一ダンスは抵抗器 R 4の抵抗値として見ることができる。 抵 抗器 R 4の抵抗値を約 1 0 k Ωに選定することにより機能試験ュニッ ト 1 0 6 A 〜 1 0 6 Nから見た直流試験装置 2 0 0のイ ンピーダンスは約 1 O k Qと して見 ることができる。  When performing a functional test, the first switch S1 and the second switch S2 are turned on and the third switch S3 is turned off. In this state, a resistor R4 is connected in series between the sensing point S Ε and the current output terminal and the voltage detection terminal ν ν. Therefore, the impedance when the DC test apparatus 200 is viewed from the functional test unit to which the DC test apparatus 200 is connected can be viewed as the resistance value of the resistor R4. By selecting the resistance value of resistor R4 to be about 10 kΩ, the impedance of DC test apparatus 200 as viewed from functional test unit 106 A to 106 N is about 1 O k Q It can be seen as
各機能試験ュニッ 卜 1 0 6 A〜 1 0 6 Nと被試験 I C 3 0 0 との間を結ぶ信号 伝送線路は一般に 5 0 Ωの特性ィンピーダンスに整合されている。 従って機能試 験ュニッ ト 1 0 6 A〜 1 0 6 Nの各出力側に 1 0 k Ωの負荷 （直流試験装置 2 0 0 ) が接続されたとしても、 線路のィンピ一ダンスが大幅に変動することはなく 、 機能試験ュニッ ト 1 0 6 A〜 1 0 6 Nから被試験 I C 3 0 0に供給する試験パ ターン信号の波形が直流試験装置 2 0 0の接続によって乱されることはない。 つ まり、 機能試験中でも直流試験装置 2 0 0を被試験 I C 3 0 0の何れかに接続し た状態に維持しても、 直流試験装置 2 0 0が接続された端子に与えられる試験パ 夕一ン信号の波形は乱されることはなく、 正常に機能試験を実行することができ る。 Signals connecting between each function test unit 106 A to 106 N and the IC under test 300 The transmission line is generally matched to a characteristic impedance of 50 Ω. Therefore, even if a load of 100 kΩ (DC test equipment 200) is connected to each output side of the functional test unit 106 A to 106 N, the impedance of the line fluctuates significantly. And the waveform of the test pattern signal supplied from the functional test unit 106A to 106N to the IC under test 300 is not disturbed by the connection of the DC test apparatus 200. . In other words, even if the DC test apparatus 200 is kept connected to any of the ICs 300 under test even during the functional test, the test signal applied to the terminal to which the DC test apparatus 200 is connected is not changed. The waveform of the one signal is not disturbed, and the function test can be executed normally.
以上の説明により直流試験装置 2 0 0が機能試験ュニッ 卜に接続されたままの 状態で機能試験を実行できることが理解されよう。  It will be understood from the above description that the function test can be performed while the DC test apparatus 200 is still connected to the function test unit.
この発明では更に、 機能試験の実行中に機能試験ュニッ 卜 1 0 6 A〜 1 0 6 N が被試験 I C 3 0 0の各端子に接続されたままの状態で直流試験 （リークテス ト ) を実行する方法を提案するものである。  Further, according to the present invention, a DC test (leak test) is performed while the function test units 106A to 106N are still connected to the respective terminals of the IC under test 300 during the execution of the function test. It suggests a way to do it.
つまり、 スィ ッチ S , ,〜 S l Dをオフの状態に制御することなく被試験 ί C 3 0 0の端子に流れるリーク電流を測定する方法を提案する。 その方法としては直流 試験装置 2 0 0がリ一ク電流を測定しょうとする端子に所定の電圧 （Η論理か L 論理を与える電圧） を印加したタイ ミ ングでその端子に接続されている機能試験 ュニッ 卜の ドライバ 1 2の出力の状態を高ィンピーダンスモー ドに制御し、 ドラ ィバ 1 2が高ィンピーダンスモードに制御されている状態において直流試験装置 2 0 0は被試験 I C 3 0 0の端子に流れるリ一ク電流を測定する。 That is, a method is proposed in which the leakage current flowing through the terminal of the device under test C 300 is measured without controlling the switches S 1 ,. The method is that the DC test equipment 200 is connected to the terminal at which the leakage current is to be measured at the timing when a predetermined voltage (voltage that gives Η logic or L logic) is applied to that terminal. The state of the output of the driver 12 of the test unit is controlled to the high impedance mode, and while the driver 12 is controlled to the high impedance mode, the DC test apparatus 200 is operated by the IC under test 300. Measure the leakage current flowing to the 0 terminal.
このためには機能試験を実行中に主制御器 M A I Νは直流試験装置 2 0 0に所 定の電圧 （Η論理か L論理） を発生させる指令信号を与える。 具体的には D A変 換器 1 7に所定の電圧を発生させるためのディ ジ夕ル値を与える。 D Α変換器 1 7はそのディ ジタル値を D A変換し、 電圧 V i^ 又は V H を出力し、 直流試験装置 2 0 0を構成する演算増幅器 1 6の非反転入力端子にその電圧 V L 又は V H を与 える。 For this purpose, the main controller MAI 与 え る gives a command signal to the DC test equipment 200 to generate the specified voltage (Η logic or L logic) during the function test. Specifically, a digital signal value for generating a predetermined voltage is given to the DA converter 17. The DΑ converter 17 converts the digital value to DA, outputs a voltage V i ^ or V H, and supplies the voltage VL or V H to the non-inverting input terminal of the operational amplifier 16 constituting the DC test apparatus 200. Give VH.
演算増幅器 1 6は電圧検出端子 T v の電圧が非反転入力端子に与えられた電圧 に等しくなるように動作する。 この結果、 電圧検出端子 T v には D A変換器 1 7 から与えられた電圧 V L 又は V H に等しい電圧が発生し、 この電圧が第 2 スイツ チ S 2 と抵抗器 R 4 を通じてセンシング点 S E Nに与えられ、 切替スィ ツチ S 2 1 〜 S 2 nの何れかを通じて被試験 I C 3 0 0の端子に供給される。 The operational amplifier 16 is configured so that the voltage of the voltage detection terminal T v is applied to the non-inverting input terminal. Operate to be equal to As a result, a voltage equal to the voltage VL or VH given from the DA converter 17 is generated at the voltage detection terminal T v, and this voltage is applied to the sensing point SEN through the second switch S 2 and the resistor R 4. given, is supplied to the DUT IC 3 0 0 terminal through one of the switching sweep rate Tutsi S 2 1 ~ S 2 n.
機能試験の実行中は第 2図 Bと Cに示すようにスィ ッチ S H〜S l nとスィ ッチ S ( , S 2 , S , を全てオンの状態に設定する。 直流のリークテス トを実行する タイ ミ ングのとり方としては例えば次のような方法が与えられる。 主制御器 M ADuring the function test execution second sweep rate, as shown in Figure B and C pitch SH～S ln the sweep rate pitch S (, S 2, S, and all set to ON state. Run the DC Rikutesu bets For example, the following method is given as a method of setting the timing: Main controller MA
1 Nに読込まれる試験プログラムの機能試験プログラムの中に第 2図 Aに示すよ うに予め直流試験用のタイ ミ ング （この夕イ ミ ングに割当る時間は 1個の端子を 試験するに要する時間とする） を設定し、 直流試験のタイ ミ ングにおいて各機能 試験ュニッ 卜 1 0 6 A ~ 1 0 6 Nの全てのドラィバ 1 2又は直流試験を行なうベ き端子に接続されている ドライバ 1 2を高ィンビ一ダンスモード （第 2図 D参照 ) に制御する制御信号 H I Pを発生させ、 ドライバ 1 2を高ィンピーダンスの状 態に制御すると共に、 直流試験装置 2 0 0に電圧発生指令を与え、 直流試験装置In the functional test program of the test program loaded into 1N, the timing for the DC test is set in advance as shown in Fig. 2A. The time required for the DC test is set, and the driver connected to all the drivers 12 of the function test units 106 A to 106 N or the terminals to be used for the DC test at the timing of the DC test Generates a control signal HIP for controlling 1 2 to high impedance mode (see Fig. 2D), controls driver 12 to high impedance state, and instructs DC test equipment 200 to generate voltage. The DC test equipment
2 0 0から所定の電圧を発生させてその電圧の印加状態でリーク電流を測定する ように制御することができる。 Control can be performed such that a predetermined voltage is generated from 200 and the leak current is measured in a state where the voltage is applied.
尚、 機能試験中に直流試験を割込ませるタイ ミ ングとしては、 被試験 I C 3 0 0に試験パターン信号を書き込んだ直後のタイ ミ ングに設定すれば、 被試験 I C If the DC test is interrupted during the function test, the timing immediately after the test pattern signal is written to the IC under test 300 can be set.
3 0 0の各端子は書き込み時に入力モ一ドに設定されているから、 そのまま直流 試験を実行できる。 Since each terminal of 300 is set to the input mode at the time of writing, the DC test can be executed as it is.
1個の端子についてリ一クテストを実行すると再び機能試験を再開させる。 機 能試験を実行中に切替スィ ッチ S ^ S ^の切替 （第 2図 E参照） を実行し、 直 流試験装置 2 0 0を他の端子に接続する。 この接続が完了した後の任意のタイ ミ ング位置に直流試験のタイミ ングを設け、 次の端子のリ一クテス 卜を実行する。 このように、 切替スィ ッチ S 2 1〜S 2 nの切替を機能試験の実行中に済ませるこ とにより、 機能試験の実行中に挿入されるリ一クテス 卜に要する時間は極く短い 時間に制限することができ、 機能試験と直流試験を平行して実行しても、 全体に 要する時間は機能試験だけに要する時間より大幅に長くなることはない。 尚、 ここで直流試験装置 2 0 0の電流測定回路について簡単に説明する。 この 実施例では微少電流 （リーク電流） 測定用の高抵抗値 （ 1 0 0 程度） を持つ 抵抗器 R 1 と大電流 （被試験 I C 3 0 0の出力電流） を測定する小抵抗値 （ 1 0 0 Ω程度） を持つ抵抗器 R 2を直列接続し、 第 5図に示したレンジ切替スィツチ S„ を省略した場合を示す。 つまり、 微少電流測定用の抵抗器 R 1 にはダイォ一 ド D 1 と D 2を並列接続し、 大電流の測定時にはこれらのダイォ一ド D 1 と D 2 をオンの状態にさせ、 大電流をダイォード D 1又は D 2をバイパスさせ、 この状 態で抵抗器 R 2に発生する電圧を引算回路 1 8 Bで検出し、 この電圧をスィツチ S5 を通じて A D変換器 1 9に与え、 A D変換して例えば主制御器 MA I Nに入 力する。 When the leak test is executed for one terminal, the function test is restarted again. Execute the switching switch S ^ S ^ (see Fig. 2E) during the execution of the function test, and connect the DC test apparatus 200 to the other terminals. After the connection is completed, provide a DC test timing at an arbitrary timing position and execute a test for the next terminal. Thus, switching sweep rate Tsu by the Sumaseruko the switching of switch S 2 1 ~S 2 n during the function test execution, function the time required for re-one Kutesu Bok to be inserted during the execution of the test is very short time Even if the function test and the DC test are performed in parallel, the time required for the entire test will not be much longer than the time required for the function test alone. Here, the current measuring circuit of the DC test apparatus 200 will be briefly described. In this embodiment, a resistor R1 having a high resistance value (about 100) for measuring a small current (leakage current) and a small resistance value (1) for measuring a large current (output current of the IC 300 under test) are used. This is the case where the resistor R 2 with a resistance of about 0 Ω is connected in series and the range switching switch S „shown in Fig. 5 is omitted. D1 and D2 are connected in parallel.When measuring a large current, these diodes D1 and D2 are turned on, and a large current is bypassed to the diode D1 or D2. vessel a voltage generated in the R 2 detected by the subtraction circuit 1 8 B, applied to the AD converter 1 9 the voltage through Suitsuchi S 5, enter by AD conversion for example to the main controller MA iN.
一方、 微少電流測定時には抵抗器 R 1には数 1 0 mV程度の電圧しか発生しな い。 このためにダイオード D 1又は D 2はオフの状態に維持される。 従って抵抗 器 R 1に発生する電圧を測定することにより、 被試験 I C 3 0 0の端子を流れる リ一ク電流を測定することができる。 つまり、 抵抗器 R 1に発生する電圧は引算 回路 1 8 Aで取り出され、 この取り出された電圧をスィ ッチ S 4 を通じて AD変 換器 1 9に与え、 AD変換器 1 9で AD変換して主制御器 MA I Nに入力し、 基 準値と比較して良否を判定する。 On the other hand, when measuring a very small current, only a voltage of about several 10 mV is generated in the resistor R1. For this reason, the diode D1 or D2 is kept off. Therefore, by measuring the voltage generated at the resistor R1, the leakage current flowing through the terminal of the IC under test 300 can be measured. That is, the voltage generated in the resistor R 1 is taken out by subtraction circuit 1 8 A, applied to the AD varying equipment 1 9 The retrieved voltage through sweep rate pitch S 4, the AD conversion by the AD converter 1 9 Then, the signal is input to the main controller MA IN and compared with the reference value to judge pass / fail.
尚、 被試験 I C 3 0 0の出力モ一ドにおける電流を測定する大電流測定モ一ド ではスィ ツチ S 〜 S 1πはオフに制御され、 機能試験装置 1 0 0は被試験 I C 3 0 0から切離され、 直流試験装置 2 0 0だけが被試験 I C 3 0 0に接続した状態 とされ、 更に直流試験装置 2 0 0では第 1スィ ッチ S 1をオフ、 第 2， 第 3スィ ツチ S 2 , S 3をオン、 スィ ッチ S 4をオフ、 スィ ッチ S 5をオンの状態にして 直流試験を実行する。 産業上の利用分野 In the large current measurement mode for measuring the current in the output mode of the IC under test 300, the switches S to S1π are controlled to be off, and the function test apparatus 100 is controlled by the IC 300 under test. Is disconnected from the DC test apparatus 200 and only the DC test apparatus 200 is connected to the IC under test 300. In the DC test apparatus 200, the first switch S1 is turned off, and the second and third switches are turned off. With the switches S 2 and S 3 on, switch S 4 off, and switch S 5 on, a DC test is performed. Industrial applications
以上説明したように、 この発明による I C試験方法によれば、 応答が遅く動作 完了までに時間が掛るスィッチ S21~S2nの切替を機能試験の実行中に行なわせ 、 機能試験の途中でドライバ 1 2を高ィンピーダンスモードに制御して直流試験 (リークテス ト） を実行させる試験方法を採ったから、 機能試験に要する時間に 直流試験に要する正味の時間 （スィ ッチの切替に要する時間を含まない） を加え た時間で機能試験とリ一クテス卜とを終了させることができる。 この結果、 全体 の試験時間を大幅に短縮できる利点が得られる。 この結果、 例えば I C製造メ -- カにおいて短時間に多量の I Cを試験しなければならない場合に用いてその効果 が発揮される。 As described above, according to the IC test method according to the invention, to perform the switching of the time until the response is slow operation completion consuming switch S 21 ~ S 2n during the function test run, the driver in the middle of the function test DC test by controlling 1 2 to high impedance mode (Leak test), the function test is performed by adding the net time required for the DC test (not including the time required for switch switching) to the time required for the functional test. Can be terminated. This has the advantage of significantly reducing the overall test time. As a result, the effect is exhibited when, for example, a large number of ICs must be tested in a short time in an IC manufacturer.

Claims

請 求 の 範 囲 The scope of the claims
1 . 出力端子の状態を高ィンピ一ダンスモ一 ドに設定できる ドラィバにより、 被試験〖 Cの各端子に試験パターン信号を印加し、 被試験 I Cの機能試験を行う 機能試験装置と、 1. A function tester that applies a test pattern signal to each terminal of the device under test C to perform a function test of the device under test IC by using a driver that can set the state of the output terminal to the high impedance mode.
被試験 I Cの各端子に所定の電圧を印加した状態で被試験 I Cの各端子に流れ る電流を測定する直流試験装置とを具備して構成される I C試験装置において、 上記機能試験装置が上記被試験 I Cの機能試験を実行中に、 上記直流試験装置 のセンシング点を抵抗を介して上記被試験 I Cの端子に接続し、 上記直流試験装 置の出力電圧が所定の電圧に設定された状態で、 上記機能試験装置のドライバを 高イ ンピーダンスモードに制御し、 この状態で上記直流試験装置によって上記被 試験 I Cの端子に流れるリーク電流を測定し、 機能試験の実行中に直流試験項目 の中のリ一ク電流測定を実行することを特徴とする I C試験方法。  A DC test device that measures a current flowing through each terminal of the IC under test while a predetermined voltage is applied to each terminal of the IC under test. During the functional test of the IC under test, the sensing point of the DC test equipment is connected to the terminal of the IC under test via a resistor, and the output voltage of the DC test equipment is set to a predetermined voltage. Then, the driver of the functional test device is controlled to the high impedance mode. In this state, the leak current flowing to the terminal of the IC under test is measured by the direct current test device. An IC test method characterized by performing a leak current measurement.
2 . A . 出力端子の状態を高イ ンピーダンスモー ドに設定できる ドライバによ り、 被試験 I Cの各端子に試験パターン信号を印加し、 被試験 I Cの機能試験を 実行する機能試験装置と、 2. A. A function test device that applies a test pattern signal to each terminal of the IC under test and executes a function test of the IC under test by a driver that can set the state of the output terminal to high impedance mode.
B . 被試験 I Cの各端子に所定の電圧を印加した状態で被試験 I Cの各端子に 流れるリ一ク電流を測定する直流試験装置と、  B. a DC test apparatus for measuring leakage current flowing through each terminal of the IC under test while a predetermined voltage is applied to each terminal of the IC under test;
C . この直流試験装置のセンシング点と被試験 I Cの端子との間に接続した抵 杭と、  C. A post connected between the sensing point of this DC test equipment and the terminal of the IC under test,
D . 上記機能試験装置が機能試験を実行中に、 上記直流試験装置のセンシング 点に所定の電圧を出力させる第 1制御手段と、  D. first control means for outputting a predetermined voltage to a sensing point of the DC test apparatus while the function test apparatus is performing a function test;
E . この第 1制御手段の制御動作が完了した時点で上記機能試験装置のドライ バの出力端子を高ィンピ一ダンスの状態に制御する第 2制御手段と、  E. second control means for controlling the output terminal of the driver of the functional test apparatus to a high impedance state when the control operation of the first control means is completed;
F . ドライバの出力端子が高ィンピ一ダンスモ一 ドに制御された状態で上記直 流試験装置において、 上記被試験 I Cの端子に流れるリーク電流を測定する動作 を実行する電流測定手段と、 によって構成したことを特徴とする I C試験装置。 F. current measuring means for performing an operation of measuring a leak current flowing in the terminal of the IC under test in the DC test apparatus in a state where the output terminal of the driver is controlled in the high impedance mode; An IC test apparatus characterized by comprising:
3 . 請求項 2記載の I C試験装置において、 上記直流試験装置は非反転入力端 子に所定の電圧が与えられて出力端子に所定の電圧を出力し、 その出力電圧を電 流検出用抵抗器を通じてセンシング点に出力し、 そのセンシング点の電圧を反転 入力端子に帰還される演算増幅器と、 上記電流検出用抵抗器に発生する電圧を測 定して被試験 I Cの端子を流れるリ一ク電流値を測定する電流測定手段とによつ て構成し、 上記センシング点を抵抗器を介して被試験 I Cの端子に接続した構成 としたことを特徴とする I C試験装置。 3. The IC test apparatus according to claim 2, wherein the DC test apparatus receives a predetermined voltage at a non-inverting input terminal, outputs a predetermined voltage to an output terminal, and outputs the output voltage to a current detection resistor. Output to the sensing point and inverts the voltage at that sensing point.The operational amplifier is fed back to the input terminal, and the leakage current flowing through the terminal of the IC under test by measuring the voltage generated at the current detection resistor. An IC test apparatus comprising current measuring means for measuring a value, and wherein the sensing point is connected to a terminal of an IC under test via a resistor.
4 . 請求項 2記載の I C試験装置において、 上記直流試験装置は非反転入力端 子と反転入力端子とを持つ演算増幅器と、 この演算増幅器の出力端子に一端側が 接続され、 他端側が電流出力端子に接続された電流検出用抵抗器と、 電流出力端 子に出力された電圧を電圧検出端子に与える第 1 スィ ッチと、 上記電流出力端子 と電圧検出端子との間に接続した保護抵抗器と、 上記電圧検出端子の電圧を上記 演算増幅器の反転入力端子に帰還させる帰還回路と、 上記電圧検出端子の電圧を センシング点を通じて被試験 I Cの端子に与える第 2 スィツチと抵抗器とから成 る直列回路と、 上記電流出力端子と上記センシング点との間に接続した第 3 スィ ツチと、 上記電流検出用抵抗器に発生する電圧を測定して上記被試験 I Cの端子 に流れる電流を測定する電流測定手段とによって構成し、 機能試験中において上 記被試験 I Cの端子に流れるリーク電流を測定するモードでは上記第 1 スィ ッチ と第 2 スィツチをオンの状態に設定し、 上記機能試験装置から直流試験装置を見 たイ ンピーダンスが上記抵抗器によって高イ ンピーダンスに見えるようにし、 非 機能試験時に行う直流試験モー ドでは上記第 1 スィ ッチをオフ、 第 2 スィ ッチと 第 3 スィ ツチをオンの状態に制御し、 上記電流出力端子を上記センシング点及び 被試験 I Cの端子に直接接続する構成としたことを特徴とする I C試験装置。 4. The IC test apparatus according to claim 2, wherein the DC test apparatus has an operational amplifier having a non-inverting input terminal and an inverting input terminal, one end connected to the output terminal of the operational amplifier, and the other end having a current output. A current detection resistor connected to the terminal, a first switch for applying a voltage output to the current output terminal to the voltage detection terminal, and a protection resistor connected between the current output terminal and the voltage detection terminal. A feedback circuit for feeding the voltage of the voltage detection terminal back to the inverting input terminal of the operational amplifier; a second switch and a resistor for applying the voltage of the voltage detection terminal to the terminal of the IC under test through a sensing point. A series circuit, a third switch connected between the current output terminal and the sensing point, and a voltage generated in the current detecting resistor is measured to determine a current flowing through the terminal of the IC under test. The first switch and the second switch are set to the ON state in the mode for measuring the leak current flowing to the terminals of the IC under test during the function test, and the function The impedance seen by the DC test equipment from the test equipment is made to look high impedance by the above resistor.In the DC test mode performed during the non-functional test, the first switch is turned off, and the second switch and the second switch are turned off. (3) An IC test apparatus, wherein a switch is controlled to an ON state, and the current output terminal is directly connected to the sensing point and a terminal of an IC under test.
PCT/JP1997/004228 1997-11-20 1997-11-20 Ic testing method and ic testing device using the same WO1999027376A1 (en)

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GB9912919A GB2335280B (en) 1997-11-20 1997-11-20 Ic testing method and ic testing device using the same
PCT/JP1997/004228 WO1999027376A1 (en) 1997-11-20 1997-11-20 Ic testing method and ic testing device using the same
JP52143599A JP3426254B2 (en) 1997-11-20 1997-11-20 IC test method and IC test apparatus using this test method
CNB971814333A CN1141593C (en) 1997-11-20 1997-11-20 IC testing method and IC testing device using the same
DE19782244T DE19782244T1 (en) 1997-11-20 1997-11-20 IC test method and IC test device operating using this IC test method
US09/319,898 US6404220B1 (en) 1997-11-20 1997-11-20 IC testing method and IC testing device using the same
TW086118710A TW356526B (en) 1997-11-20 1997-12-11 An IC testing method and IC testing device using the same method

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102609A (en) * 1999-09-28 2001-04-13 Kanegafuchi Chem Ind Co Ltd Device for measuring characteristic of photoelectric conversion device
JP2003098234A (en) * 2001-09-27 2003-04-03 Advantest Corp Semiconductor tester
WO2007007658A1 (en) * 2005-07-07 2007-01-18 Advantest Corporation Testing apparatus
WO2011132225A1 (en) * 2010-04-22 2011-10-27 株式会社アドバンテスト Pin card and test device using same

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AT412242B (en) * 2000-03-02 2004-11-25 Siemens Ag Oesterreich METHOD AND ARRANGEMENT FOR TESTING A TEST
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923676U (en) * 1982-08-04 1984-02-14 株式会社アドバンテスト IC test equipment with self-diagnosis function
JPS6329277A (en) * 1986-07-23 1988-02-06 Nec Corp Testing device for logic integrated circuit
JPS63190975U (en) * 1987-05-29 1988-12-08

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923676U (en) * 1982-08-04 1984-02-14 株式会社アドバンテスト IC test equipment with self-diagnosis function
JPS6329277A (en) * 1986-07-23 1988-02-06 Nec Corp Testing device for logic integrated circuit
JPS63190975U (en) * 1987-05-29 1988-12-08

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102609A (en) * 1999-09-28 2001-04-13 Kanegafuchi Chem Ind Co Ltd Device for measuring characteristic of photoelectric conversion device
JP2003098234A (en) * 2001-09-27 2003-04-03 Advantest Corp Semiconductor tester
JP4729212B2 (en) * 2001-09-27 2011-07-20 株式会社アドバンテスト Semiconductor test equipment
WO2007007658A1 (en) * 2005-07-07 2007-01-18 Advantest Corporation Testing apparatus
US7679372B2 (en) 2005-07-07 2010-03-16 Advantest Corporation Test apparatus
KR100989588B1 (en) 2005-07-07 2010-10-25 가부시키가이샤 어드밴티스트 Testing apparatus
JP5087398B2 (en) * 2005-07-07 2012-12-05 株式会社アドバンテスト Test apparatus and device interface apparatus
WO2011132225A1 (en) * 2010-04-22 2011-10-27 株式会社アドバンテスト Pin card and test device using same
US8547124B2 (en) 2010-04-22 2013-10-01 Advantest Corporation Pin card
JP5629680B2 (en) * 2010-04-22 2014-11-26 株式会社アドバンテスト Pin card and test apparatus using the same

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CN1244925A (en) 2000-02-16
GB2335280A (en) 1999-09-15

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