WO1995032520A1 - Electronic device package and its manufacture - Google Patents
Electronic device package and its manufacture Download PDFInfo
- Publication number
- WO1995032520A1 WO1995032520A1 PCT/JP1995/000977 JP9500977W WO9532520A1 WO 1995032520 A1 WO1995032520 A1 WO 1995032520A1 JP 9500977 W JP9500977 W JP 9500977W WO 9532520 A1 WO9532520 A1 WO 9532520A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electronic element
- mold
- package
- spacer
- manufacturing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 125000006850 spacer group Chemical group 0.000 claims abstract description 75
- 239000000463 material Substances 0.000 claims abstract description 33
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 49
- 239000012778 molding material Substances 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 32
- 230000001681 protective effect Effects 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 15
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 19
- 229920005989 resin Polymers 0.000 description 13
- 239000011347 resin Substances 0.000 description 13
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 230000007547 defect Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 241001479493 Sousa Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004848 polyfunctional curative Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06Â -Â H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Definitions
- the present invention relates to an electronic element package in which an electronic element is protected by a protection member, and a method for manufacturing the same.
- Electronic devices such as ICs
- ICs are generally sealed with protective members and used as independent electronic device packages, unless they are directly mounted on an electronic circuit board.
- This electronic element package is used, for example, by soldering the lead wire to an electronic circuit board or inserting it into a socket soldered to the electronic circuit board.
- TAB Tape Automated Bonding
- the following steps are performed to manufacture an electronic element package. That is,
- a conductive pattern with a thickness of 10 zm is formed on a substrate tape made of polyimide or the like to produce a film carrier.
- a portion corresponding to the electrode of the electronic element and a portion of the substrate tape in the vicinity of the portion and in close contact with the conductive pattern are removed by a method such as etching or the like.
- the conductive pattern is projected from the outside toward the inside of the device hole, and a lead line (the side of the lead line projecting into the device hole is referred to as an âinner holeâ). And the side connected to the external circuit etc. is called the "outer lead").
- a metal column jig called a bonding tool which presses the tip of the inner lead to the semiconductor electrode via conductive bumps while heating and mechanically and electrically joins them.
- (7) Encapsulate the package with resin etc. to enclose the electronic element,
- TAB technology is that since the electrodes of the electronic element and the inner leads can be connected at the same time, productivity can be increased compared to methods such as wire bonding.
- productivity can be increased compared to methods such as wire bonding.
- the electronic element has a large number of electrodes. Therefore, the recent trend of increasing the number of electrodes in electronic devices has further emphasized the superiority of TAB technology.
- TAB technology Another feature of TAB technology is that it is easy to reduce the thickness of electronic device packages. It is said that thinning of portable electronic devices such as calculators cannot be considered without TAB technology.
- transfer bump TAB technology as an improved technology of the TAB technology.
- this transfer bump TAB technology instead of forming a conductive bump on the electrode side of the electronic element in the above step (4), a conductive bump separately formed on the inner lead side is bonded first, and then a conductive bump is formed on the inner lead side. The inner lead is joined to the electrode of the electronic element.
- This transfer bump TAB technology does not require a conductive bump to be formed directly on the electrode of an electronic device, and can be widely used for ordinary electronic devices that do not have a special design or process.
- TAB technology there are various variations of TAB technology.
- the lead wire and the electrode of the electronic element are joined by a method such as wire bonding.
- a method such as wire bonding.
- an electronic element to which a lead wire such as an inner lead is joined is placed inside a mold formed by combining upper and lower dies. It is widely practiced to inject a molding material such as a resin into the mold to produce a mold package.
- FIG. 5 is a plan view of a film carrier-bonded electronic device manufactured by the method for manufacturing an electronic device package.
- the electrodes arranged on the four sides of the electronic element 27 An inner lead 22 formed by etching or the like in close contact with the substrate film 21 of the Lum carrier is joined.
- the inner lead 22 is connected at the same time by a dam bar 24 integrally formed therewith.
- FIG. 6 is a cross-sectional view showing a state in which the film carrier-bonded electronic device of FIG. 5 is placed in a mold to form a package.
- An electronic element 27 in which a film carrier inner lead 22 is joined to an electrode is sandwiched between an upper mold 28 and a lower mold 29, and is placed inside a mold formed therebetween. ing.
- a mold material 31 is injected from the gate 30 into the mold, and fills the mold so as to include the electronic element 27.
- the dam bar 24 fills the gap between the upper mold 28 and the lower mold 29 in the outer peripheral portion of the package, so that the molding material 31 does not leak from this gap.
- the electronic element 27 is supported by the inner lead 22 and held in a state of being floated on the mold die 2 so as not to come into contact with the mold.
- the upper mold 28 and the lower mold 29 are removed, and the part extending from the inner lead 22 (or outer lead 23) package is shaped to form an electronic element package. It is said that.
- the present inventors have found that in such a conventional method of manufacturing an electronic element package, the yield when manufacturing a thin electronic element package may be reduced, or the reliability of the manufactured electronic element package may be reduced. I found that. That is, if the electronic element 27 held in the mold by the inner lead 22 happens to be slightly inclined or the flow of the molding material 31 is uneven, the flow of the molding material 31 In some cases, the lead wire / electronic element 27 was exposed to the outside of the package due to the force of, or was greatly inclined inside the package. If a part of the lead wire / electronic element 27 is exposed to the outside of the package, the reliability of the electronic element 27 is greatly impaired. If the inclination of the electronic element 27 exceeds a certain range, defects such as contact between the inner leads 22 or disconnection of the inner leads 22 occur. This tendency is stronger as the package is thinner, so the yield decreases as the package becomes thinner.
- the reliability of the electronic element package in which the electronic element is greatly inclined inside the package, was low because undue stress was applied to the lead wires and the like, and the bondability with the electrodes was deteriorated.
- the electronic element package according to the present invention includes: an electronic element; a protection member including the electronic element; a lead wire joined to the electronic element and exposed to the outside of the protection member; and the electronic element surface of the protection member. And a spacer provided between the lead wires.
- an electronic element formed by joining one end of a lead wire is placed in a mold, a molding material is injected into the mold, and the mold is removed.
- the spacer is provided with a covering member made of the same material as the protective member on an outer edge surface side of the protective member.
- the lead wire is bonded to an electrode of the electronic element via a conductive bump.
- another aspect of the electronic element package of the present invention is an electronic element, an inner lead having one end joined to an electrode of the electronic element and a part of a substrate film of a film carrier adhered to the electronic element, A protective member encapsulated therein and molded so as to expose the other end of the inner lead to the outside, and an outer edge surface of the substrate film which is parallel to the electronic element surface of the protective member. And a plurality of said inner leads are in close contact with each other.
- an electronic element having one end of a lead wire is placed in a mold, a molding material is injected into the mold, and then the mold is removed.
- a spacer is provided between a surface of the mold that is parallel to the electronic device surface and the lead wire, and the mold material is injected into the mold. It is characterized by doing.
- the lead wire is bonded to an electrode of the electronic element via a conductive bump.
- the mold is molded into the mold while urging the spacer toward a surface parallel to the electronic element surface of the mold. It is characterized by injecting a material.
- the mold material is injected in a direction in which the spacer is urged against a surface of the mold die parallel to the electronic element. It is characterized by.
- the spacer is urged against a surface parallel to the electronic element surface of the mold by the elastic force of the lead wire. It is characterized in that a mold material is injected into the mold while the mold material is being injected.
- the spacer used is one closely attached to a plurality of lead wires.
- an electronic element is bonded to an inner lead of a film carrier, the electronic element is placed in a mold, and a molding material is injected into the mold. Thereafter, when manufacturing the electronic element package by removing the mold, a part of the inner lead placed in the mold is in close contact with a part of the substrate film of the film carrier. It is characterized by the use of such a device.
- a contact portion of the substrate film with the inner lead is formed such that a side of the mold is coated with a material of the same type as the molding material. It is characterized by.
- the inclination of the electronic element inside the package can be reduced.
- undue stress is not applied to the lead wire even in a thin package, and the reliability of the package is high.
- the inclination of the electronic element does not extremely increase in the mold, and the electronic element is mounted outside the package. Yields can be improved because defects such as exposure, lead wires contacting each other at the time of packaging, and breakage of the lead wires do not easily occur.
- an electronic element package of the present invention since the position of the electronic element in the mold is stable and a defect is unlikely to occur, an electronic element package can be manufactured with good yield. it can.
- FIG. 1 is a plan view showing one embodiment of a film carrier bonded electronic element used in the method of manufacturing an electronic element package of the present invention.
- FIG. 2 is a view showing one step of an embodiment of a method for manufacturing an electronic element package according to the present invention.
- FIG. 3 is a view showing a step of another embodiment of the method of manufacturing an electronic element package according to the present invention.
- FIG. 4 is a view showing one embodiment of the electronic element package of the present invention.
- FIG. 5 is a plan view showing an example of a film carrier bonded electronic element used in a conventional method for manufacturing an electronic element package.
- FIG. 6 is a diagram illustrating an example of a conventional electronic element package.
- FIG. 7 is a plan view showing another embodiment of the film carrier-bonded electronic device used in the method for manufacturing an electronic device package of the present invention.
- FIG. 8 is a plan view showing another embodiment of the film carrier-bonded electronic element used in the method of manufacturing an electronic element package according to the present invention.
- 1 2 Covering member, 1 3: Electronic element package, 2 1: Film carrier, 2 2: Inner lead, 2 3: Outer lead, 2 4: Dam bar,
- the electronic element various semiconductor ICs and LSIs, dielectric optical circuit elements, and the like are preferably used.
- the protective member is defined as a member to which moisture, harmful rays or heat reaches the electronic element. It is a member that protects the electronic element by encapsulating it (wrapping it so that the electronic element is not exposed to the outside) so that it does not occur.
- a paste-like inorganic or organic material that has been solidified by physical stimulus such as heating or irradiation or by the passage of time is preferably used.
- a mixture of various thermosetting resins, such as epoxy, and a filler, such as a hardening agent and silica is injected into a mold in which electronic elements are placed, and heated.
- the powder of the above mixture is formed into a tablet in advance, and is supplied to the entrance (gate) of the mold, and is heated and pressurized to be melted and pasted into the mold.
- the supply method transfer-mold method
- the supply method is also preferably performed.
- the lead wire may be any member that is joined to the electronic element and exposed to the outside of the package.
- conductive foil called inner lead terlead of TAB technology, bond wire of wire-to-bond technology, or conductive lead wire bonded to this.
- Film carrier inner leads and outer leads in TAB technology are preferred because they have adequate rigidity.
- the lead wire may or may not have conductivity.
- the lead wire may transmit a signal or power to an electronic element, but need not necessarily have such a function. It only needs to be exposed outside the package and does not need to be extended.
- âparallel toâ a certain surface means extending one-dimensionally or two-dimensionally in a direction substantially parallel to the surface.
- the outer edge surface parallel to the electronic element surface of the protective member (the surface having the largest area or the surface facing the electronic device) is the outer surface of the protective member, Refers to a surface that is roughly parallel to the electronic element surface.
- the surface parallel to the mold-type electronic element surface refers to a mold-type inner surface that is oriented substantially parallel to the electronic element surface.
- the spacer keeps the lead wire constant from the outer edge of the protective member so that the lead wire does not touch (or is exposed to the outside) the outer edge of the protective member when packaging the electronic element. Used to separate by the above distance. For example, when an electronic device with a lead wire is placed in a mold and the molding material is injected into the mold, the spacer is located between the mold and the lead wire. It has the effect of keeping the distance between the molds greater than the thickness of the spacer. Since the lead wire is bonded to the electronic element, the distance between the electronic element and the mold is constant. Thus, the electronic element can be prevented from being exposed to the outside of the package or greatly tilted inside the package.
- the spacer By placing the spacer between the lead wire bonded to two or more sides of the electronic element and the mold, the inclination of the electronic element inside the package can be effectively suppressed. . As a result, unreasonable stress or the like is not applied to the lead wire, and disconnection of the lead wire can be prevented.
- the spacer When placing a spacer between a lead wire joined to electrodes along a plurality of sides and a mold, the spacer should be provided on all sides where the lead wire is provided. In order to secure the strength of the spacer, it is preferable that adjacent spacers are connected as shown in FIG. 1, for example. In FIG. 1, all spacers along the four sides are connected, and are substantially integrated.
- the spacer is limited to one that is continuously provided as a piece corresponding to the side between the lead wire bonded to a plurality of electrodes provided on one side and the mold. Not done. That is, as shown in FIG. 8, the spacers arranged on one side may be composed of a plurality of pieces instead of a continuous piece.
- the spacer itself may or may not be exposed outside the package. However, depending on the combination of the material of the spacer and the material of the protective material of the package, there is a gap between the spacer and the package due to the aging of the package, and moisture enters the package through the gap. There may be a risk. In such a case, it is preferable to cover the surface of the spouter with a material having a good affinity for the protective member.
- the degree of freedom in setting the position where the molding material is injected into the mold can be increased. This is because the flow force of the molding material is applied to the direction in which the electronic element and the lead wire are urged toward the side where the spacer is located, and the electronic element is not exposed to the outside of the package. It is. Rather, it is preferable to apply such a force to stabilize the position of the electronic element in the mold.
- the spacer is in close contact with the lead wire because the spacer does not move when the molding material is poured into the mold. It is also preferable that the spacer be in close contact with a plurality of lead wires and connect the lead wires. This makes it possible to supplement the rigidity of the lead wires and reduce the possibility that the lead wires come into contact with each other when the molding material is injected into the mold.
- a spacer is provided in the direction along only the two opposing sides of the electronic element as shown in FIG. 7 or arranged on one side as shown in FIG. In a continuous piece of sousa Instead, it can be preferably used because it can be filled into the mold while maintaining good flow of the mold material by using a plurality of pieces.
- the spacer may be on the side of the electronic element with respect to the lead wire or on the opposite side.
- the spacer may be provided on both the electronic element side of the lead wire and the opposite side. In this case, it is preferable that the electronic element does not tilt or is exposed to the outside of the package regardless of the direction in which the force of the flow of the molding material is applied.
- the force of the flow of the molding material is applied to the side where the electronic element or lead wire has no spacer, for example, the elasticity of the lead wire
- the molding material is preferable to inject the molding material into the mold while applying a force to the surface of the mold that is parallel to the electronic element surface by force or the like.
- the elastic force of the lead wire it is preferable to use the elastic force of the lead wire to apply the bias.
- the protective member is provided with a covering member, the covering member is that having a material of the molding material and the same type (molding material chemically affinity It is preferable to consist of This makes it difficult for the spacer to be exposed to the outer edge of the package and hardly generates a gap between the spacer and the molding material, thereby reducing the possibility of water being transmitted to the lead wire.
- the thickness of the covering member is preferably about 20 to 200 â m.
- a part of the substrate film of the film carrier can be left on the inner lead and used as a spacer.
- the substrate film of the film carrier 1 may be etched so that the spacer 5 remains in the inner lead 2 of the film carrier 1.
- the conductive pattern such as the inner lead 2 is formed by, for example, electrolytic plating, the adhesion between the inner lead 2 and the spacer 5 is generally improved. It is easy to raise it. Further, it is easy to form a spacer in close contact with a plurality of inner leads. Due to such characteristics, an electronic element package manufactured by TAB technology is preferable as an application target of the present invention.
- an upper mold and a lower mold as shown in FIG. 3 are combined, and a mold having a package shape in the gap is preferably used.
- metal or ceramic is used as the material of the mold.
- the position where the mold material is injected is such that the force of the flow of the mold material is applied to the side where there is no spacer in the electronic element or lead wire. It is preferable to decide not to apply strong bias. For example, when the spacer 5 is provided between the upper die 8 and the electronic element 7 as shown in FIG. 3, the injection position (gate 10) of the molding material is set to the lower die 9 side as shown in FIG. It is preferable to provide it.
- the injection position of the molding material may be provided on both the upper die 8 side and the lower die 9 side, and the injection amount of the lower die 9 may be larger than the injection amount of the upper die 8.
- the force of the flow of the molding material is not applied in the direction in which the electronic element 7 or the like is urged to the side where the spacer is not provided, and sufficient molding material is applied to the upper die 8 side of the electronic element 7. Can be supplied, so it is preferable.
- the molding when the spacer is urged toward the mold by the force of the flow of the molding material, the molding can be performed in a state where the spacer is almost in close contact with the mold.
- the outer edge surface of the electronic element package is substantially parallel to the electronic element surface, and the inclination of the electronic element in the package can be minimized.
- the thickness of the spacer is about half of the thickness of the electronic element package minus the thickness of the lead wire, the electronic element is securely placed almost in the center of the package. Can be preferred.
- the electronic device package of the present invention was manufactured through the steps shown in FIGS.
- Film Carrier 1 (1) Conductive patterns such as inner leads 2 water leads 3 and dam bars 4 are formed on the polyimide substrate film by electrolytic plating.
- the substrate film is etched to form a device hole 6 while leaving the spacer 5;
- the inner lead 2 of the film carrier 1 was joined to the electrodes arranged on the four sides of the electronic element 7 by an inner bonder commonly used in TAB technology.
- the electronic element 7 having the film carrier bonded thereto is placed inside a mold formed between the upper mold 8 and the lower mold 9 and the molding material 11 is moved to the lower mold. It was injected from the gate 10 provided in 9 and heated. At this time, the distance between the surface of the inner lead 2 and the surface parallel to the surface of the electronic element 7 of the upper mold 8 was made shorter than the thickness of the spacer 5. Thus, the spacer 5 was urged against the surface parallel to the surface by the elastic force of the inner lead 2. Further, a gate 10 is provided on the side of the lower mold 9 so that the force of the flow of the molding material 11 is slightly applied to the spacer 5 side with respect to the electronic element 7 binary lead 2.
- the molding material was a mixture of epoxy resin and filler and hardener.
- the thickness of the electronic element package 13 was very thin, 0.5 mm, there were almost no defects such as the electronic element being exposed to the outside of the package and being greatly inclined inside the package. Did not.
- FIG. 4 is a cross-sectional view showing a step corresponding to FIG.
- a covering member 12 was provided on the surface of the spacer 5 with the same material as the molding material 11.
- the thickness of the covering member 12 was 40 m.
- the coating member 12 was formed by applying a drawing-type resin coating device only to a portion of the film carrier 1 that was in close contact with the spacer 5 before being bonded to the electronic element 7.
- the spacer was not exposed to the outside of the package, and there was almost no possibility of moisture entering between the protective member and the spacer.
- Example 3 An electronic element package similar to that of Example 1 was manufactured except that only a spacer extending in a direction along two opposing sides of the electronic element was provided, and a resin having a high degree of sharpness was used as the resin.
- FIG. 7 is a plan view showing a step corresponding to FIG. The spacer 5 was provided in such a manner as to be parallel to the resin flow direction during resin injection. As a result, even when a resin having a high viscosity was used, the resin could be filled into the mold while maintaining good flow, and an electronic element package could be manufactured.
- FIG. 8 is a plan view showing a process corresponding to FIG.
- the spacers 5 were provided as a plurality of independent pieces as shown in FIG.
- the degree of freedom of the resin flow on the upper surface of the electronic element was increased, and the resin could be filled into the mold while maintaining a good flow even when a high-viscosity resin was used, thereby producing an electronic element package.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
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Claims
1 . é»åçŽ åãšã åèšé»åçŽ åãå
å
ããä¿è·éšæãšã åèšé»åçŽ åã«æ¥åãã åèšä¿è·éšæã®å€éšã«é²åºãã ãªäžãç·ãšã åèšä¿è·éšæã®åèšé»åçŽ åé¢ã«äžŠ åããå€ç·£é¢ããã³åèšãªäžãç·ã®éã«èšããããã¹ãºãŒã¶ãšãåããããšãç¹ åŸŽãšããé»åçŽ åããã±ãŒãžã
2 . ãªãŒ ãç·ã®äžç«¯ãæ¥åãããŠãªãé»åçŽ åãã¢ãŒã«ãåå
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3 . åèšã¹ãºãŒãµã¯ã åèšä¿è·éšæã®å€çžé¢åŽã«åèšä¿è·éšæãšåçš®ã®æ質ãã ãªã被èŠéšæãåããŠãªãããšãç¹åŸŽãšããè«æ±é
1 ãŸã㯠2ã«èšèŒã®é»åçŽ å ã㜠ãã²ãŒ ã³ 0
4 . åèšãªãŒ ãç·ã¯ã å°é»ãã³ããä»ããŠåèšé»åçŽ åã®é»æ¥µã«æ¥åãããŠãªã ããšãç¹åŸŽãšããè«æ±é
1 ã 3ã®ããããã«èšèŒã®é»åçŽ åããã±ãŒãžã
5 . é»åçŽ åãšã åèšé»åçŽ åã®é»æ¥µã«äžç«¯ãæ¥åãããã€ãã£ã«ã ãã£ãªã¢ã® åºæ¿ãã€ã«ã ã®äžéšãå¯çããã£ã³ããŒãªãŒ ããšã åèšé»åçŽ åãå
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6 . ãªãŒ ãç·ã®äžç«¯ãæ¥åãããŠãªãé»åçŽ åãã¢ãŒã«ãåå
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7 . åèšãªãŒ ãç·ã¯ã å°é»ãã³ããä»ããŠåèšé»åçŽ åã®é»æ¥µã«æ¥åãããŠãã ããšãç¹åŸŽãšããè«æ±é
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8 . åèšã¹ãºãŒãµãã åèšã¢ãŒã«ãåã®åèšé»åçŽ åé¢ãšäžŠåããé¢ã«åããŠä» å¢ããªããåèšã¢ãŒã«ãåå
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9 . åèšã¹ãºãŒã¶ãåèšã¢ãŒã«ãåã®åèšé»åçŽ åã«äžŠåããé¢ã«å¯ŸããŠä»å¢ã
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1 0 . åèšã¹ãºäžãµãåèšãªãŒ ãç·ã®åŒŸæ§åã«ããåèšã¢ãŒã«ãåã®åèšé»åçŽ åé¢ã«äžŠåããé¢ã«å¯ŸããŠä»å¢ããªããåèšã¢ãŒã«ãåå
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8ãŸã㯠9ã«èšèŒã®é»åçŽ åããã±ãŒãžã®è£œé æ¹æ³ã
1 1 . åèšã¹ãºãŒãµãšããŠã¯ã åèšã¢ãŒã«ãåã®åŽãåèšã¢ãŒã«ãæãšåçš®ã®æ 質ã«ãã被èŠããããã®ãçšããããšãç¹åŸŽãšããè«æ±é
6ã 1 0ã®ããããã« èšèŒã®é»åçŽ åããã±ãŒãžã®è£œé æ¹æ³ã
1 2 . åèšã¹ãºäžãµãšããŠã¯ã è€æ°ã®ãªãŒ ãç·ã«å¯çããããã®ãçšããããšã ç¹åŸŽãšããè«æ±é
6ã 1 1ã®ããããã«èšèŒã®é»åçŽ åããã±ãŒãžã®è£œé æ¹æ³ã
1 3 . ãã£ã«ã ãã€ãªã¢ã®ã£ã³ããŒãªãŒ ãã«é»åçŽ åãæ¥åãã 該é»åçŽ åã㢠äžã«ãåå
ã«çœ®ãã 該ã¢ãŒã«ãåå
ã«ã¢ãŒã«ãæã泚å
¥ãã ãããåŸã åèšã¢ãŒ ã«ãåãé€å»ããããŠé»åçŽ åããã±ãŒãžã補é ããã«éããŠã åèšã£ ã³ããŒãª äžãã®ãã¡åèšã¢ãŒã«ãåå
ã«çœ®ãããéšäœãã åèšãã£ã«å¶ã〠ãªã¡ã®åºæ¿ã ã£ã«ã ã®äžéšãšå¯çãããŠãªããã®ãçšããããšãç¹åŸŽãšããé»åçŽ åããã±äž ãžã®è£œé æ¹æ³ã
1 4 . åèšåºæ¿ãã£ã«ã ã®åèšã€ã³ãäžãªãŒ ããšã®å¯çéšã¯ã åèšã¢ãŒã«ãåã® åŽãåèšã¢ãŒã«ãæãšåçš®ã®æ質ã«ãã被èŠãããŠãªãããšãç¹åŸŽãšããè«æ±é
1 3ã«èšèŒã®é»åçŽ åããã±ãŒãžã®è£œé æ¹æ³ã
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950705781A KR960703272A (ko) | 1994-05-23 | 1995-05-22 | ì ììì í©ìŒìŽì§ ë° ê·ž ì ì¡°ë°©ë² (electronic device package and method for manufacturing the same) |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6/108592 | 1994-05-23 | ||
JP10859294 | 1994-05-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1995032520A1 true WO1995032520A1 (en) | 1995-11-30 |
Family
ID=14488723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1995/000977 WO1995032520A1 (en) | 1994-05-23 | 1995-05-22 | Electronic device package and its manufacture |
Country Status (2)
Country | Link |
---|---|
KR (1) | KR960703272A (ja) |
WO (1) | WO1995032520A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19921867A1 (de) * | 1999-05-11 | 2000-11-30 | Siemens Ag | Verfahren zur Herstellung eines Halbleiterelements mit mindestens einem verkapselten Chip auf einem Substrat |
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JPS5754356A (ja) * | 1980-08-05 | 1982-03-31 | Gao Ges Automation Org | |
JPS61268417A (ja) * | 1985-05-23 | 1986-11-27 | Ryoden Kasei Co Ltd | æš¹èæ圢äœã®è£œé æ¹æ³ |
JPS63190363A (ja) * | 1987-02-02 | 1988-08-05 | Matsushita Electronics Corp | ãã¯âããã±âãž |
JPH0590317A (ja) * | 1991-09-27 | 1993-04-09 | Rohm Co Ltd | é»åéšåã«ãããã¢ãŒã«ãéšã®æ圢æ¹æ³ |
JPH06334109A (ja) * | 1993-05-27 | 1994-12-02 | Hitachi Cable Ltd | åå°äœè£ 眮çšãªãŒããã¬ãŒã ãšåå°äœè£ 眮ã®è£œé æ¹æ³ |
-
1995
- 1995-05-22 WO PCT/JP1995/000977 patent/WO1995032520A1/ja unknown
- 1995-05-22 KR KR1019950705781A patent/KR960703272A/ko not_active Application Discontinuation
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Publication number | Priority date | Publication date | Assignee | Title |
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JPS5754356A (ja) * | 1980-08-05 | 1982-03-31 | Gao Ges Automation Org | |
JPS61268417A (ja) * | 1985-05-23 | 1986-11-27 | Ryoden Kasei Co Ltd | æš¹èæ圢äœã®è£œé æ¹æ³ |
JPS63190363A (ja) * | 1987-02-02 | 1988-08-05 | Matsushita Electronics Corp | ãã¯âããã±âãž |
JPH0590317A (ja) * | 1991-09-27 | 1993-04-09 | Rohm Co Ltd | é»åéšåã«ãããã¢ãŒã«ãéšã®æ圢æ¹æ³ |
JPH06334109A (ja) * | 1993-05-27 | 1994-12-02 | Hitachi Cable Ltd | åå°äœè£ 眮çšãªãŒããã¬ãŒã ãšåå°äœè£ 眮ã®è£œé æ¹æ³ |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19921867A1 (de) * | 1999-05-11 | 2000-11-30 | Siemens Ag | Verfahren zur Herstellung eines Halbleiterelements mit mindestens einem verkapselten Chip auf einem Substrat |
DE19921867C2 (de) * | 1999-05-11 | 2001-08-30 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterbauelements mit mindestens einem verkapselten Chip auf einem Substrat |
Also Published As
Publication number | Publication date |
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KR960703272A (ko) | 1996-06-19 |
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