US8419299B2 - Coating and developing apparatus and method, and storage medium - Google Patents

Coating and developing apparatus and method, and storage medium Download PDF

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US8419299B2
US8419299B2 US13/219,955 US201113219955A US8419299B2 US 8419299 B2 US8419299 B2 US 8419299B2 US 201113219955 A US201113219955 A US 201113219955A US 8419299 B2 US8419299 B2 US 8419299B2
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developing
block
modules
substrate
resist
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US20120057861A1 (en
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Nobuaki Matsuoka
Akira Miyata
Shinichi Hayashi
Suguru Enokida
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • G03F7/3021—Imagewise removal using liquid means from a wafer supported on a rotating chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/6715—Apparatus for applying a liquid, a resin, an ink or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67178—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers vertical arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67184—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames

Definitions

  • the present disclosure relates to a coating and developing apparatus, a coating and developing method and a storage medium for applying a resist to a substrate and developing the resist after exposure.
  • a semiconductor manufacturing process includes a photolithography process comprising applying a photoresist (hereinafter simply referred to as a resist) to a surface of a semiconductor wafer (hereinafter simply referred to as a wafer), exposing the resist in a predetermined pattern, and developing the exposed resist to form a resist pattern.
  • a coating and developing apparatus for forming such a resist pattern includes a processing block having processing modules for performing various types of processing of a wafer.
  • the processing block is comprised of a stack of unit blocks for forming various types of coating films (e.g. resist film) and unit blocks for performing developing processing, as described e.g. in Japanese Patent Laid-Open Publication No. 2007-115831 (JP2007115831A).
  • Each unit block has therein a wafer transport mechanism, by which a wafer is transported to various processing modules provided in each unit block, in which the wafer undergoes processing in the processing modules according to a predetermined order.
  • processing modules provided in a processing block are becoming diversified.
  • a processing block may also be provide with a hardening liquid supplying module for hardening a patterned resist film to allow repetitive photolithography process, and an upper protective film-forming module for forming a protective film for immersion exposure.
  • a hardening liquid supplying module for hardening a patterned resist film to allow repetitive photolithography process
  • an upper protective film-forming module for forming a protective film for immersion exposure.
  • the wafers are transported sequentially among the modules in the unit blocks. Thus, if one of the processing modules fails, the wafers can no longer be transported to the processing module for the later-stage processing. This significantly may lower the operation efficiency of the apparatus.
  • the present disclosure provides a technique which can reduce the lowering of the throughput of a coating and developing apparatus, and enables small installation area of a processing block.
  • a coating and developing apparatus comprising a carrier block, a processing block and an interface block arrayed in that order, the interface block connectable to an exposure apparatus, said coating and developing apparatus being configured to transfer a substrate from a carrier, which has been loaded into the carrier block, to the processing block, form coating films containing a resist film, deliver the substrate to the exposure apparatus via the interface block, develop the substrate, which has been exposed by the exposure apparatus and returned to the processing block via the interface block, in the processing block, and return the substrate into the carrier block, wherein: (a) the processing block includes a liquid processing block disposed on a carrier block side and a heating processing block disposed on an interface block side, the liquid processing block comprising a stack of a liquid processing unit blocks; (b) the liquid processing unit blocks includes a first unit block, a second unit block and one or more of developing unit blocks, said one or more developing unit blocks overlying or underlying a stack of the first unit block and the second unit block, the second unit block overlying the first unit
  • a coating and developing apparatus comprising a carrier block, a processing block and an interface block arrayed in that order, the interface block connectable to an exposure apparatus, said coating and developing apparatus being configured to transfer a substrate from a carrier, which has been loaded into the carrier block, to the processing block, form coating films containing a resist film, deliver the substrate to the exposure apparatus via the interface block, develop the substrate, which has been exposed by the exposure apparatus and returned to the processing block via the interface block, in the processing block, and return the substrate into the carrier block, wherein: (a) the processing block includes a liquid processing block disposed on a carrier block side and a heating processing block disposed on an interface block side, the liquid processing, block comprising a stack of a liquid processing unit blocks; (b) the liquid processing unit blocks includes a first unit block, a second unit block and one or more developing unit blocks, said one or more developing unit blocks overlying or underlying a stack of the first unit block and the second unit block, the second unit block overlying the first unit
  • the coating and developing apparatus may be configured such that, said coating and developing apparatus includes two developing unit blocks, one being a positive resist-developing unit block exclusively for developing a positive resist and having the positive resist-developing modules disposed on both sides of the associated transport passage, and the other being a negative resist-developing unit block exclusively for developing a negative resist having the negative resist-developing modules disposed on both sides of the associated transport passage.
  • each of said one or more developing unit blocks includes at least two positive resist-developing modules and at least two negative resist-developing modules.
  • the two positive resist-developing modules may be arranged on both sides of the transfer passage, and the two negative resist-developing modules may be arranged on both sides of the transfer passage.
  • the two positive resist-developing modules may be arranged side by side on one side of the transfer passage, and the two negative resist-developing modules may be arranged side by side on another side of the transfer passage.
  • a coating and developing apparatus comprising a carrier block, a processing block and an interface block arrayed in that order, the interface block connectable to an exposure apparatus, said coating and developing apparatus being configured to transfer a substrate from a carrier, which has been loaded into the carrier block, to the processing block, form coating films containing a resist film, deliver the substrate to the exposure apparatus via the interface block, develop the substrate, which has been exposed by the exposure apparatus and returned to the processing block via the interface block, in the processing block, and return the substrate into the carrier block, wherein: (a) the processing block includes a liquid processing block disposed on a carrier block side and a heating processing block disposed on an interface block side, the liquid processing block comprising a stack of a liquid processing unit blocks; (b) the liquid processing unit blocks include a stack of film-forming unit blocks comprising an antireflection film-forming unit block for forming an antireflection film on a substrate, a resist film-forming unit block for forming a resist film on the antireflection
  • a coating and developing method that employs a coating and developing apparatus including a carrier block, a processing block and an interface block arrayed in that order, the interface block connectable to an exposure apparatus, said coating and developing apparatus being configured to transfer a substrate from a carrier, which has been loaded into the carrier block, to the processing block, form coating films containing a resist film, deliver the substrate to the exposure apparatus via the interface block, develop the substrate, which has been exposed by the exposure apparatus and returned to the processing block via the interface block, in the processing block, and return the substrate into the carrier block, wherein: (a) the processing block includes a liquid processing block disposed on a carrier block side and a heating processing block disposed on an interface block side, the liquid processing block comprising a stack of a liquid processing unit blocks; (b) the liquid processing unit blocks includes a first unit block, a second unit block and one or more of developing unit blocks, said one or more developing unit blocks overlying or underlying a stack of the first unit block and the second unit block, the
  • a coating and developing method that employs a coating and developing apparatus including a carrier block, a processing block and an interface block arrayed in that order, the interface block connectable to an exposure apparatus, said coating and developing apparatus being configured to transfer a substrate from a carrier, which has been loaded into the carrier block, to the processing block, form coating films containing a resist film, deliver the substrate to the exposure apparatus via the interface block, develop the substrate, which has been exposed by the exposure apparatus and returned to the processing block via the interface block, in the processing block, and return the substrate into the carrier block, wherein: (a) the processing block includes a liquid processing block disposed on a carrier block side and a heating processing block disposed on an interface block side, the liquid processing block comprising a stack of a liquid processing unit blocks; (b) the liquid processing unit blocks includes a first unit block, a second unit block and one or more developing unit blocks, said one or more developing unit blocks overlying or underlying a stack of the first unit block and the second unit block, the second
  • a coating and developing method that employs a coating and developing apparatus including a carrier block, a processing block and an interface block arrayed in that order, the interface block connectable to an exposure apparatus, said coating and developing apparatus being configured to transfer a substrate from a carrier, which has been loaded into the carrier block, to the processing block, form coating films containing a resist film, deliver the substrate to the exposure apparatus via the interface block, develop the substrate, which has been exposed by the exposure apparatus and returned to the processing block via the interface block, in the processing block, and return the substrate into the carrier block, wherein: (a) the processing block includes a liquid processing block disposed on a carrier block side and a heating processing block disposed on an interface block side, the liquid processing block comprising a stack of a liquid processing unit blocks; (b) the liquid processing unit blocks include a stack of film-forming unit blocks comprising an antireflection film-forming unit block for forming an antireflection film on a substrate, a resist film-forming unit block for forming a
  • a coating and developing method that employs a coating and developing apparatus including a carrier block, a processing block and an interface block arrayed in that order, the interface block connectable to an exposure apparatus, said coating and developing apparatus being configured to transfer a substrate from a carrier, which has been loaded into the carrier block, to the processing block, form coating films containing a resist film, deliver the substrate to the exposure apparatus via the interface block, develop the substrate, which has been exposed by the exposure apparatus and returned to the processing block via the interface block, in the processing block, and return the substrate into the carrier block, wherein: (a) the processing block includes a liquid processing block disposed on a carrier block side and a heating processing block disposed on an interface block side, the liquid processing block comprising a stack of a liquid processing unit blocks; (b) the liquid processing unit blocks include a stack of film-forming unit blocks comprising an antireflection film-forming unit block for forming an antireflection film on a substrate, a resist film-forming unit block for forming a
  • This method may further includes: applying a positive resist liquid to a second substrate by using one of the resist film-forming modules to form a first positive-type resist film; supplying a developer to the second substrate to provide the first positive-type resist film with a first pattern; supplying a hardening liquid to the first positive-type resist film to harden it; applying a positive resist liquid onto the hardened first positive-type resist film by using one of the resist film-forming modules to form a second positive-type resist film; and supplying a developer to the second substrate by using one of the positive-resist developing modules to provide the second positive-type resist film with a second pattern.
  • a non-transitory storage medium storing a computer program for use in a coating and developing apparatus, wherein the computer program is configured to perform the foregoing coating and developing method.
  • FIG. 1 is a plan view of a coating and developing apparatus in a first embodiment
  • FIG. 2 is a perspective view of the coating and developing apparatus
  • FIG. 3 is a vertical sectional side view of the coating and developing apparatus
  • FIG. 4 is a vertical sectional side view of the anterior processing block of the coating and developing apparatus
  • FIG. 5 is a vertical sectional front view of the liquid processing block of the coating and developing apparatus
  • FIG. 6 is a vertical sectional front view of a heating processing block of the coating and developing apparatus
  • FIG. 7 is a vertical sectional front view of an auxiliary block of the coating and developing apparatus
  • FIG. 8 is a top plan view of the auxiliary block of the coating and developing apparatus
  • FIG. 9 is a vertical sectional front view of an interface block of the coating and developing apparatus.
  • FIG. 10 is a diagram showing the construction of the control section of the coating and developing apparatus
  • FIG. 11 is a flow diagram illustrating a wafer transport route in the coating and developing apparatus
  • FIG. 12 is a diagram illustrating exposure of a wafer W
  • FIG. 13 is a diagram illustrating exposure of a wafer W
  • FIG. 14 is a flow diagram illustrating a wafer transport route in the normal situation
  • FIG. 15 is a flow diagram illustrating a wafer transport route in a case where abnormality occurs in a liquid processing module
  • FIG. 16 is a plan view of a coating and developing apparatus in a second embodiment
  • FIG. 17 is a perspective view of the coating and developing apparatus in the second embodiment
  • FIG. 18 is a vertical sectional side view of the coating and developing apparatus in the second embodiment
  • FIG. 19 is a vertical sectional side view of the anterior processing block of the coating and developing apparatus in the second embodiment
  • FIG. 20 is a top plan view of the liquid processing block of the coating and developing apparatus in the second embodiment
  • FIG. 21 is a top plan view of the liquid processing block of the coating and developing apparatus in the second embodiment.
  • FIG. 22 is a top plan view of the liquid processing block of the coating and developing apparatus in the second embodiment
  • FIG. 23 is a flow diagram illustrating a wafer transport route in the coating and developing apparatus in the second embodiment
  • FIG. 24 is a flow diagram illustrating a wafer transport route in the coating and developing apparatus in the second embodiment
  • FIG. 25 is a flow diagram illustrating a wafer transport route in the coating and developing apparatus in the second embodiment
  • FIG. 26 is a plan view of a wafer processed by the coating and developing apparatus in the second embodiment
  • FIG. 27 is a plan view of a wafer processed by the coating and developing apparatus in the second embodiment
  • FIG. 28 is a plan view of a wafer processed by the coating and developing apparatus in the second embodiment
  • FIG. 29 is a top plan view of the liquid processing block of the coating and developing apparatus in one modification of the second embodiment
  • FIG. 30 is a top plan view of the liquid processing block of the coating and developing apparatus in one modification of the second embodiment
  • FIG. 31 is schematic diagram showing one modification of the first embodiment in which hardening modules are provided.
  • FIG. 32 is schematic diagram showing one modification of the first, embodiment in which hardening modules are provided.
  • the coating and developing apparatus 1 includes a carrier block S 1 for receipt and deliver of carriers C, in each of which a plurality of, for example 25 , wafers W are hermetically housed, a processing block S 20 for performing processing of the wafers W, an auxiliary block S 5 and an interface block S 6 , the blocks being arrayed linearly.
  • a processing block S 20 for performing processing of the wafers W
  • an auxiliary block S 5 for performing processing of the wafers W
  • an auxiliary block S 5 an interface block S 6
  • an exposure apparatus S 7 for performing immersion exposure.
  • the right side of FIG. 1 is hereinafter referred to as “anterior”, the left side as “posterior”, the upper side as “left”, and the lower side as “right”.
  • the carrier block S 1 includes stages 11 for placing the carriers C thereon, shutters 12 provided in a wall in front of the stages 11 , and a transfer arm 13 for taking wafers W out of the carriers C via the shutters 12 .
  • the transfer arm 13 has five wafer holders 14 arranged in the vertical direction, and is configured to be movable back and forth, vertically movable, rotatable about a vertical axis and movable in the carrier C arrangement direction.
  • the transfer arm 13 transfers, at a time, five wafers W to a transfer module BU 11 of the processing block S 20 .
  • An element having a site on which a wafer W can be placed is herein referred to as “module”.
  • processing module A module for carrying out processing of a wafer W, such as heating, processing with a liquid, supply of a gas, peripheral exposure, etc., is herein referred to as “processing module”; and a processing module for supplying a chemical liquid or a cleaning liquid is herein referred to as “liquid processing module”.
  • the processing block S 20 is composed of an anterior processing block S 2 , a liquid processing block S 3 and a heating processing block S 4 , which are arranged in that order from the carrier block S 1 side to the auxiliary block S 5 side.
  • FIG. 4 is a schematic sectional side view of the anterior processing block S 2 .
  • the anterior processing block S 2 includes a shelf unit U 1 and a shelf unit U 2 , each of which is composed of a plurality of modules stacked on top of each other.
  • the shelf units U 1 and U 2 are arranged in right-and-left direction.
  • Each of the shelf units U 1 and U 2 has hydrophobizing modules ADH, which are disposed at the same level as a first liquid processing unit block B 1 in the liquid processing block S 3 .
  • the hydrophobizing module ADH is configured to supply a processing gas to the surface, including the bevel portion, of a wafer W to enhance the hydrophobicity of the surface of the wafer W, thereby preventing peeling off of a film from the wafer W during immersion exposure.
  • the unit block has transfer modules BU 11 and BU 12 , the former BU 11 being provided for receiving wafers W from a carrier C, the latter BU 12 being provided for returning wafers W to a carrier C.
  • the transfer module BU 11 has five wafer holders arranged vertically at five different levels to collectively receive five wafers W at a time from the aforementioned transfer arm 13 .
  • the wafers W transferred to the transfer module BU 11 are removed therefrom one by one, and then are subjected to predetermined process steps.
  • the modules designated by reference signs including letters “BU” each have stages, each of which is configured to allow a wafer to be placed thereon to store the wafer.
  • a transfer arm 15 Disposed between the shelf units U 1 and U 2 is a transfer arm 15 which is configured to be vertically movable, rotatable about a vertical axis and movable back and forth.
  • the transfer arm 15 can transfer a wafer among the shelf units U 1 and U 2 , and a shelf unit U 3 described later.
  • the liquid processing block S 3 is composed of liquid processing unit blocks B 1 , B 2 , B 3 , B 4 and B 5 , which are stacked in that order from the bottom, and which are separated from each other by partitioning walls.
  • the liquid processing unit blocks B 1 to B 5 have essentially the same mechanical structure and layout.
  • FIG. 1 shows the second liquid processing unit block B 2 , which will be described as a representative of the liquid processing unit blocks B 1 to B 5 .
  • a transport region (transport passage) R 1 is formed in the second liquid processing unit block B 2 at the central area thereof to extend in anteroposterior direction.
  • Resist film-forming modules COT 1 and COT 2 are disposed on both sides (left side and right side) of the transport region R 1 so as to oppose each other.
  • a main arm A 2 which is a main transport mechanism, is provided in the transport region R 1 .
  • the main arm A 2 is configured to be movable back and forth, vertically movable, rotatable about a vertical axis and movable in the anteroposterior direction.
  • the main arm A 2 can transfer a wafer between the modules in the second liquid processing unit block B 2 .
  • the resist film-forming modules COT 1 includes two spin chucks 22 arranged in the anteroposterior direction. Each spin chuck 22 is capable of attracting and holding a central portion of the back surface of a wafer W by suction and is rotatable about a vertical axis. A top-open processing cup 23 surrounds the periphery of the spin chuck 22 and prevents scattering of a resist liquid. When a wafer W is being processed, the wafer W is housed in the processing cup 23 , with the central portion of the back surface of the wafer W being held by the spin chuck 22 .
  • the resist film-forming modules COT 1 has nozzles 24 and 25 which are shared by the two processing cups 23 .
  • the nozzle 24 is provided to supply a positive resist (a positive-type resist) liquid to a wafer, while the nozzle 25 is provided to supply a negative resist (a negative-type resist) liquid to a wafer.
  • the nozzles 24 and 25 are supported by an arm 26 .
  • a drive mechanism 27 via the arm 26 , moves the nozzles 24 and 25 in the arrangement direction of the processing cups 23 and vertically moves the nozzles 24 and 25 .
  • the nozzles 24 and 25 can be moved by means of the drive mechanism 27 between the two processing cups. 23 .
  • the nozzle 24 can therefore eject a negative (negative-type) or positive (positive-type) resist liquid toward the center of a wafer W held by each spin chuck 22 .
  • the resist liquid which has been supplied from the nozzle 24 or 25 to the wafer W, spreads to the periphery of the wafer W due to centrifugal force caused by the rotation of the wafer W about a vertical axis, whereby a resist film is formed on the wafer W.
  • the resist film-forming module COT 1 is provided with a nozzle for supplying a solvent to a peripheral portion of a wafer W to remove an unnecessary film in the peripheral portion.
  • the resist film-forming module COT 2 has the same structure as the resist film-forming module COT 1 .
  • the other processing unit blocks B 1 and B 3 to B 5 will be briefly described.
  • the other processing unit blocks B 1 and B 3 to B 5 also includes modules having the same layout as that of the processing unit block B 2 . That is, liquid processing modules are disposed on both sides of the transport region R 1 to oppose each other.
  • Main arms A 1 A 2 , A 3 and, A 4 are disposed in the processing unit blocks B 1 to B 4 , respectively, so that in each processing unit block a wafer W is transported between the associated processing modules by the associated main arm independently of the other processing unit blocks.
  • the first processing unit block B 1 has the essentially the same structural features as the second processing unit block B 2 except that the former has antireflection film-forming modules BCT 1 and BCT 2 instead of the resist film-forming modules COT 1 and COT 2 of the latter.
  • the antireflection film-forming modules BCT 1 and BCT 2 have essentially the same structural features as the resist film-forming modules COT 1 and COT 2 except that the former is configured to supply a chemical liquid for forming an antireflection film to a wafer from a single nozzle 24 to form an antireflection film on the wafer W.
  • the antireflection film-forming modules BCT 1 and BCT 2 have two processing cups 23 and two spin chucks 22 , by which a single nozzle 24 is shared.
  • the third processing unit block B 3 has essentially the same structural features as the second processing unit block B 2 except that the former has protective film-forming modules ITC 1 and ITC 2 instead of the resist film-forming modules COT 1 and COT 2 of the latter.
  • the protective film-forming modules ITC 1 and ITC 2 are each configured to supply a chemical liquid for forming a protective film to a wafer from a single nozzle 24 to form a protective film on the wafer W.
  • the fourth processing unit block B 4 has essentially the same structural features as the second processing unit block B 2 except that the former has negative resist-developing modules NDEV 1 and NDEV 2 instead of the resist film-forming modules COT 1 and COT 2 of the latter.
  • the negative resist-developing modules NDEV 1 and NDEV 2 have essentially the same structural features as the resist film-forming modules COT 1 and COT 2 except that the former is configured to supply a developer for developing a negative resist (negative-type resist) instead of a resist liquid of the latter.
  • the fifth processing unit block B 5 has essentially the same structural features as the second processing unit block B 2 except that the former has negative resist-developing modules NDEV 3 and NDEV 4 instead of the resist film-forming modules COT 1 and COT 2 of the latter.
  • the negative resist-developing modules NDEV 3 and NDEV 4 have the essentially the same structural features as the resist film-forming modules COT 1 and COT 2 except that the former is configured to supply a developer for developing a negative resist (negative type resist) instead of a resist liquid of the latter.
  • the transport region R 1 of the fourth processing unit block B 4 and the transport region R 1 of the fifth processing unit block B 5 are vertically connected to each other.
  • the main arm A 4 is shared by the fourth and fifth processing unit blocks B 4 and B 5 .
  • the main arm A 4 has, in addition to each of the main arms A 1 to A 3 , a function of vertically moving between the fourth and fifth processing unit blocks B 4 and B 5 , and thus can transfer wafers between modules in the fourth and fifth processing unit blocks B 4 and B 5 .
  • a shelf unit U 3 vertically extending across the liquid processing unit blocks B 1 to B 5 , is provided in the liquid processing block S 3 at a position facing the carrier block S 1 .
  • the shelf unit U 13 is comprised of a stack of a plurality of modules, including transfer modules CPL 11 and transfer modules CPL 12 provided in height positions accessible by the main arms A 1 and A 4 , respectively. Wafers W can be transferred between the anterior block S 2 and liquid processing block S 3 via the transfer modules CPL 11 and CPL 12 .
  • a transfer module with the reference sign “CPL” is provided with a cooling stage for cooling a wafer W placed on it.
  • a transfer module with the reference sign “TRS” has a stage allowing a wafer W to be placed thereon.
  • a shelf unit U 4 vertically extending across the liquid processing unit blocks B 1 to B 5 , is provided in the liquid processing block S 3 at a position facing the interface block S 1 .
  • the shelf unit U 4 is comprised of a stack of a plurality of modules, including transfer modules BU 31 , BU 32 , BU 33 and BU 34 provided in height positions corresponding to the liquid processing unit blocks B 1 , B 2 , B 3 and 85 , respectively.
  • the wafer In a case where a wafer cannot be loaded into a liquid processing module in a processing unit block because the liquid processing module is being occupied, by another wafer or subjected to maintenance work, the wafer is transported into the transfer module (any one of BU 31 -BU 34 ) associated with the processing unit block (any one of B 1 -B 5 ) to temporarily stand-by, before the wafer is loaded into the transport-destination module.
  • the transfer module any one of BU 31 -BU 34
  • the processing unit block any one of B 1 -B 5
  • transfer modules TRS 11 are provided in a height position corresponding to the liquid processing unit block B 1
  • transfer modules TRS 12 and TRS 13 are provided in a height position corresponding to the liquid processing unit block B 2
  • transfer modules TRS 14 and TRS 15 are provided in a height position corresponding to the liquid processing unit block B 3
  • transfer modules TRS 16 are provided in a height position corresponding to the liquid processing unit block B 4
  • transfer modules TRS 17 are provided in a height position corresponding to the liquid processing unit block B 5 .
  • Wafers W can be transferred between the liquid processing block S 3 and heating processing block S 4 via the transfer modules TRS 11 to TRS 17 .
  • the heating processing block S 4 is composed of heating processing unit blocks C 1 , C 2 , C 3 and 04 , which are stacked in that order from the bottom, and which are separated from each other by partitioning walls.
  • the heating processing unit block C 1 is disposed laterally adjacent to the liquid processing unit blocks B 1 and B 2 ; the heating processing unit block C 2 is disposed laterally adjacent to the liquid processing unit blocks B 3 ; and the heating processing unit block C 3 and C 4 are disposed laterally adjacent to the liquid processing unit blocks B 4 and B 5 , respectively.
  • Each of the heating processing unit block C 1 to C 4 includes: heating modules; a main arm (D 1 -D 3 ) which is a transport means of the individual heating processing unit block (C 1 -C 4 ); and a transport region R 2 within which the main arm (D 1 -D 3 ) moves.
  • FIG. 1 shows the first heating processing unit block C 1 , which will be described as a representative of the liquid processing unit blocks C 1 to C 4 .
  • the transport region R 2 is formed in the first heating processing unit block C 1 at the central area thereof to extend in anteroposterior direction. Shelf units U 11 , U 12 and U 13 are arrayed in a row along the transport region R 2 on the left side thereof, while shelf units U 14 , U 15 and U 16 are arrayed in a row along the transport region R 2 on the right side thereof, so that the shelf units U 11 , U 12 and U 13 and the shelf units U 14 , U 15 and U 16 oppose each other across the transport region R 2 .
  • Each of the shelf units U 11 to U 16 includes heating modules stacked in multiple (e.g., four) layers.
  • the main arm D 1 is arranged in the transport region R 2 .
  • the main arm D 1 is configured to be movable back and forth, vertically movable, rotatable about a vertical axis and movable in the anteroposterior direction, which will be described in more detail, later.
  • the heating module has a hot plate 31 for heating a wafer W placed thereon, and a cooling plate 32 for cooling the wafer W and also for transferring the wafer W between the hot plate and the main arm D 1 .
  • the wafer W heated by the hot plate 31 is transferred to the cooling plate 32 , is cooled on the cooling plate 32 , and then is transferred to the main arm D 1 .
  • the heating modules for heating a wafer after formation an antireflection film is designated by the reference sign “CHP”
  • PAB the heating modules for heating a wafer after formation a resist film
  • the second heating processing unit block 02 has a planner arrangement similar to that of the first heating processing unit block C 1 , while the second heating processing unit block C 2 is different from the first heating processing unit block C 1 in that, in the former, each of the shelf units U 14 , U 15 and U 16 includes heating modules stacked in two layers.
  • the heating modules are provided for heating a wafer W after formation of a protective film, and are designated by the reference sign “CHP”.
  • the main arm D 1 is shared by the first and second heating processing unit blocks C 1 and C 2 ; the main arm D 1 can transfer a wafer to and from the modules in the first and second heating processing unit blocks C 1 and C 2 , the modules of the shelf unit U 4 provided in height positions corresponding to the first and second heating processing unit blocks C 1 and C 2 and modules of the shelf unit U 5 (described later) provided in height positions corresponding to the first and second heating processing unit blocks C 1 and C 2 .
  • the third heating processing unit block C 3 has essentially the same structure as the second heating processing unit block C 2 but differs from the latter in that the former has a main arm D 2 provided exclusively for the third heating processing unit block C 3 .
  • the main arm D 2 can transfer a wafer W to and from the modules in the third heating processing unit block C 3 , the modules of the shelf unit U 4 provided in a height position corresponding to the third heating processing unit block C 3 and modules of the shelf unit U 5 provided in a height position corresponding to the third heating processing unit block C 3 .
  • the heating modules contained in the third heating processing unit block C 3 are heating modules for heating a wafer after exposure designated by reference sign “PEB”, and heating modules for heating a wafer after development designated by reference sign “POST”.
  • the fourth heating processing unit block C 4 has essentially the same structure as the third heating processing unit block C 3 , and has a main arm D 3 which is essentially the same as the main arm D 2 .
  • the main arms D 1 , D 2 and D 3 constitute a “vertical transport mechanism”.
  • the auxiliary processing unit block S 5 is composed of auxiliary processing unit blocks E 1 , E 2 , E 3 , E 4 and E 5 , which are stacked in that order from the bottom, and which are separated from each other by partitioning walls.
  • the auxiliary processing unit blocks E 1 and E 2 are disposed laterally adjacent to the first heating processing unit block C 1 ; and the auxiliary processing unit blocks E 3 , E 4 and E 5 are disposed laterally adjacent to the third, fourth and fifth heating processing unit blocks C 2 , C 3 and C 4 , respectively.
  • FIG. 1 shows the second auxiliary processing unit block E 2 , which will be described as a representative of the auxiliary processing unit blocks E 1 to E 5 .
  • a transport region R 3 is formed in the second auxiliary processing unit block B 2 at the central area thereof to extend in anteroposterior direction.
  • Back surface cleaning modules BST 1 and BST 2 are disposed on both sides (left side and right side) of the transport region R 3 so as to oppose each other.
  • the back surface cleaning module (BST) has essentially the same mechanical structure as that of the antireflection film-forming module (BCT), and has two processing cups 23 and two spin chucks 22 , but the former differs from the latter in that the former has two nozzles (not shown) each assigned to respective ones of the processing cups 23 , instead of the previously described nozzle 24 of the latter.
  • a main arm F 1 Provided in the transport region R 3 is a main arm F 1 , which is configured to be movable back and forth, vertically movable, rotatable about a vertical axis and movable in the anteroposterior direction.
  • the first auxiliary processing unit block E 1 also has a transport region R 3 like the second auxiliary processing unit block E 2 , but does not have liquid processing modules.
  • the first auxiliary processing unit block E 3 has the same construction as the second auxiliary processing unit block E 2 , and has back surface cleaning modules BST 3 and BST 4 having the same construction as the back surface cleaning modules BST 1 and BST 2 .
  • the transport regions R 3 of the first to third auxiliary processing unit blocks E 1 to E 3 are vertically connected to form a single transport region, and share the main arm F 1 .
  • the main arm F 1 transfers a wafer between modules provided in the first to third auxiliary processing unit blocks E 1 to E 3 and modules provided in shelf units U 5 and U 6 (described later in detail) disposed at the levels (heights) of the first to third auxiliary processing unit blocks E 1 to E 3 .
  • FIG. 8 is a plan view of the fourth auxiliary processing unit block E 4 .
  • the fourth auxiliary processing unit block E 4 has a transport region R 3 like the second auxiliary processing unit block E 2 , but differs from the second auxiliary processing unit block E 2 in that the fourth auxiliary processing unit block E 4 has a developing module DEV 1 and post-exposure cleaning modules PIR 1 and PIR 2 instead of the back surface cleaning module BST.
  • the post-exposure cleaning modules PIR 1 and PIR 2 are arrayed in the anteroposterior direction and face the transport region R 3 .
  • the developing module DEV 1 faces the post-exposure cleaning modules PIR 1 and PIR 2 across the transport region R 3 .
  • the post-exposure cleaning modules PIR 1 and PIR 2 are each provided to supply a processing liquid for removing the protection film or for cleaning, and each have the same mechanical structure as the resist film forming module COT except that one nozzle 24 is provided for one processing cup 23 and one spin chuck 22 .
  • the developing module DEV 1 has the same mechanical construction as the resist film-forming module COT 1 (i.e., one nozzle 24 is shared by two processing cups 24 ), but differs from the resist film-forming module COTI in that the developing module DEV 1 (also DEV 2 ) supplies a developer for developing a positive (positive-type) resist instead of a resist liquid. That is, the developing module DEV 1 is a positive resist-developing module.
  • the fifth auxiliary processing unit block E 5 includes a developing module DEV 2 corresponding to the developing module DEV 1 , and post-exposure cleaning modules PIR 3 and PIR 4 corresponding to the post-exposure cleaning modules PIR 1 and PIR 2 .
  • the fourth and fifth auxiliary processing unit blocks E 4 and E 5 share a main arm F 2 corresponding to the main arm F 1 .
  • the main arm F 2 transfers a wafer between modules provided in the fourth and fifth auxiliary processing unit blocks E 4 and E 5 and modules provided in shelf units U 5 and U 6 (described later in detail) disposed at the levels (heights) of the fourth and fifth auxiliary processing unit blocks E 4 and E 5 .
  • a shelf unit U 5 is provided on the carrier block S 1 side in the transport regions R 3 to extend vertically from the first auxiliary processing unit block E 1 to the fifth auxiliary processing unit block E 5 .
  • transfer modules CPL 31 is provided at height positions accessible by the main arm F 1
  • transfer modules CPL 32 and CPL 33 are provided at height positions accessible by the main arm F 2 .
  • FIG. 9 is the vertical sectional view of the interface block S 6 .
  • a shelf unit U 6 formed by stacking modules in multiple layers is provided in the interface block S 6 .
  • a transfer module TRS 21 is provided at a height position accessible by the main arm F 2
  • transfer modules TRS 22 is provided at a height position accessible by the main arm F 1 .
  • transfer modules BU 41 , BU 42 , CPL 41 and CPL 42 are also provided.
  • Interface arms 35 and 36 are provided in the interface block S 6 .
  • the interface arms 35 and 36 are each configured to be movable back and forth, vertically movable, rotatable about a vertical axis, and also horizontally movable.
  • the interface arm 35 can access the exposure apparatus S 7 , the transfer modules CPL 41 and CPL 42 , and transfer a wafer W between those modules.
  • the interface arm 36 can access the modules constituting the shelf unit U 6 , and transfer a wafer W between those modules.
  • the controller 51 provided in the coating and developing apparatus 1 will now be described with reference to FIG. 10 .
  • reference numeral “ 50 ” denotes a bus.
  • the controller 51 includes a program 52 , a memory 53 , a CPU 54 , etc.
  • the program 52 contains instructions (steps) to output control signals to various components of the coating and developing apparatus 1 , to transport wafers W between modules in the below-described manners, and to carry out processing of each wafer W.
  • the program 52 (including program for displaying and inputting of process parameters) is stored in a non-transitory storage medium such as flexible disk, compact disk, hard disk, MO (magneto-optical) disk, memory card, etc., and installed in the controller 51 .
  • the memory has a storage area 55 for storing transfer schedules showing the relationship between, the ID of a wafer, the transfer destination modules of the wafer, the sequence (order) of transporting the wafer to the transfer destination modules.
  • the controller 51 has a mode selection unit 56 , by which one of processing modes can be selected for each production lot of wafers W.
  • the processing modes includes: a negative development processing mode in which a negative resist is applied to a wafer in the resist film-forming module COT and the wafer is developed in the negative resist-developing module NDEV; and a positive development processing mode in which a positive resist is applied to a wafer in the resist film-forming module COT and the wafer is developed in the positive developing module DEV.
  • the transfer schedule is determined based on the selected processing mode. Note that, in this specification, the reference signs designating the processing modules are sometimes simplified by removing the numeral part thereof (e.g., COT 1 ⁇ COT) in a case where there is no need to distinguish individual modules from each other.
  • a wafer W is transferred from a carrier C to the transfer module BU 11 in the shelf unit U 1 by the transfer arm 13 , and transferred to the transfer arm 15 and then to the hydrophobizing unit ADH in the shelf unit U 1 or U 2 , in which the wafer is subjected to a hydrophobizing treatment.
  • the wafer W is transferred, in the following order, to the transfer arm 15 ⁇ the transfer module CPL 11 of the shelf unit U 3 ⁇ the main arm A 1 of the first liquid processing unit block B 1 ⁇ the antireflection film-forming module BCT 1 or BCT 2 in which an antireflection film is formed on the wafer W.
  • the wafer W is transferred, in the following order, to the main arm A 1 ⁇ the transfer module TRS 11 of the shelf unit U 4 ⁇ the main arm D 1 of the first heat processing unit block C 1 ⁇ the heating module CHP ⁇ the main arm D 1 ⁇ the transfer module TRS 12 of the shelf unit U 4 ⁇ the main arm A 2 of the second liquid processing unit block B 2 ⁇ the resist film-forming unit COT 1 or COT 2 in which a negative resist film is formed on the wafer W.
  • the wafer W is transferred, in the following order, to the main arm A 2 ⁇ the transfer module TRS 13 of the shelf unit U 4 ⁇ the main arm D 2 ⁇ the heating module PAB ⁇ the main arm D 1 ⁇ the transfer module TRS 14 of the shelf unit U 4 ⁇ the main arm A 3 of the third liquid processing unit block B 3 ⁇ the protective film-forming unit ITC 1 or ITC 2 in which a protective film is formed on the resist film.
  • the wafer W is transferred, in the following order, to the main arm A 3 ⁇ the transfer module TRS 15 of the shelf unit U 4 ⁇ the main arm D 1 ⁇ the heating module CHP ⁇ the main arm D 1 ⁇ the transfer module CPL 31 of the shelf unit U 5 ⁇ the main arm F 1 of the first to third auxiliary unit block E 1 to E 3 ⁇ one of the back surface cleaning module BST 1 to BST 4 in which the wafer is subjected to the back surface cleaning process.
  • the wafer W is transferred, in the following order, to the main arm F 1 ⁇ the transfer module TRS 21 of the shelf unit U 6 ⁇ the interface arm 36 ⁇ the transfer module BU 41 ⁇ the interface arm 36 ⁇ the transfer module CPL 41 ⁇ the interface arm 35 ⁇ the exposure apparatus S 7 in which the wafer is subjected to immersion exposure.
  • FIGS. 12 and 13 illustrate processing of a wafer in the exposure apparatus S 7 .
  • reference numeral “ 41 ” denotes a stage on which a wafer W to be exposed is placed. The stage 41 rotates on a vertical axis.
  • Reference letter “N” denotes a notch formed in the wafer W.
  • Reference numeral “ 43 ” denotes an exposure head which moves while exposing the wafer W. The exposure head 43 moves on parallel lines across the wafer W, as shown by the arrow and the dashed line, while applying light to the wafer W. A striped-pattern exposed area 44 is thus formed in the wafer W. In the figures, the exposed area 44 is shown by the dotted area.
  • reference numeral “ 45 ” denotes a non-exposed area.
  • the wafer W is transferred, in the following order, to the interface arm 35 ⁇ the transfer module CPL 42 ⁇ the interface arm 36 ⁇ the transfer module BU 42 ⁇ the interface arm 36 ⁇ the transfer module TRS 22 ⁇ the main arm F 2 of the fourth and fifth auxiliary unit block E 4 and E 5 ⁇ one of the post-exposure cleaning modules PIR 1 to PIR 4 in which the wafer W is subjected to the protective film-removing and cleaning process.
  • the wafer W is transferred, in the following order, to the main arm F 2 ⁇ the transfer module CPL 32 or CPL 33 of the shelf unit U 5 ⁇ the main arm D 2 of the third heating processing unit block C 3 or the main arm D 3 of the fourth heating processing unit block C 4 ⁇ the heating module PEB ⁇ the main arm D 2 or D 3 ⁇ the transfer module TRS 16 or TRS 17 of the shelf unit U 4 ⁇ the main arm A 4 of the fourth and fifth liquid processing unit block E 4 and E 5 ⁇ one of the negative resist-developing modules NDEV 1 to NDEV 4 in which the developer is supplied to the wafer W so that the non-exposed area 65 is dissolved in a developer to form a lattice-like pattern of holes.
  • the holes can be used, for example, for the formation of contact holes.
  • the wafer W is transferred, in the following order to, the main arm E 4 ⁇ the transfer module TRS 16 or TRS 17 of the shelf unit U 4 ⁇ the main arm D 2 or D 3 ⁇ the heating module POST ⁇ the main arm D 2 or D 3 ⁇ the transfer module TRS 16 or TRS 17 ⁇ the main arm A 4 ⁇ the transfer module CPL 12 of the shelf unit U 3 ⁇ the transfer arm 15 ⁇ the transfer module BU 12 ⁇ the transfer arm 13 ⁇ the carrier C.
  • the wafer transport route in the coating and developing apparatus 1 in a case where the user selects a positive development processing mode, will be described, focusing on the differences from the foregoing case where the user selects the negative development processing mode.
  • a wafer W is transported from a carrier C to the resist film-forming module COT 1 or COT 2 in which a positive resist liquid is applied to the wafer W.
  • the wafer W is transported from the resist film-forming module (COT 1 or COT 2 ) to the exposure apparatus S 7 .
  • the exposure process in the exposure apparatus S 7 does not perform the rotation of the stage 41 and the subsequent movement and exposure by the exposure head 43 after the first exposure of the whole surface of the wafer.
  • the pattern formed by the positive development processing mode is different from that formed by the negative development processing mode.
  • the wafer W is transported to the one of the post-exposure cleaning modules PIR 1 to PIR 4 and to the heating module PEB along the same transport route as that of the negative development processing mode, in which the wafer W is subjected to the predetermined processes.
  • the main arm D 2 or D 3 of the heating processing unit block C 3 or C 4 transports the wafer to the transfer module CPL 32 or CPL 33 .
  • the main arm F 2 transports the wafer W to the developing module DEV 1 or DEV 2 , in which a developer for positive development is supplied to the wafer W, the exposed portions of the resist film is dissolved.
  • the wafer is transported, in the following order, to the main arm F 2 ⁇ the transfer module CPL 32 or CPL 33 ⁇ the main arm D 3 or D 4 ⁇ the heating module POST. After that, the wafer W is returned to the carrier C through the same transport route as that of the negative development processing mode.
  • FIG. 14 schematically shows the transport route in normal operation; while FIG. 15 schematically shows the transport route in a case where the resist film-forming module COT 2 and the negative developing module NDEV 2 are unusable.
  • the transport schedule of the subsequent wafers W which are scheduled to be transported into the unusable resist film-forming module COT 2 is changed such that they are transported into the resist film-forming module COT 1 to be processed therein;
  • the transport schedule of the subsequent wafers W which are scheduled to be transported into the unusable negative resist-developing module NDEV 2 is changed such that they are transported into the negative resist-developing module NDEV 1 to be processed therein.
  • the transport schedule is changed such that the subsequent wafers W are transported into the liquid processing module opposing the unusable liquid processing module of the same type.
  • a liquid processing module is unusable when the liquid processing module fails or when the liquid processing module is subjected to maintenance.
  • the controller 51 automatically changes the transport schedule.
  • the user In case of maintenance, the user must designate the liquid processing module which is to be subjected to maintenance, and then the controller 51 automatically changes the transport schedule.
  • the timing at which the wafer W is subjected to the hydrophobizing process is not limited to that described above.
  • the transport route may be changed as follows: After formation of the resist film and the subsequent heating processing in the heating module PAB, the wafer may be transported through the main arm D 1 , the main arm A 2 and the transfer module in the shelf unit U 3 to one of the hydrophobizing modules ADH in the shelf units U 1 and U 2 in which the wafer W may be subjected to the hydrophobizing process. The wafer W may be then transported through the transfer module in the shelf unit U 3 and the transfer arm 15 into the liquid processing block S 2 .
  • the coating and developing apparatus 1 in the foregoing embodiment includes the liquid processing block S 3 which is formed by vertically stacking the liquid processing unit blocks B 1 to B 5 which are respectively provided with the antireflection film-forming modules BCT, the resist film-forming modules COT, the protective film-forming modules ITC, the negative resist-developing modules NDEV and the negative resist-developing modules NDEV; and includes a heating processing clock S 4 which is formed by vertically stacking the heating modules and which is located laterally adjacent to the liquid processing block S 3 :
  • liquid processing modules of the same type face across the transport region R 1 .
  • the footprint of the liquid processing block S 3 can be reduced; decrease in the throughput can be suppressed, because, even if one of the liquid processing modules becomes unusable, the other liquid processing module(s) can be used to process the subsequent wafers W.
  • the coating and developing apparatus 1 in the foregoing embodiment includes the negative resist-developing modules NDEV and the positive developing modules DEV and thus can deal with formation of both negative and positive resist patterns, resulting in cost reduction and efficient use of the floor area of the factory.
  • FIGS. 16 , 17 and 18 are a plan view of the coating and developing apparatus 6 , a perspective view thereof, and a vertical sectional side view thereof, respectively.
  • disposed in the anterior processing block S 2 are a shelf unit U 21 and a shelf unit U 22 on the posterior side of the shelf unit U 1 and the shelf unit U 2 , respectively.
  • the space between the shelf unit U 1 and the shelf unit U 2 , and the space between the shelf unit U 21 and the shelf unit U 22 provide a transport region R 4 extending in the anteroposterior direction.
  • FIG. 19 is a front view of the anterior processing block S 2 . Note that, for the convenience of the drawing making, the shelf units U 21 and U 22 are illustrated outside the shelf units U 1 and U 2 .
  • the hydrophobizing modules ADH are provided in the shelf units U 21 and U 22 , like the shelf units U 1 and U 2 .
  • FIG. 20 is a top plan view of the first liquid processing unit block B 1 .
  • the antireflection film-forming modules BCT 1 and BCT 2 are disposed on the carrier block S 1 side, while hardening modules FCOT 1 and FCOT 2 are disposed on the interface block S 6 side.
  • the hardening module FCOT has the same mechanical structure as the resist film-forming module COT, but is configured to supply a hardening liquid instead of a resist liquid.
  • a hardening liquid is supplied to a resist film in which a resist pattern is formed, the resist pattern hardens, so that the resist pattern becomes insoluble in a solvent contained in a resist liquid.
  • FIG. 16 is a top plan view of the resist film-forming modules COT 1 and COT 2 disposed on the carrier block S 1 side.
  • the protective film-forming modules ITC 1 and ITC 2 are disposed on the interface block S 6 side.
  • FIG. 21 is a top plan view of the third liquid processing block S 3 .
  • the negative resist-developing modules NDEV 1 and NDEV 2 are disposed on the carrier block S 1 side so as to oppose each other, and the negative resist-developing modules NDEV 3 and NDEV 4 are disposed on the interface block S 6 side.
  • FIG. 22 is a top plan view of the fourth liquid processing unit block B 4 .
  • the developing modules DEVI and DEV 2 are disposed on the carrier block S 1 side, and the developing modules DEV 3 and DEV 4 are disposed on the interface block S 6 side.
  • the heating processing block S 4 of the coating and developing apparatus 6 has essentially the same mechanical structure as that in the first embodiment.
  • the main arm D 1 can transfer a wafer W to and from the transfer modules provided in height positions corresponding to the liquid processing unit blocks B 1 and B 2 in the shelf unit U 4 .
  • the main arms D 2 and D 3 can transfer a wafer W to and from the transfer modules provided in height positions corresponding to the liquid processing unit blocks B 3 and B 4 in the shelf unit U 4 .
  • the auxiliary block S 5 is composed of auxiliary processing unit blocks E 1 , E 2 , E 3 and E 4 , by which a main arm F 1 is shared.
  • the back surface cleaning module BST and the post-exposure cleaning modules PIR are disposed so as to oppose each other across the transport region R 3 .
  • the back surface cleaning module BST provided in the coating and developing apparatus 6 has one spin chuck 22 and one processing cup 23 .
  • the user can select one of the negative development processing mode and the positive development processing mode by the mode selection unit 56 of the controller 51 .
  • the lattice-like resist pattern of holes which has been described in the above first embodiment, can be formed.
  • the wafer transport route when the negative development processing mode is carried out, will be described with reference to FIG. 23 .
  • a wafer W is transported, in the following order, to the transfer arm 13 ⁇ the transfer module BU 11 of the shelf unit U 1 ⁇ the hydrophobizing module ADH of the shelf unit U 1 , U 2 , U 21 or U 22 ⁇ the transfer arm 15 ⁇ the transfer module CPL 11 ⁇ the main arm A 1 ⁇ the antireflection film-forming module BCT 1 or BCT 2 ⁇ the main arm A 1 ⁇ the transfer module TRS 11 ⁇ the main arm D 1 ⁇ the heating module CHP ⁇ the main arm D 1 ⁇ the transfer module TRS 12 ⁇ the main arm A 2 ⁇ the resist film-forming unit COT 1 or COT 2 in which a negative resist film is formed on the wafer W.
  • the wafer W is transferred, in the following order, to the main arm A 2 ⁇ the transfer module TRS 13 ⁇ the main arm D 1 ⁇ the heating module PAB ⁇ the main arm D 1 ⁇ the transfer module TRS 14 ⁇ the main arm A 2 ⁇ the protective film-forming unit ITC 1 or ITC 2 ⁇ the main arm A 2 ⁇ the transfer module TRS 15 ⁇ the main arm D 1 ⁇ the heating module CHP ⁇ the transfer module CPL 31 ⁇ the main arm F 1 ⁇ the back surface cleaning module BST ⁇ the main arm F 1 .
  • the wafer W is loaded into the exposure apparatus S 7 via the interface block S 6 , and is subjected to immersion exposure similarly to when the negative development processing mode is performed in the first embodiment.
  • the wafer W is transferred from the interface block S 6 to the main arm F 1 , from which the wafer W is transferred, in the following order to, the post-exposure cleaning module PIR ⁇ the transfer module CPL 32 ⁇ the main arm D 2 ⁇ the heating module PEB ⁇ the main arm D 2 ⁇ the transfer module TRS 16 ⁇ the main arm A 3 ⁇ the negative resist-developing modules NDEV 1 , NDEV 2 , NDEV 3 or NDEV 4 in which the wafer W is subjected to developing processing.
  • the post-exposure cleaning module PIR the transfer module CPL 32 ⁇ the main arm D 2 ⁇ the heating module PEB ⁇ the main arm D 2 ⁇ the transfer module TRS 16 ⁇ the main arm A 3 ⁇ the negative resist-developing modules NDEV 1 , NDEV 2 , NDEV 3 or NDEV 4 in which the wafer W is subjected to developing processing.
  • the wafer W is transported, in the following order, to the main arm A 3 ⁇ the transfer module TRS 17 ⁇ the main arm D 2 ⁇ the heating module POST ⁇ the main arm D 2 ⁇ the transfer module TRS 18 ⁇ the main arm A 3 ⁇ the transfer module CPL 12 . Thereafter, the wafer W is returned to the carrier C, like the first embodiment.
  • FIGS. 24 and 25 show the wafer transfer route, when the positive developing process is carried out, focusing on the differences from the foregoing negative developing process.
  • a wafer W taken out from the carrier C is subjected to a first resist pattern formation, and the wafer W is returned to the carrier C.
  • the wafer W is subjected to a second resist pattern formation, and is again returned to the carrier C.
  • FIG. 24 shows the transport route upon the first resist pattern formation and the modules used therefor
  • FIG. 25 shows the transport route upon the second resist pattern formation and the modules used therefor.
  • FIGS. 26 to 28 show the surface of a wafer W during processing, and description is made suitably referring to FIGS. 26 to 28 .
  • a wafer W is transported from the carrier C to the exposure apparatus S 7 along the same route as the route when the negative developing process is performed, and is processed in the respective modules.
  • the resist film-forming module COT 1 or COT 2 a positive resist is applied onto the wafer W instead of a negative resist.
  • the exposure apparatus S 7 a striped-pattern exposed area is formed similarly to when the negative development processing mode is performed in the first embodiment.
  • FIG. 26 shows the resist pattern in which recesses of the pattern are denoted by reference numeral 61 and projections thereof are denoted by reference numeral 62 .
  • a vertical side section of the resist pattern is indicated by the arrow.
  • the wafer W is transported, in the following order, to the main arm A 4 ⁇ the transfer module TRS 17 ⁇ the heating module POST ⁇ the transfer module TRS 18 ⁇ the main arm A 4 ⁇ the transfer module CPL 12 . Thereafter, the wafer is returned to the carrier C like the first embodiment, and the first resist pattern formation is finished.
  • the wafer W is again taken out from the carrier C to the transfer module BU 11 , and the second resist pattern formation is started as shown in FIG. 25 .
  • the wafer W is transported, in the following order, to the transfer arm 15 ⁇ the transfer module CPL 11 ⁇ the hardening module FCOT 1 or FCOT 2 ⁇ the main arm D 1 ⁇ the heating module CHP in which the pattern is hardened.
  • the wafer W is transported to the resist film-forming module COT 1 or COT 2 in which a positive resist is supplied to the wafer W, like the first resist pattern formation.
  • the recesses 61 are filled with the newly supplied resist 63 .
  • the wafer W is transported along the same route as the first resist pattern formation.
  • the wafer W is loaded into the exposure apparatus S 7 .
  • the exposure head 43 moves such that a striped-pattern exposed area is formed.
  • the orientation of the notch N in the wafer W differs from that of the exposure process of the first pattern formation by 90° ( FIG. 28 ).
  • the wafer W After immersion exposure, like the first pattern formation, the wafer W is transported to the developing module DEV in which an area 64 that has been exposed in the second pattern formation dissolves in a developer. However, the projections 62 , which have been formed in the first pattern formation, do not dissolve in the developer, although the projections 62 are included in the exposed area 64 . Thus, holes in a lattice pattern are formed. Thereafter, the wafer W is processed similarly to the first pattern formation, and is transported among the respective modules so as to be returned to the carrier C. Also in the second embodiment, like the first embodiment, when one of the opposed liquid processing modules of the same kind fails, the wafer W can be continuously transported and processed by using the other liquid processing module.
  • the liquid processing block S 3 is constituted by stacking the first liquid processing unit bock B 1 including the antireflection film-forming modules BCT and the hardening modules FCOT, the second liquid processing unit block B 2 including the resist film-forming modules COT and the protective film-forming modules ITC, the third liquid processing unit block B 3 including the negative resist-developing modules NDEV, and the fourth liquid processing unit block B 4 including the developing modules DEV.
  • the heating processing block S 4 in which the heating modules are stacked is laterally adjacent to the liquid processing block S 3 .
  • the liquid processing modules of the same kind oppose each other across the transport region R 1 .
  • a pattern of the same shape can be formed.
  • a resist pattern of an excellent shape can be formed.
  • the layout of the liquid processing modules in the coating and developing apparatus 6 in the second embodiment is not limited to the above example.
  • the antireflection film-forming modules BCT and the resist film-forming modules COT may be provided in the first liquid processing unit block B 1
  • the hardening modules FCOT and the protective film-forming modules ITC may be provided in the second liquid processing unit block B 2 .
  • a wafer W is heated in the heating module CHP of the first heating processing unit block C 1 after formation of an antireflection film.
  • the wafer W is returned to the first liquid processing unit block B 1 via the transfer module TRS of the shelf unit U 5 , and is processed in the resist film-forming module COT.
  • the wafer W is again loaded into the first heating processing unit block C 1 , and is heated in the heating module PAB.
  • the wafer W is transported to the second liquid processing unit block B 2 by the main arm F 1 in which a protective film is formed thereon. After that, the wafer W is transported along the same transport route as the second embodiment so as to be processed.
  • a wafer W is transported along the same route as the aforementioned negative developing process. After a first resist pattern has been formed, the wafer W is transported, from the carrier C, in the following order, to the transfer arm 13 ⁇ the transfer module BU 11 ⁇ the transfer arm 15 ⁇ the first liquid processing, unit block B 1 ⁇ the first heating processing unit block C 1 ⁇ the second liquid processing unit block B 2 .
  • the wafer W is processed by the hardening module FCOT 1 or FCOT 2 of the second liquid processing unit block B 2 .
  • the wafer W is transported to the heating module CHP of the first heating processing unit block C 1 in which the wafer W is heated. Further, the wafer W is transported, in the following order, to the auxiliary block S 5 ⁇ the transfer module CPL 42 of the interface block S 6 ⁇ the transfer module BU 41 ⁇ the third heating processing unit block C 3 ⁇ the fourth liquid processing unit block B 4 , and is returned to the carrier C. At this time, the wafer W is transported to the carrier C without being processed in the respective blocks. After that, the wafer W is again taken out from the carrier C, and is loaded into the first liquid processing unit block B 1 . Then, the wafer W is transported and processed in the same manner as the first resist pattern formation, so as to perform a second resist pattern formation.
  • the layout of the liquid processing modules of the unit block for performing development is not limited to those in the above embodiments.
  • the third liquid processing unit block C 3 are provided with the developing modules DEV and the fourth liquid processing unit block C 4 is provided with the negative resist-developing modules NDEV, the third and the fourth liquid processing unit blocks C 3 and C 4 may each include both the developing modules DEV and the negative resist-developing modules NDEV.
  • one unit block for performing development may include at least two developing modules (positive resist-developing modules) DEV and at least two negative resist-developing modules NDEV; the two developing modules of the same type (DEV or NDEV) may be arranged on both side of the transfer passage of the unit block to face across the transfer passage, such that two different developing modules (DEV and NDEV) are arranged side by side on each side of the transfer passage.
  • DEV positive resist-developing modules
  • NDEV negative resist-developing modules
  • the two developing modules of one type may be arranged side by side on one side of the transfer passage of the unit block
  • the two developing modules of the other type e.g., NDEV
  • the main arm of the third liquid processing unit block C 3 for performing developing processing or the main arm of the fourth liquid processing unit block C 4 for performing developing processing may be shared by these liquid processing unit blocks C 3 and C 4 .
  • the liquid processing unit blocks including the developing modules DEV and the negative resist-developing modules NDEV may be located below the liquid processing unit bock including the other liquid processing modules.
  • the hardening module FCOT provided in the coating and developing apparatus 6 in the second embodiment may be applied to the coating and developing apparatus 1 in the first embodiment.
  • FIG. 31 is schematic diagram showing the coating and developing apparatus 1 including the hardening modules FCOT so as to form the lattice-like pattern of holes.
  • the liquid processing block S 3 of the coating and developing apparatus 1 is composed of liquid processing unit block G 1 , G 2 , G 3 , C 4 , G 5 and G 6 , which are stacked in that order from the bottom.
  • the liquid processing unit blocks G 1 , G 3 and G 4 have the same mechanical structure as the liquid processing unit blocks B 1 , B 2 and B 3 in the first embodiment, respectively.
  • the liquid processing unit blocks G 5 and G 6 have the same structural features as the liquid processing unit blocks B 4 and B 5 in the first embodiment except that the former have the developing modules DEV instead of the negative resist-developing modules NDEV of the latter.
  • the liquid processing unit block G 2 has the same structural features as the liquid processing unit block B 1 except that the former has the liquid processing modules FCOT.
  • the main arm D 1 disposed in the heating processing unit blocks C 1 and C 2 can access the transfer modules provided in height positions corresponding to the liquid processing unit blocks G 1 , G 2 , G 3 and G 4 .
  • a wafer W can be transferred between the liquid processing unit blocks G 1 to G 4 and the heating processing unit blocks C 1 and C 2 .
  • the wafer W is transported to the liquid processing unit block G 5 or G 6 so as to be processed.
  • the wafer W is transported to the liquid processing unit block G 5 or G 6 so as to be processed.
  • FIG. 32 shows another modification in which the hardening module FCOT is applied to the first embodiment.
  • the liquid processing unit block G 6 of the liquid processing block S 3 shown herein is provided with the negative resist-developing modules NDEV as liquid processing modules. Except for this difference, the liquid processing block 83 shown in FIG. 32 has the same mechanical structure as the liquid processing block shown in FIG. 31 .
  • the coating and developing apparatus 1 including such a liquid, processing unit block S 3 can also perform the negative development processing mode and the positive development processing mode in a switching manner, and can form a resist pattern in which a number of holes are arranged in a lattice pattern in the respective developing modes, like the second embodiment.
  • the protective film-forming module ITC may supply a chemical liquid for forming an antireflection film, instead of a chemical liquid for forming a protective film, so as to form the antireflection film.
  • the process for repeatedly form resist patterns on one wafer W is not performed.
  • the unit blocks for developing are stacked in two layers, the unit blocks for developing may be stacked in three or more layers, or in only a single layer. Even when the main arm A is shared by the unit blocks for developing as in the first embodiment, as long as the unit block B has a height corresponding to heights of the two other unit blocks B, the unit block B is deemed as a two-layered unit block.

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  • Microelectronics & Electronic Packaging (AREA)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120235335A1 (en) * 2011-03-18 2012-09-20 Tokyo Electron Limited Substrate holding device

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5212443B2 (ja) * 2010-09-13 2013-06-19 東京エレクトロン株式会社 塗布、現像装置、塗布、現像方法及び記憶媒体
JP5901477B2 (ja) * 2012-09-10 2016-04-13 東京エレクトロン株式会社 塗布、現像装置
JP6005604B2 (ja) 2012-09-13 2016-10-12 東京エレクトロン株式会社 現像処理装置
JP5779168B2 (ja) * 2012-12-04 2015-09-16 東京エレクトロン株式会社 周縁部塗布装置、周縁部塗布方法及び周縁部塗布用記録媒体
KR102108307B1 (ko) * 2013-07-26 2020-05-11 세메스 주식회사 기판 처리 설비
US9685357B2 (en) 2013-10-31 2017-06-20 Semes Co., Ltd. Apparatus for treating substrate
KR101579510B1 (ko) * 2013-10-31 2015-12-23 세메스 주식회사 기판 처리 설비
CN108873626B (zh) * 2018-07-02 2021-04-23 京东方科技集团股份有限公司 涂胶显影设备
JP7181068B2 (ja) * 2018-11-30 2022-11-30 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置
JP6994489B2 (ja) * 2019-10-02 2022-01-14 東京エレクトロン株式会社 塗布、現像装置及び塗布、現像方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6299363B1 (en) * 1999-07-05 2001-10-09 Tokyo Electron Limited Substrate processing apparatus
JP2007115831A (ja) 2005-10-19 2007-05-10 Tokyo Electron Ltd 塗布、現像装置及びその方法
US7836845B2 (en) * 2006-04-19 2010-11-23 Tokyo Electron Limited Substrate carrying and processing apparatus
US20120008936A1 (en) * 2010-07-09 2012-01-12 Tokyo Electron Limited Coating and developing apparatus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0230194B2 (ja) * 1986-07-04 1990-07-04 Kyanon Kk Handotaiseizosochi
JP3385325B2 (ja) * 1998-11-09 2003-03-10 日本電気株式会社 格子パターンの露光方法および露光装置
JP4142702B2 (ja) * 2000-09-01 2008-09-03 大日本スクリーン製造株式会社 基板処理装置および基板処理システム
JP3869326B2 (ja) * 2002-03-07 2007-01-17 東京エレクトロン株式会社 現像処理方法
JP3856125B2 (ja) * 2002-05-10 2006-12-13 東京エレクトロン株式会社 処理方法及び処理装置
JP2004207750A (ja) * 2004-02-12 2004-07-22 Dainippon Screen Mfg Co Ltd 基板処理装置
JP2006310376A (ja) * 2005-04-26 2006-11-09 Renesas Technology Corp 半導体集積回路装置の製造方法
JP5323698B2 (ja) * 2007-07-11 2013-10-23 ＡｚエレクトロニックマテリアルズＩｐ株式会社 微細パターン形成用組成物およびそれを用いた微細パターン形成方法
JP4785905B2 (ja) * 2008-11-12 2011-10-05 東京エレクトロン株式会社 基板搬送処理装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6299363B1 (en) * 1999-07-05 2001-10-09 Tokyo Electron Limited Substrate processing apparatus
JP2007115831A (ja) 2005-10-19 2007-05-10 Tokyo Electron Ltd 塗布、現像装置及びその方法
US7661894B2 (en) 2005-10-19 2010-02-16 Tokyo Electron Limited Coating and developing apparatus, and coating and developing method
US7836845B2 (en) * 2006-04-19 2010-11-23 Tokyo Electron Limited Substrate carrying and processing apparatus
US20120008936A1 (en) * 2010-07-09 2012-01-12 Tokyo Electron Limited Coating and developing apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120235335A1 (en) * 2011-03-18 2012-09-20 Tokyo Electron Limited Substrate holding device
US8720873B2 (en) * 2011-03-18 2014-05-13 Tokyo Electron Limited Substrate holding device

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JP5338777B2 (ja) 2013-11-13
US20120057861A1 (en) 2012-03-08

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