US3900597A - System and process for deposition of polycrystalline silicon with silane in vacuum - Google Patents

System and process for deposition of polycrystalline silicon with silane in vacuum Download PDF

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US3900597A
US3900597A US426396A US42639673A US3900597A US 3900597 A US3900597 A US 3900597A US 426396 A US426396 A US 426396A US 42639673 A US42639673 A US 42639673A US 3900597 A US3900597 A US 3900597A
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wafers
tube
silicon
silane
furnace
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US426396A
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Jerry L Chruma
Paul G Hilton
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Motorola Solutions Inc
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Motorola Inc
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Priority to US426396A priority Critical patent/US3900597A/en
Priority to GB5447774A priority patent/GB1470614A/en
Priority to JP49145507A priority patent/JPS5095185A/ja
Priority to CA216,252A priority patent/CA1047850A/en
Priority to DE2460211A priority patent/DE2460211B2/de
Priority to FR7500576A priority patent/FR2255707B1/fr
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Publication of US3900597A publication Critical patent/US3900597A/en
Priority to HK683/80A priority patent/HK68380A/xx
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/006—Apparatus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

Definitions

  • the present invention is directed to the method and means for depositing polycrystalline silicon from silane in a vacuum.
  • This process contemplates the use of a gas source and a means for assuring a uniform flow of gas into the deposition chamber.
  • the deposition chamber is a hot wall furnace.
  • the deposition zone is kept at as uniform a temperature as possible.
  • the preferred temperature is 600C with a workable range extending from 600C to 700C.
  • the deposition zone is profiled flat from a temperature point of view, the deposition rate over the length of the tube appears as a flattened curve. This means that at the source and exhaust portions of the tube, the dep0Sition rates are different from that rate in the central flattened portion.
  • the boat upon which the wafers are placed is centered within the center portion of the curve along its flattest portion. Wafers are placed perpendicular to the gas flow with a preferred spacing approximately 50 mils on center when using wafers 21) mils thick.
  • the wafers are placed in the tube from the source input end. At the gas exhaust end. intermediate the tube and the vacuum pump, is an optical baffle. The function of the optical baffle is to collect the undeposited silane material and silicon lay-products which pass through the tube.
  • the undeposited silane material appears in the form of a brown dust which is granular silicon and silicon monoxide. This granular material forms around the exit end of the tube and in the baffle.
  • the prior art method for forming polycrystalline silicon on wafers is run in a hot-wall furnace using nitrogen gas as the carrier gas and silicon tetrahydride as the source of silicon.
  • the furnace is given a heat profile which resembles a ramp beginning at the source end and increasing towards the exhaust end of the tube.
  • Each furnace is independently profiled such that there is a rain-out profile giving the most uniform front-toback. and sideto-side poly deposition as is possible within the system.
  • the quartz boat is placed in the rain-out area of the furnace and wafers are placed side-by-side with one broad surface on the boat such that the deposition of the polycrystalline silicon occurs over the opposing and upturned second major surface. Because of the placement of the wafers on their flat surfaces, approximately l2 to wafers fit within the deposition zone of the furnace at any one time. Normally, two lines of wafers are placed on the boat. The deposition profile of the polycrystalline material on the wafer appears bell-shaped when taken on a straight line across the wafer and perpendicular to the flow of gas. This means that in the center of the wafer, the polycrystalline material is thickest and at the edge of the wafer. it is thinnest. Normally.
  • an average thickness of 4,500 A. is chosen with the thickest material in the center at 6.000 A. and the edge thickness of the material at 3,000 A.
  • the center portion of 6.000 A. thick material can be too thick for the manufacture of devices on that wafer while the 3.000 thick A. of polycrystalline silicon can be too thin for the successful fabrication of devices. Accordingly. some workable devices are fabricated in the intermediate area where the polycrystalline thickness is typically 4.500 A.
  • a third drawback in this system is the wafers are placed into the furnace from the exit end. the brown, powdered silicon material oftentimes drops off the walls onto the wafer as they are being pulled out of or put into the furnace.
  • the prior art process for deposit polycrystalline on wafers has the problems of low throughut; i.c.. l2 to 20 wafers at a time. non-uniformity of deposition of material $1,500 A. across the surface of the wafers. and the wafers are put in from the exit end of the tube subjecting them to the flaking off of powdered silicon material which then falls onto the wafers either prior to polycrystalline silicon deposition or after such polycrystalline silicon deposition.
  • Such deposition of granular silicon renders the adjacent area unfit for the fabrication of devices.
  • the present invention relates generally to a process and product for the deposition of polycrystalline silicon on a substrate in a heated tube, using a gaseous source and a vacuum and. more particularly, the present invention relates to a process and product for depositing polycrystalline silicon on a substrate in a heated tube using silicon tetrahydride as the source gas. and using a vacuum.
  • substrates used in the manufacture of semiconductor devices at temperatures over 600C such as silicon. germanium, sapphire, spine], ceramic. silicon dioxide, and refractory metals such as tungston. molybdenum.
  • FIG. I shows a schematic view of a standard polycrystalline silicon deposition apparatus
  • FIG. 2 shows the temperature profile used in the apparatus shown in FIG. 1;
  • FIG. 3 shows a deposition curve normally associated with the apparatus shown in FIG. 1;
  • FIG. 4 shows the top view of a typical two-inch wafer shaded to show its non-uniform coating of polycrystalline silicon in a system as shown in FIG. 1;
  • FIG. 5 shows a thickness profile taken along the line 5-5 of the wafer shown in FIG. 4 which is perpendicular to the path of the gas flow;
  • FIG. 6 shows a plurality of thickness profiles taken along the line 6-6 of the wafer shown in FIG. 4 which profiles are along the path of the gas flow at different positions in the tube;
  • FIG. 7 shows the schematic view of the apparatus of the present invention
  • FIG. 8 shows the temperature profile of the apparatus shown in FIG. 7;
  • FIG. 9 shows the deposition profile at a selected temperature
  • FIG. 10 identifies a plurality of locations on a wafer which is coated with different thicknesses of polycrystalline silicon when the wafers are closely spaced on the boat;
  • FIG. 1 1 shows the cross sectional profile of the polycrystalline film along the lines RR', 5-8, and T-T' identified in FIG. 10, and the films are formed in the apparatus shown in FIG. 7, wherein the wafers were spaced approximately 3,000 mils apart;
  • FIG. I2 identifies a plurality of locations on a wafer which is coated with a substantially uniform thickness of polycrystalline silicon material over substantially all of the area of the wafer, when the wafer is spaced from the next adjacent wafer approximately 50 mils on centers using mil thick wafers;
  • FIG. 13 shows the cross sectional profile of the thickness of polycrystalline film above the lines XX' and Y-Y' shown in FIG. 12 of a wafer placed in a furnace of FIG. 7 wherein the spacing between adjacent wafers is on 50 mil centers and the wafers are 20 mils thick;
  • FIG. 14 shows the maximum variations of deposited polycrystalline silicon over the wafer surface as a function of the spacing of the wafers.
  • FIG. I there is shown a source I of nitrogen gas which is the carrier gas for the system and a source of 3 of silicon tetrahydride which is a source of silicon.
  • the furnace tube 5 can be heated by resistance heater coils 7 adjusted to give a temperature profile as shown in FIG. 2.
  • This temperature profile has been chosen in combination with the deposition profile as shown in FIG. 3 such that the highest degree of uniformity of polycrystalline deposition is achieved on the wafers 9 which are placed within the fallout range of the tube as indicated by the line 11 shown in FIG. 1.
  • the fallout range is that area of the tube 5 at which the polycrystalline silicon deposits out of the gas flow through the tube.
  • the temperature within the furnace is such as to decompose the silicon tetrahydride causing the silicon to rainout from the gas stream onto the wafers positioned below.
  • the top view of the wafer having polycrystalline silicon deposited thereon shown in FIG. 4 while a cross section through the wafer taken on the lines 5-5 perpendicular to the gas flow is shown in FIG. 5 and shows the variation in thickness across a single representative wafer. The coverage of the wafers is greatest at the center of the wafer and tapers off to a thinnest portion on the edge of the wafers.
  • FIG. 6 shows the variation in thickness of polycrystalline silicon depending on the location of the wafer within the fallout zone 11.
  • this view shows the temperature profile of the prior art deposition tube.
  • the temperature is established as a ramp beginning at 625C at the source end of the fallout zone identified as A.
  • the central portion B of the fallout zone is set at 650C, while the exhaust end C of the fallout zone is held at 675C.
  • this view shows the deposition thickness profile as a measure of the position of the wafer surface in the fallout zone.
  • This figure shows a variation of first a plus 3,000 A. and then a minus 3,000 A. along the fallout zone.
  • the source end of the fallout zone A shows a thickness of 3,000 A
  • the central point B shows a thickness of 6,000 A.
  • the exhaust end shows a thickness of 3,000 A.
  • the profile is a typical profile for a fixed run of 30 minutes. Larger or shorter runs would give different numbers. Also other factors such as flow rates and temperatures would give different numbers from run to run if minute differences in such run parameters occurred.
  • FIG. 4 shows the top view of a typical 2-inch wafer. Larger or smaller size wafers would have similar shaped profiles in all the views, both in the prior art and in the new system.
  • the source gas is flowing from left to right in FIG. 4.
  • FIG. 5 shows the variation of the polycrystalline deposition across a single wafer along a line perpendicular to the source gas flow. This figure shows that the target thickness is identified as X A. This target thickness is exceeded by a figure of approximately 500 A. in the center Q of the wafer, and the actual thickness falls short by about L000 A. at both edges P and R of the wafer.
  • FIG. 6 shows the variation of polycrystalline silicon thickness across the wafer taken along the direction of gas flow at the center N of a wafer and at both the first edge M and trailing edge 0 depending upon the place rnent of the wafer in the fallout zone 1 1.
  • Curve C shows a generally decreasing thickness for a wafer placed at the exhaust end.
  • Curve B shows a concave variation for the center of the fallout zone.
  • Curve A shows a generally increasing thickness for wafers placed at the source end of the tube.
  • a medium thickness of 4,500 A. is selected such that the thickest portion of the wafer along the line 6-6 of FIG. 4 is approximately 6,000 A. thick, FIG. 3, while the thinnest part of the wafer along the line 55 is at 3,000 A. thick, FIG. 3.
  • This variation in thickness guarantees that certain regions of the wafer have an optimum thickness of the polycrystalline mate rial at 4,500 A. With the optimum thickness, certain usable devices can be made on the wafer. However, it has been found that 3,000 A. can be too thin and 6,000 A. can be too thick for usable device performance.
  • FIG. 7 there is shown a schematic view of the present system wherein the preferred source 20 of semiconductor material is silane in a gaseous form.
  • Other sources can be used as SiC1 H SiClH or SiCl...
  • a flowmeter 22 is provided for metering the correct amount of silane gas flow into the tube and over the wafers.
  • a first source 24 of nitrogen is provided along with a nitrogen flowmeter 26. This flow is normally used at a low flow level to backflush any residual silane remaining within the plumbing lines outside of the furnace since silane is explosive when above a certain temperature and exposed to air.
  • a second source 28 of nitrogen is provided along with a flowmeter 30 for measuring the flow of nitrogen from the source 30 into a tube 32.
  • This source of nitrogen is used for rapidly bringing the evacuated tube 32 up to atmospheric pressure as well as aiding in the initial heating of the wafers. While nitrogen is shown, any inert gas normally used in the processing of semiconductor wafers can be used; i.e., argon, etc. Best results are achieved when the source gas 20 is used along during the deposition of the polycrystalline material. All gases flow in the direction of the arrow 34. An end cap 36 is in engagement with the tube to provide a vacuum seal with the tube. The N and SiH, flows enter the tube 32 at the point where the line 38 pases through an appropriate fitting in the end cap 36. A pressure sensor and vacuum gauge 40 is also attached to the input line 38 for reading the pressure and vacuum at this point.
  • the furnace tube 32 is profiled to exhibit a flat temperature profile as shown in FIG. 8 while the deposition profile is shown with reference to FIG. 9.
  • the usable range of the furnace provides a thickness variation of only 500 A. from the front to the back of the furnace. Referring to FIG. 13 briefly, this figure shows that for any one wafer the thickness is substantially constant over the entire wafer surface when the wafers are stood on edge perpendicular to the gas flow.
  • the embodiment shown with reference to FIG. 7 provides this improved thickness control.
  • the profiling temperature for the furnace shown in FIG. 7 can lie within a tmeperature range anywhere from 600-700 for giving practical results. At temperatures lower than 600, the rate of deposition slows to the point where the run takes too long. However, in those instances where a slow deposition rate can be tolerated, temperatures can be lowered to the minimum temperature at which the silane decomposes. At the upper end of the temperature spectrum; i.e.. above 700C, crystalline imperfections are formed on the surface of the wafers. Such imperfections or outgrowths are formed in a deposition atmosphere in the absence of hydrogen.
  • FIG. 8 shows the preferred temperature profile of the furnace 32 wherein the temperature of 600C is established at the source end A, the center B and the exhaust end C of the deposition zone indicated in FIG. 7 by a line 41.
  • FIG. 9 shows the deposition profile of the system shown in FIG. 7 when the tube is heated to 600C and the deposition run lasts for thirty minutes.
  • the variation from the source end A to the exhaust end B of the deposition zone is 500 A. as indicated by a line 42.
  • the deposition profile within the preferred deposition zone of the tube plus a leading and trailing edge is shown by the curve 43. It has been found that the best results are achieved when the maximum deposition thickness is set at the target thickness and the variations occur on the downward side as shown in FIG. 9. Similar deposition curves are achieved using a target thickness other than 4,500 A.
  • optical baffles 45 are attached at the exhaust end 46 of the quartz tube 32 to trap out the powdered silicon at this point.
  • Wafers 47 are placed into a quartz boat 49 and the loaded boat is loaded into the tube through the source end 51 of the quartz tube 32. In this way contact with the deposited powdered silicon material at the exhaust end 45 of the quartz tube is avoided.
  • the silicon boat carrying the wafers is placed within the preferred portion of the deposition curve, as discussed with reference to FIG. 9.
  • the wafers are placed on end and are placed with their broad surface perpendicular to the gas flow.
  • FIG. 14 shows the maximum variation across the wafer as a function of wafer spacing.
  • a preferable open space distance of 30 mils between adjacent surfaces of adjacent wafers has been selected as the preferable distance.
  • a polycrystalline silicon layer is formed on a wafer shown in H0. 12 having a deposition profile as shown in FIG. 13.
  • a line 55 shows the thickness variation in both the X-X' and Y-Y' directions as shown-in FIG. 12. This shows an essentially uniform thickness of polycrystalline silicon material deposited across the major portion of the wafer. It is only at the edge points 61a and 61b of the curve 55 shown in FIG.
  • the thickness of the polycrystalline material across the major surface between the lines is essentially uniform while the difference in thickness from wafer to wafer from the source end of the deposition zone to the exhaust end of the deposition zone differs by a total of 500 A. as shown with reference to FIG. 9.
  • the operation of the system shown in FIG. 7 has the following special steps.
  • the vacuum identified as the preferred vacuum level lies within the range of 600 to 1,600 millitorr.
  • Nitrogen from source 24 is always used to purge any residual SiH, left in the system once the Sil-l is turned off.
  • Nitrogen from the source 28 is used to break the vacuum and establish atmospheric pressure within the tube 32.
  • gaseous silicon source is selected from SiH SiCl H SiCl and SiCl.,.
  • the wafer to be covered with polycrystalline silicon is selected from silcion, germanium, sapphire, spinel, ceramic, silicon dioxide, tungsten and molybdenum.
  • a method of forming a polycrystalline silicon layer upon a plurality of silicon wafers comprising the steps of:
  • l0. ln a method for depositing polycrystalline silicon material onto a wafer which has a layer of silicon dioxide formed on a first major surface of the wafer, and the silicon is obtained from a gaseous silane source flowing through a heated furnace tube, and the tube has a first end into which the gaseous silicon is added to the tube,
  • the tube is further equipped with a second end from which the residual gaseous silane is exhausted.

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US426396A 1973-12-19 1973-12-19 System and process for deposition of polycrystalline silicon with silane in vacuum Expired - Lifetime US3900597A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US426396A US3900597A (en) 1973-12-19 1973-12-19 System and process for deposition of polycrystalline silicon with silane in vacuum
GB5447774A GB1470614A (en) 1973-12-19 1974-12-17 Process for deposition of polycrystalline silicon
JP49145507A JPS5095185A (de) 1973-12-19 1974-12-18
CA216,252A CA1047850A (en) 1973-12-19 1974-12-19 System and process for deposition of polycrystalline silicon with silane in vacuum
DE2460211A DE2460211B2 (de) 1973-12-19 1974-12-19 Verfahren zum chemischen Abscheiden von polykristallinem Silicium aus der Gasphase
FR7500576A FR2255707B1 (de) 1973-12-19 1975-01-09
HK683/80A HK68380A (en) 1973-12-19 1980-12-04 A process for deposition of polycrystalline silicon

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US426396A US3900597A (en) 1973-12-19 1973-12-19 System and process for deposition of polycrystalline silicon with silane in vacuum

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JP (1) JPS5095185A (de)
CA (1) CA1047850A (de)
DE (1) DE2460211B2 (de)
FR (1) FR2255707B1 (de)
GB (1) GB1470614A (de)
HK (1) HK68380A (de)

Cited By (49)

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US4027053A (en) * 1975-12-19 1977-05-31 Motorola, Inc. Method of producing polycrystalline silicon ribbon
US4048954A (en) * 1975-09-04 1977-09-20 Siemens Aktiengesellschaft Coating device for small electrically conductive components
US4053335A (en) * 1976-04-02 1977-10-11 International Business Machines Corporation Method of gettering using backside polycrystalline silicon
US4082865A (en) * 1976-11-19 1978-04-04 Rca Corporation Method for chemical vapor deposition
US4098923A (en) * 1976-06-07 1978-07-04 Motorola, Inc. Pyrolytic deposition of silicon dioxide on semiconductors using a shrouded boat
US4164436A (en) * 1977-07-22 1979-08-14 Hitachi, Ltd. Process for preparation of semiconductor devices utilizing a two-step polycrystalline deposition technique to form a diffusion source
US4203387A (en) * 1978-12-28 1980-05-20 General Signal Corporation Cage for low pressure silicon dioxide deposition reactors
US4228004A (en) * 1979-04-12 1980-10-14 Thermco Products Corporation Method and apparatus for removal of by-products of chemical vapor deposition from oil for vacuum pump
US4263087A (en) * 1979-02-19 1981-04-21 Fujitsu Limited Process for producing epitaxial layers
US4263336A (en) * 1979-11-23 1981-04-21 Motorola, Inc. Reduced pressure induction heated reactor and method
US4315968A (en) * 1980-02-06 1982-02-16 Avco Corporation Silicon coated silicon carbide filaments and method
US4367768A (en) * 1979-02-24 1983-01-11 Heraeus Quarzschmelze Gmbh Refractory protective tube for the heat treatment of semiconductor components
DE3235503A1 (de) * 1981-11-12 1983-05-19 Advanced Semiconductor Materials America, Inc., 85040 Phoenix, Ariz. Verbesserte abscheidung von silizium aus einem plasma
US4388342A (en) * 1979-05-29 1983-06-14 Hitachi, Ltd. Method for chemical vapor deposition
US4444812A (en) * 1980-07-28 1984-04-24 Monsanto Company Combination gas curtains for continuous chemical vapor deposition production of silicon bodies
US4449037A (en) * 1978-10-31 1984-05-15 Fujitsu Limited Method and apparatus for heating semiconductor wafers
US4489103A (en) * 1983-09-16 1984-12-18 Rca Corporation SIPOS Deposition method
US4509456A (en) * 1981-07-28 1985-04-09 Veb Zentrum Fur Forschung Und Technologie Mikroelektronik Apparatus for guiding gas for LP CVD processes in a tube reactor
US4547404A (en) * 1982-08-27 1985-10-15 Anicon, Inc. Chemical vapor deposition process
US4556584A (en) * 1984-05-03 1985-12-03 Btu Engineering Corporation Method for providing substantially waste-free chemical vapor deposition of thin-film on semiconductor substrates
US4597160A (en) * 1985-08-09 1986-07-01 Rca Corporation Method of fabricating a polysilicon transistor with a high carrier mobility
US4734297A (en) * 1984-10-30 1988-03-29 Rhone-Poulenc Specialites Chimiques Production of shaped articles of ultra-pure silicon
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US4853669A (en) * 1985-04-26 1989-08-01 Wisconsin Alumni Research Foundation Sealed cavity semiconductor pressure transducers and method of producing the same
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US5026574A (en) * 1986-03-19 1991-06-25 The General Electric Company, P.L.C. Chemical vapor deposition process for depositing large-grain polysilicon films
US5298452A (en) * 1986-09-12 1994-03-29 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US5906680A (en) * 1986-09-12 1999-05-25 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US4897360A (en) * 1987-12-09 1990-01-30 Wisconsin Alumni Research Foundation Polysilicon thin film process
US5181964A (en) * 1990-06-13 1993-01-26 International Business Machines Corporation Single ended ultra-high vacuum chemical vapor deposition (uhv/cvd) reactor
US5112773A (en) * 1991-04-10 1992-05-12 Micron Technology, Inc. Methods for texturizing polysilicon utilizing gas phase nucleation
US5874129A (en) * 1991-08-09 1999-02-23 Applied Materials, Inc. Low temperature, high pressure silicon deposition method
US5614257A (en) * 1991-08-09 1997-03-25 Applied Materials, Inc Low temperature, high pressure silicon deposition method
US5607724A (en) * 1991-08-09 1997-03-04 Applied Materials, Inc. Low temperature high pressure silicon deposition method
US5695819A (en) * 1991-08-09 1997-12-09 Applied Materials, Inc. Method of enhancing step coverage of polysilicon deposits
US5753559A (en) * 1996-01-16 1998-05-19 United Microelectronics Corporation Method for growing hemispherical grain silicon
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US6479166B1 (en) 1998-10-06 2002-11-12 Case Western Reserve University Large area polysilicon films with predetermined stress characteristics and method for producing same
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US6268068B1 (en) 1998-10-06 2001-07-31 Case Western Reserve University Low stress polysilicon film and method for producing same
US6564810B1 (en) 2000-03-28 2003-05-20 Asm America Cleaning of semiconductor processing chambers
US6666924B1 (en) 2000-03-28 2003-12-23 Asm America Reaction chamber with decreased wall deposition
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US20050250302A1 (en) * 2001-02-12 2005-11-10 Todd Michael A Thin films and methods of making them
US7026219B2 (en) 2001-02-12 2006-04-11 Asm America, Inc. Integration of high k gate dielectric
US8067297B2 (en) 2001-02-12 2011-11-29 Asm America, Inc. Process for deposition of semiconductor films
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US7285500B2 (en) * 2001-02-12 2007-10-23 Asm America, Inc. Thin films and methods of making them
US20050233529A1 (en) * 2001-02-12 2005-10-20 Pomarede Christophe F Integration of high k gate dielectric
US7893433B2 (en) 2001-02-12 2011-02-22 Asm America, Inc. Thin films and methods of making them
US7547615B2 (en) 2001-02-12 2009-06-16 Asm America, Inc. Deposition over mixed substrates using trisilane
US7790556B2 (en) 2001-02-12 2010-09-07 Asm America, Inc. Integration of high k gate dielectric
US20080047877A1 (en) * 2001-08-07 2008-02-28 Freissle Manfred Franz A Screening Arrangement
US7651953B2 (en) 2002-07-19 2010-01-26 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
US20090311857A1 (en) * 2002-07-19 2009-12-17 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
US20080038936A1 (en) * 2002-07-19 2008-02-14 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
US7964513B2 (en) 2002-07-19 2011-06-21 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
US8921205B2 (en) 2002-08-14 2014-12-30 Asm America, Inc. Deposition of amorphous silicon-containing films
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US20040124131A1 (en) * 2002-09-11 2004-07-01 Aitchison Bradley J. Precursor material delivery system for atomic layer deposition
US9443730B2 (en) 2014-07-18 2016-09-13 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
US9837271B2 (en) 2014-07-18 2017-12-05 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
US10460932B2 (en) 2017-03-31 2019-10-29 Asm Ip Holding B.V. Semiconductor device with amorphous silicon filled gaps and methods for forming
CN115613007A (zh) * 2022-10-13 2023-01-17 上海中欣晶圆半导体科技有限公司 一种改善翘曲的成膜方法

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DE2460211A1 (de) 1975-11-06
DE2460211B2 (de) 1979-05-23
GB1470614A (en) 1977-04-14
CA1047850A (en) 1979-02-06
JPS5095185A (de) 1975-07-29
FR2255707A1 (de) 1975-07-18
FR2255707B1 (de) 1978-06-23
HK68380A (en) 1980-12-12

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