CA1047850A - System and process for deposition of polycrystalline silicon with silane in vacuum - Google Patents
System and process for deposition of polycrystalline silicon with silane in vacuumInfo
- Publication number
- CA1047850A CA1047850A CA216,252A CA216252A CA1047850A CA 1047850 A CA1047850 A CA 1047850A CA 216252 A CA216252 A CA 216252A CA 1047850 A CA1047850 A CA 1047850A
- Authority
- CA
- Canada
- Prior art keywords
- wafers
- silicon
- tube
- silane
- flow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 42
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 229910000077 silane Inorganic materials 0.000 title claims abstract description 31
- 230000008021 deposition Effects 0.000 title abstract description 45
- 235000012431 wafers Nutrition 0.000 claims abstract description 142
- 238000000151 deposition Methods 0.000 claims abstract description 63
- 239000010703 silicon Substances 0.000 claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 239000000463 material Substances 0.000 claims abstract description 15
- 230000003287 optical effect Effects 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000002210 silicon-based material Substances 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 10
- 239000011261 inert gas Substances 0.000 claims description 7
- 230000008450 motivation Effects 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910003915 SiCl2H2 Inorganic materials 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 229910052596 spinel Inorganic materials 0.000 claims description 2
- 239000011029 spinel Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000011010 flushing procedure Methods 0.000 claims 2
- 230000006872 improvement Effects 0.000 claims 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 1
- 229910003910 SiCl4 Inorganic materials 0.000 claims 1
- 230000000694 effects Effects 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 claims 1
- PPDADIYYMSXQJK-UHFFFAOYSA-N trichlorosilicon Chemical compound Cl[Si](Cl)Cl PPDADIYYMSXQJK-UHFFFAOYSA-N 0.000 claims 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 abstract 2
- 239000006227 byproduct Substances 0.000 abstract 1
- 239000000428 dust Substances 0.000 abstract 1
- 239000008187 granular material Substances 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 20
- 229960005419 nitrogen Drugs 0.000 description 11
- 239000010453 quartz Substances 0.000 description 10
- 229910052757 nitrogen Inorganic materials 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- QYKABQMBXCBINA-UHFFFAOYSA-N 4-(oxan-2-yloxy)benzaldehyde Chemical compound C1=CC(C=O)=CC=C1OC1OCCCC1 QYKABQMBXCBINA-UHFFFAOYSA-N 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000009428 plumbing Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/24—Deposition of silicon only
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/006—Apparatus
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/122—Polycrystalline
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Mechanical Engineering (AREA)
- Materials Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical Vapour Deposition (AREA)
- Silicon Compounds (AREA)
Abstract
SYSTEM AND PROCESS FOR DEPOSITION
OF POLYCRYSTALLINE SILICON
WITH SILANE IN VACUUM
ABSTRACT OF THE DISCLOSURE
The present invention is directed to the method and means for depositing polycrystalline silicon from silane in a vacuum. This process contemplates the use of a gas source and a means for assuring a uniform flow of gas into the deposition chamber. The deposition chamber is a hot wall furnace. The deposition zone is kept at as uniform a tem-perature as possible. The preferred temperature is 600°C
with a workable range extending from 600°C to 700°C. While the deposition zone is profiled flat from a temperature point of view, the deposition rate over the length of the tube appears as a flattened curve. This means that at the source and exhaust portions of the tube, the deposition rates are different from that rate in the central flattened portion. The boat upon which the wafers are placed is centered within the center portion of the curve along its flattest portion. Wafers are placed perpendicular to the gas flow with a preferred spacing approximately 50 mils on center when using wafers 20 mils thick. The wafers are placed in the tube from the source input end. At the gas exhaust end, intermediate the tube and the vacuum pump, is an optical baffle. The function of the optical baffle is to collect the undeposited silane material and silicon by-products which pass through the tube. The undeposited silane material appears in the form of a brown dust which is granular silicon and silicon monoxide. This granular material forms around the exit end of the tube and in the baffle.
OF POLYCRYSTALLINE SILICON
WITH SILANE IN VACUUM
ABSTRACT OF THE DISCLOSURE
The present invention is directed to the method and means for depositing polycrystalline silicon from silane in a vacuum. This process contemplates the use of a gas source and a means for assuring a uniform flow of gas into the deposition chamber. The deposition chamber is a hot wall furnace. The deposition zone is kept at as uniform a tem-perature as possible. The preferred temperature is 600°C
with a workable range extending from 600°C to 700°C. While the deposition zone is profiled flat from a temperature point of view, the deposition rate over the length of the tube appears as a flattened curve. This means that at the source and exhaust portions of the tube, the deposition rates are different from that rate in the central flattened portion. The boat upon which the wafers are placed is centered within the center portion of the curve along its flattest portion. Wafers are placed perpendicular to the gas flow with a preferred spacing approximately 50 mils on center when using wafers 20 mils thick. The wafers are placed in the tube from the source input end. At the gas exhaust end, intermediate the tube and the vacuum pump, is an optical baffle. The function of the optical baffle is to collect the undeposited silane material and silicon by-products which pass through the tube. The undeposited silane material appears in the form of a brown dust which is granular silicon and silicon monoxide. This granular material forms around the exit end of the tube and in the baffle.
Description
il~4785V
BACKGROUND OF THE INVENTION
The prior art method for forming polycrystalline silicon on wafers is run in a hot-wall furnace using nitro-gen gas as the carrier gas and silicon tetrahydride as the source of silicon. The furnace is given a heat profile which resembles a ramp beginning at the source end and increasing towards the exhaust end of the tube. Each furnace is independently profiled such that there is a rain-out profile giving the most uniform front-to-back, and side-to-side poly deposition as is possible within the system.
According to the prior art practice, the quartz boat is placed in the rain-out area of the furnace and wafers are placed side-by-side with one broad surface on the boat such that the deposition of the polycrystalline silicon occurs over the opposing and upturned second major surface.
Because of the placement of the wafers on their flat sur-faces, approximately 12 to 20 wafers fit within the deposi-tion zone of the urnace at any one time. Normally, two lines of wafers are placed on the boat. The deposition profile of the polycrystalline material on the wafer appears bell-shaped when taken on a straight line across the wafer and perpendicular to the flow of gas. This means that in ~ -the center of the wafer, the polycrystalline material is thicke~t and at the edge of the wafer, it is thinnest.
Normally, an average thickness of 4500 Angstroms is chosen ~ ~-with the thickest material in the center at 6000 Angstroms and the edge thickness of the material at 3000 Angstroms.
In practice, the center portion of 6000 Angstroms thick ~;
material can be too thick for the manufacture of devices on that wafer while the 3000 thick Angstroms of polycrystalline silicon can be too thin for the successful fabrication of - -- .
.
.
~0478S~
devices. Accordingly, some workable devices are fabricated in the intermediate area where the polycrystalline thickness is typically 4500 Angstroms. A third drawback in this system is the wafers are placed into the furnace from the exit end, the brown, powdered silicon material oftentimes drops off the walls onto the wafer as they are being pulled out of or put into the furnace. The buildup of such powdered silicon material on the quartz tube is so rapid that normally a maximum of ten to twenty runs can be made using the same quartz tube. When the quartz tube is pulled from the furnace to be cleaned, the coefficient of expansion between the quartz and the silicon is so great that the quartz tube breaks and a new center section must be fused with the unbroken end sections as to reuse these two end portions of the tube.
In summary, the prior art process for deposit poly-crystalline on wafers has the problems of low throughput;
i.e., 12 to 20 wafers at a time, non-uniformity of deposi-tion of material +1500 Angstroms across the surface of the wafers, and the wafers are put in from the exit end of the tube subjecting them to the flaking off of powdered silicon material which then falls onto the wafers either prior to polycrystalline silicon deposition or after such polycrys-talline silicon deposition. Such deposition of granular silicon renders the adjacent area unfit for the fabrication of devices.
SUMMARY OF THE INVENTION
The present invention relates generally to a process and product for the deposition of polycrystalline silicon on a substrate in a heated tube, using a gaseous source and 1~347850 a vacuum and, more particularly, the present invention relates to a process and product for depositing polycrystal-line silicon on a substrate in a heated tube using silicon tetrahydride as the source gas, and using a vacuum.
It is an object of the present invention to provide a new improved method for depositing polycrystalline silicon on a substrate using a heated tube and a vacuum.
It is an additional object of the present invention to ;
provide a hot-wall furnace tube having a flat temperature profile in the hot zone of the tube which results in the deposition of a uniform thickness of polycrystalline silicon over the major portion of the surface of the wafer.
It is still a further object of the present invention to provide a method for depositing polycrystalline silicon from silane in a hot-wall furnace tube with improved uni-formity as compared to that presently possible.
It is another object of the present invention to pro~
vide a means and a method for depositing polycrystalline silicon from silane at a uniform rate over the wafer with a tolerance of better than 500 Angstroms from edge to edge of a single wafer.
It is still a further object of the present invention to provide a method for depositing polycrystalline silicon on wafers within a hot-wall furnace tube for increasing the throughput capacity of the furnace. ~-~
It is a further object of the present invention to provide a method for depositing polycrystalline silicon on wafers in a hot-wall tube such that the major surface of the wafers contain a uniform thickness of the polycrystalline ~
silicon over a~ great a region as possible. -It is another object of the present invention to pro-vide a method for depositing polycrystalline silicon on ~ - -lQ47850 wafers in a furnace wherein the wafers are placed on edge and their broad major surfaces are then placed perpendicular to the flow of the source gas and the wafers are placed closer together than previously thought possible.
It is an additional object of the present invention to provide a method for depositing polycrystalline silicon on many different substrates used in the manufacture of semi-conductor devices at temperatures over 600C, such as sili-con, germaniumj-sapphire, spinel, ceramic, silicon dioxide, and refractory metals such-as tungsten,-molybdenum.
It is a stil-l further object of the present invention to provide a method of depositing polycrystalline silicon in -a heated tube, which method is independent of the means for heating the tube and heating means such as RF, resistance or radiant heat can be used.
It is another object-of the present invention to pro~
vide a method for depositing polycrystalline silicon on a substrate using several gas sources such as silane, SiC12H2, SiClH3, and SiC14.
It is a further object of the present invention to -provide-a method for deposi-ti-ng polycrystalline silicon in a heated evacuated tube under a vacuum on a substrate and using a gaseous source, wherein the spacing of the wafers is minimized for increasing the throughput of the method.
The invention of a method of forming a polycrystalline silicon layer upon a plurality of silicon wafers, comprises the steps of placing a plurality of silicon wafers in a closed container; establishing a uniform temperature throughout a portion of the closed container, said temperature being less than 700C, and said wafers being placed within the uniform temperature portion of the container; placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance greater than 30 mils; and passing ~ ' ~ _ 5 _ , : .
a gas stream of silane over ~he heated wafers under the motivation of a vacuum. Preferably the vacuum is established between the range of 600 to 1600 millitorr.
More particularly, ~here is provided:-a method of forming a polycrystalline silicon layer upon a plurality of silicon wafers, comprising the steps of:
placing a plurality of silicon wafers in a closed container;
heating said wafers to a temperature less than 700C;
passing a gas stream of silane over the heated wafers under the motivation of a vacuum established between the range of 600 to 1600 millitorr; and placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance greater than 30 mils. -There is also provided:-a method of forming a polycrystalline silicon layer upon a plurality of d licon wafers, comprising the teps of:
placing a plurality of s~licon wafers in a closed container;
heating said wafers to a temperature less than 700--C, placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance600 to 1600 mlllitorr; and ~ ~ -pass~ng 8 gas stream of silane over the heated --w~fers under the motivation of a vacuum.
~ 5a '~ .
1~47850 DESCRIPTION OF THE FIGURES
Fig. 1 shows a schematic view of a standard polycrys-talline silicon deposition apparatus;
Fig. 2 shows the temperature profile used in the apparatus shown in Fig. l; ~ ~
Fig. 3 shows a deposition curve normally associated ~ -with the apparatus shown in Fig. l;
D~
, 1~)47850 Fig. 4 shows the top view of a typical two-inch wafer shaded to show its non-uniform coating of polycrystalline silicon in a system as shown in Fig. 1;
Fig. 5 shows a thickness profile taken along the line 5-5 of the wafer shown in Fig. 4 which is perpendicular to the path of the gas flow;
Fig. 6 shows a plurality of thickness profiles taken along the line 6-6 of the wafer shown in Fig. 4 which pro-files are along the path of the gas flow at different posi-tions in the tube;
Fig. 7 shows the schematic view of the apparatus of the present invention;
Fig. 8 shows the temperature profile of the apparatus shown in Fig. 7;
Fig. 9 shows the deposition profile at a selected temperature;
Fig. 10 identifies a plurality of locations on a wafer -~
which is coated with different thicknesses of polycrystal-line silicon when the wafers are closely spaced on the boat;
Fig. 11 shows the cross sectional profile of the poly-crystalline film along the lines R-R, S-S, and T-T identi-fied in Fig. 10, and the films are formed in the apparatus shown in Fig. 7, wherein the wafers were spaced approxi-mately 3000 mils apart;
Fig. 12 identifies a plurality of locations on a wafer which is coated with a substantially uniform thickness of polycrystalline silicon material over substantially all of the area of the wafer, when the wafer is spaced from the next adjacent wafer approximately 50 mils on centers using 20 mil thick wafers;
.
.
Fig. 13 shows the cross-sectional profile of the thick-ness of polycrystalline film above the lines X-X and Y-Y
shown in Fig. 12 of a wafer placed in a furnace of Fig. 7 wherein the spacing between adjacent wafers is on 50 mil centers and the wafers are 20 mils thick; --Fig. 14 shows the maximum variations of deposited poly-crystalline silicon over the wafer surface as a function of the spacing of the wafers.
BRIEF DESCRIPTION OF THE INVENTION
In the prior art system of depositing polycrystalline silicon, as shown with reference to Fig~ 1, there is shown a source 1 of nitrogen gas which is the carrier gas for the system and a source 3 of silicon tetrahydride which is a source of silicon. The furnace tube 5 can be heated by resistance heater coils 7 adjusted to give a temperature profile as shown in Fig. 2. This temperature profile has been chosen in combination with the deposition profile as shown in Fig. 3 such that the highest degree of uniformity of polycrystalline deposition is achieved on the wafers 9 which are placed within the fallout range of the tube as indicated by the line 11 shown in Fig. 1. The fallout range is that area of the tube 5 at which the polycrystalline silicon deposits out of the gas flow through the tube. The temperature within the furnace is such as to decompose the silicon tetrachloride causing the silicon to rainout from the gas stream onto the wafers positioned below. The top view of the wafer having polycrystalline silicon deposited thereon shown in Fig. 4 while a cross section through the wafer taken on the lines 5-5 perpendicular to the gas flow is shown in Fig. 5 and shows the variation in thickness lQ47850 across a single representative wafer. The coverage of the wafers is greatest at the center of the wafer and tapers off t~ a thinnest portion on the edge of the wafers. Fig. 6 shows the variation in thickness of polycrystalline silicon depending on the location of the wafer within the fallout zone 11.
Referring again to Fig. 2, this view shows the tempera-ture profile of the prior art deposition tube. The tempera-ture is established as a ramp beginning at 625C at the source end of the fallout zone identified as A. The central portion B of the fallout zone is set at 650C, while the exhaust end C of the fallout zone is held at 675C.
Referring again to Fig. 3, this view shows the deposi-tion thickness profile as a measure of the position of the wafer surface in the fallout zone. This figure shows a variation of first a plus 3000 Angstroms and then a minus 3000 Angstroms along the fallout zone, The source end of the fallout zone A shows a thickness of 3000 Angstroms, while the central point B shows a thickness of 6000 Ang-stroms and the exhaust end shows a thickness of 3000 Ang-stroms. While it is possible to build devices with the thickness of polycrystalline silicon over the entire range as shown in Fig. 3, it is impractical from a commercial viewpoint to identify and sort the individual die according to thickness. It is not uncommon to have several hundred die to a wafer. The actual identification and sorting of these die is too costly. Again the profile is a typical profile for a fixed run of 30 minutes, Larger or shorter runs would give different numbers. Also other factors such as flow rates and temperatures would give different numbers from run to run if minute differences in such run parameters occurred.
- 8 - ;
' 1~47850 Fig. 4 shows the top view of a typical two-inch wafer.
Larger or smaller size wafers would have similar shaped pro-files in all the views, both in the prior art and in the new , system. The source gas is flowing from left to right in Fig. 4.
Fig. 5 shows the variation of the polycrystalline depo-sition across a single wafer along a line perpendicular to the source gas flow. This figure shows that the target thickness is identified as ~ Angstroms. This target thick-ness is exceeded,by a figure of approximately 500 Angstroms in the center Q of the wafer, and the actual thickness falls short by about 1000 Angstroms at both edges P and R of the wafer.
Fig. 6 shows the variation of polycrystalline silicon thickness across the wafer taken along the direction of gas ,~
flow at the center N of a wafer and at both the first edge M
and txailing edge O depending upon the placement of the wafer in the fallout zone 11. Curve C shows a generally decreas- ' ing thickness for a wafer placed at the exhaust end. Curve B
shows a concave variation'for the center of the fallout zone.
Curve A shows a generally increasing thickness for wafers placed at the source end of the tube.
In operation, a medium thickness of 4500 Angstroms is selected such that the thickest portion of the wafer along the line 6-6 of Fig. 4 is approximately 6000 Angstroms thick, Fig. 3, while the thinnest part of the wafer along the line 5-5 is at 3000 Angstroms thick, Fig. 3. This variation in thickness guarantees that certain regions of the wafer have an optimum thickness of the polycrystalline material at 4500 Angstroms. With the optimum thickness, certain usable devices can be made on the wafer. However, it has been found that 1~47850 3000 Angstroms can be too thin and 6000 Angstroms can be too thick for usable device performance.
Accordingly, it is desirable to form a polycrystalline layer with a more optimum thickness over a greater portion of the wafer. In the system shown in Fig. 1 only 12 to 20 wafers can be passed through the system at one time because of the size of the tube and the size of the fallout zone. ~-Since the wafers must lie on a major surface with the poly-crystalline material raining out from the gas stream upon the upper or opposite major surface of a substrate, the physical limitation of the system is 12 to 20 wafers.
Another drawback on the system shown with reference to Fig. 1 is the fact that the wafers are put in through the -exhaust end 13 of the tube. When the wafers are being put in, as well as when the wafers are taken out, some of the powdered silicon material flecks off of the walls of the tube at the end 13 and become deposited on the wafers. This means that any polycrystalline material grown over that powdered piece of silicon would be unsuitable for the forma-tion of semiconductor devices. Also, any flecks of powdered -silicon fallingon a newly grown polycrystalline layer adversely affects the use of that area for an active device. ~-Referring to Fig. 7 there is shown a schematic view of -~
the present system wherein the preferred source 20 of semi-conductor material is silane in a gaseous form. Other ~
sources can be used as SiCl2H2, SiClH3 or SiC14. A flow- ~ -meter 22 i8 provided for metering the correct amount of silane gas flow into the tube and over the wafers. A first source 24 of nitrogen is provided along with a nitrogen flowmeter 26. This flow is normally used at a low flow level to backflush any residual silane remaining within the , , : ............................. ~ . : .
:, :' . - : : ~ .
:1~)478SO :
plumbing lines outside of the furnace since silane is explo- -sive when above a certain temperature and exposed to air.
A second source 28 of nitrogen is provided along with a flowmeter 30 for measuring the flow of nitrogen from the source 30 into a tube 32. This source of nitrogen is used for rapidly bringing the evacuated tube 32 up to atmospheric pressure as well as aiding in the initial heating of the wafers. While nitrogen is shown, any inert gas normally used in the processing of semiconductor wafers can be used;
i.e., argon, etc. Best results are achieved when the source gas 20 is used alone during the deposition of the ~
polycrystalline material. All gases flow in the direction ~-of the arrow 34. An end cap 36 is in engagement with the tube to provide a vacuum seal with the tube. The N2 and SiH4 flows enter the tube 32 at the point where the line 38 passes through an appropriate fitting in the end cap 36. A
pressure sensor and vacuum gauge 40 is also attached to the ~ --input line 38 for reading the pressure and vacuum at this point. The furnace tube 32 is profiled to exhibit a flat ~
temperature profile as shown in Fig. 8 while the deposition - -profile is shown with reference to Fig. 9. This means that the flattened curve shown in Fig. 9 represents the variation in the thickness of polycrystalline silicon material deposited on a wafer when positioned at any location within the entire heated zone of the furnace. The usable range of the furnace proyides a thickness variation of only 500 Angstroms from the front to the back of the furnace. Refer- ~ -ring to Fig. 13 briefly, this figure shows that for any one wafer the thickness is substantially constant over the entire wafer surface when the wafers are stood on edge perpendicular to the gas flow. The embodiment shown with , . . . . .
- , . :
.- , , ,.,,: . : ' . .
1~47850 reference to Fig. 7 provides this improved thickness control.
The profiling temperature for the furnace shown in Fig. 7 can lie within a temperature range anywhere from 600-700 for giving practical results. At temperatures lower than 600, the rate of deposition slows to the point where the run takes too long. However, in those instances where a slow deposition rate can be tolerated, temperatures can be lowered to the minimum temperature at which the silence decomposes. At the upper end of the temperature spectrum; i.e., above 700C, crystalline imperfections are formed on the surface of the wafers. Such imperfections or outgrowths are formed in a deposition atmosphere in the absence of hydrogen. Fig. 8 shows the preferred temperature profile of the furnace 32 wherein the temperature of 600C
is established at the source end A, the center B and the exhaust end C of the deposition zone indicated in Fig. 7 by a line 41.
Fig. 9 shows the deposition profile of the system shown in Fig. 7 when the tube is heated to 600C and the deposi-tion run lasts for thirty minutes. The variation from the source end A to the exhaust end B of the deposition zone is 500 Angstroms as indicated by a line 42. The deposition profile within the preferred deposition zone of the tube plu9 a leading and trailing edge is shown by the curve 43.
It has been found that the best results are achieved when the maximum deposition thickness is set at the target thick-ness and the variations occur on the downward side as shown in Fig. 9. Similar deposition curves are achieved using a target thickness other than 4500 Angstroms.
In some early experiments a cold trap cooled by liquid nitrogen was used to remove the silane before it was vented into the vacuum pump 44 shown in Fig. 7. This was to pre-.
- 1~47850 -vent damage to the vacuum apparatus. However, the cold trap was allowed to warm after the deposition run was completed it was damaged by the spontaneous burning of the silane as it warmed and became exposed to air.
Accordingly, optical baffles 45 are attached at the exhaust end 46 of the quartz tube 32 to trap out the powdered silicon at this point. Wafers 47 are placed into a quartz boat 49 and the loaded boat is loaded into the tube through the source ~nd 51 of the quartz tube 32. In this way contact with the deposited powdered silicon material at the exhaust end 45 of the quartz tube is avoided. The silicon boat carrying the wafers is placed within the pre-ferred portion of the deposition curve, as discussed with reference to Fig. 9. The wafers are placed on end and are placed with their broad surface perpendicular to the gas .... .... . .
flow.
In earlîer experiments, wafers were placed at greater distances and wafers were manufactured having the top view as shown in Fig. 10. The upper portion of the wafer indi-cated by the line S-S has a uniform amount of material deposited thereon, as shown by a comparison curve S-S' in -Fig. 11, but the lower portion indicated by the line R-R was substantially non-uniform and unusable as shown by the comparison curve R-R' in Fig. 11. Additionally, a thickness variation also occurred from the top to the bottom of the wafer as indicated by the line T-T in Figs, 10 and 11. The spacing which gave the results illustrated in Fig. 11 was 3000 mils~ It should be kept in mind that the length of the spacing between wafers is that distances between midpoints - - -of the thickness of adjacent wafers. When two wafers are 20 mils thick and the spacing is given as 50 mils, there is actually a 30 mil open area between the rear surface of the .
~V47850 first wafer and the front surface of the next wafer.
Accordingly, if thicker wafers are used, the spacings would change also. This change would only be significant at the upper and lower limits as in between it does not matter. It is recommended that the actual spacing of 30 mils from surface to surface should not be made smaller. At the upper limit, minimum acceptable depositions on the top half of wafers were achieved at actual back surface to front surface spacing of 2980 mils.
Accordingly, many experiments were run to ascertain the optimum spacing of the wafers side-by-side. This informa-tion is shown in Fig. 14 by the line 53. This curve shows the maximum variation across the wafer as a function of wafer spacing. A preferable open space distance of 30 mils between adjacent surfaces of adjacent wafers has been selected as the preferable distance. A polycrystalline silicon layer is formed on a wafer shown in Fig. 12 having a deposition profile as shown in Fig. 13. A line 55 shows the thickness variation in both the X-X~ and Y-Y~ directions as shown in Fig. 12. This shows an essentially uniform thickness of polycrystalline silicon material deposited across the major portion of the wafer. It is only at the edge points 61a and 61b of the curve 55 shown in Fig. 13 that a slight increase in thickness is found, It should be emphasized that the thickness of the polycrystalline - -material across the major surface between the lines is -essentially uniform while the difference in thickness from ~ -wafer to wafer from the source end of the deposition zone to the exhaust end of the deposition zone differs by a total - -of 500 Angstroms as shown with reference to Fig. 9.
In the impro~ed system as shown with reference to Fig. 7, approximately 250 wafers can be placed on a 12-inch .. . . .
1~47BSO
boat. This is a throughput greater than 10 to 1 as compared with the prior art method of forming polycrystalline silicon material.
The operation of the system shown in Fig. 7 has the following special steps. The vacuum identified as the preferred vacuum level lies within the range of 600 to 1600 millitorr. Nitrogen from source 24 is always used to purge : ,, .
any residual SiH4 left in the system once the SiH4 is turned off. Nitrogen from the source 28 is used to b~eak the vacuum and establish atmospheric pressure within the tube 32.
Although specific embodiments of the invention have been described herein, it is not intended to limit the invention solely thereto but to include all of the varia-tions and modifications which suggest themselves to one skilled in the art within the spirit and scope of the appended claims, " - :"' ' :
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BACKGROUND OF THE INVENTION
The prior art method for forming polycrystalline silicon on wafers is run in a hot-wall furnace using nitro-gen gas as the carrier gas and silicon tetrahydride as the source of silicon. The furnace is given a heat profile which resembles a ramp beginning at the source end and increasing towards the exhaust end of the tube. Each furnace is independently profiled such that there is a rain-out profile giving the most uniform front-to-back, and side-to-side poly deposition as is possible within the system.
According to the prior art practice, the quartz boat is placed in the rain-out area of the furnace and wafers are placed side-by-side with one broad surface on the boat such that the deposition of the polycrystalline silicon occurs over the opposing and upturned second major surface.
Because of the placement of the wafers on their flat sur-faces, approximately 12 to 20 wafers fit within the deposi-tion zone of the urnace at any one time. Normally, two lines of wafers are placed on the boat. The deposition profile of the polycrystalline material on the wafer appears bell-shaped when taken on a straight line across the wafer and perpendicular to the flow of gas. This means that in ~ -the center of the wafer, the polycrystalline material is thicke~t and at the edge of the wafer, it is thinnest.
Normally, an average thickness of 4500 Angstroms is chosen ~ ~-with the thickest material in the center at 6000 Angstroms and the edge thickness of the material at 3000 Angstroms.
In practice, the center portion of 6000 Angstroms thick ~;
material can be too thick for the manufacture of devices on that wafer while the 3000 thick Angstroms of polycrystalline silicon can be too thin for the successful fabrication of - -- .
.
.
~0478S~
devices. Accordingly, some workable devices are fabricated in the intermediate area where the polycrystalline thickness is typically 4500 Angstroms. A third drawback in this system is the wafers are placed into the furnace from the exit end, the brown, powdered silicon material oftentimes drops off the walls onto the wafer as they are being pulled out of or put into the furnace. The buildup of such powdered silicon material on the quartz tube is so rapid that normally a maximum of ten to twenty runs can be made using the same quartz tube. When the quartz tube is pulled from the furnace to be cleaned, the coefficient of expansion between the quartz and the silicon is so great that the quartz tube breaks and a new center section must be fused with the unbroken end sections as to reuse these two end portions of the tube.
In summary, the prior art process for deposit poly-crystalline on wafers has the problems of low throughput;
i.e., 12 to 20 wafers at a time, non-uniformity of deposi-tion of material +1500 Angstroms across the surface of the wafers, and the wafers are put in from the exit end of the tube subjecting them to the flaking off of powdered silicon material which then falls onto the wafers either prior to polycrystalline silicon deposition or after such polycrys-talline silicon deposition. Such deposition of granular silicon renders the adjacent area unfit for the fabrication of devices.
SUMMARY OF THE INVENTION
The present invention relates generally to a process and product for the deposition of polycrystalline silicon on a substrate in a heated tube, using a gaseous source and 1~347850 a vacuum and, more particularly, the present invention relates to a process and product for depositing polycrystal-line silicon on a substrate in a heated tube using silicon tetrahydride as the source gas, and using a vacuum.
It is an object of the present invention to provide a new improved method for depositing polycrystalline silicon on a substrate using a heated tube and a vacuum.
It is an additional object of the present invention to ;
provide a hot-wall furnace tube having a flat temperature profile in the hot zone of the tube which results in the deposition of a uniform thickness of polycrystalline silicon over the major portion of the surface of the wafer.
It is still a further object of the present invention to provide a method for depositing polycrystalline silicon from silane in a hot-wall furnace tube with improved uni-formity as compared to that presently possible.
It is another object of the present invention to pro~
vide a means and a method for depositing polycrystalline silicon from silane at a uniform rate over the wafer with a tolerance of better than 500 Angstroms from edge to edge of a single wafer.
It is still a further object of the present invention to provide a method for depositing polycrystalline silicon on wafers within a hot-wall furnace tube for increasing the throughput capacity of the furnace. ~-~
It is a further object of the present invention to provide a method for depositing polycrystalline silicon on wafers in a hot-wall tube such that the major surface of the wafers contain a uniform thickness of the polycrystalline ~
silicon over a~ great a region as possible. -It is another object of the present invention to pro-vide a method for depositing polycrystalline silicon on ~ - -lQ47850 wafers in a furnace wherein the wafers are placed on edge and their broad major surfaces are then placed perpendicular to the flow of the source gas and the wafers are placed closer together than previously thought possible.
It is an additional object of the present invention to provide a method for depositing polycrystalline silicon on many different substrates used in the manufacture of semi-conductor devices at temperatures over 600C, such as sili-con, germaniumj-sapphire, spinel, ceramic, silicon dioxide, and refractory metals such-as tungsten,-molybdenum.
It is a stil-l further object of the present invention to provide a method of depositing polycrystalline silicon in -a heated tube, which method is independent of the means for heating the tube and heating means such as RF, resistance or radiant heat can be used.
It is another object-of the present invention to pro~
vide a method for depositing polycrystalline silicon on a substrate using several gas sources such as silane, SiC12H2, SiClH3, and SiC14.
It is a further object of the present invention to -provide-a method for deposi-ti-ng polycrystalline silicon in a heated evacuated tube under a vacuum on a substrate and using a gaseous source, wherein the spacing of the wafers is minimized for increasing the throughput of the method.
The invention of a method of forming a polycrystalline silicon layer upon a plurality of silicon wafers, comprises the steps of placing a plurality of silicon wafers in a closed container; establishing a uniform temperature throughout a portion of the closed container, said temperature being less than 700C, and said wafers being placed within the uniform temperature portion of the container; placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance greater than 30 mils; and passing ~ ' ~ _ 5 _ , : .
a gas stream of silane over ~he heated wafers under the motivation of a vacuum. Preferably the vacuum is established between the range of 600 to 1600 millitorr.
More particularly, ~here is provided:-a method of forming a polycrystalline silicon layer upon a plurality of silicon wafers, comprising the steps of:
placing a plurality of silicon wafers in a closed container;
heating said wafers to a temperature less than 700C;
passing a gas stream of silane over the heated wafers under the motivation of a vacuum established between the range of 600 to 1600 millitorr; and placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance greater than 30 mils. -There is also provided:-a method of forming a polycrystalline silicon layer upon a plurality of d licon wafers, comprising the teps of:
placing a plurality of s~licon wafers in a closed container;
heating said wafers to a temperature less than 700--C, placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance600 to 1600 mlllitorr; and ~ ~ -pass~ng 8 gas stream of silane over the heated --w~fers under the motivation of a vacuum.
~ 5a '~ .
1~47850 DESCRIPTION OF THE FIGURES
Fig. 1 shows a schematic view of a standard polycrys-talline silicon deposition apparatus;
Fig. 2 shows the temperature profile used in the apparatus shown in Fig. l; ~ ~
Fig. 3 shows a deposition curve normally associated ~ -with the apparatus shown in Fig. l;
D~
, 1~)47850 Fig. 4 shows the top view of a typical two-inch wafer shaded to show its non-uniform coating of polycrystalline silicon in a system as shown in Fig. 1;
Fig. 5 shows a thickness profile taken along the line 5-5 of the wafer shown in Fig. 4 which is perpendicular to the path of the gas flow;
Fig. 6 shows a plurality of thickness profiles taken along the line 6-6 of the wafer shown in Fig. 4 which pro-files are along the path of the gas flow at different posi-tions in the tube;
Fig. 7 shows the schematic view of the apparatus of the present invention;
Fig. 8 shows the temperature profile of the apparatus shown in Fig. 7;
Fig. 9 shows the deposition profile at a selected temperature;
Fig. 10 identifies a plurality of locations on a wafer -~
which is coated with different thicknesses of polycrystal-line silicon when the wafers are closely spaced on the boat;
Fig. 11 shows the cross sectional profile of the poly-crystalline film along the lines R-R, S-S, and T-T identi-fied in Fig. 10, and the films are formed in the apparatus shown in Fig. 7, wherein the wafers were spaced approxi-mately 3000 mils apart;
Fig. 12 identifies a plurality of locations on a wafer which is coated with a substantially uniform thickness of polycrystalline silicon material over substantially all of the area of the wafer, when the wafer is spaced from the next adjacent wafer approximately 50 mils on centers using 20 mil thick wafers;
.
.
Fig. 13 shows the cross-sectional profile of the thick-ness of polycrystalline film above the lines X-X and Y-Y
shown in Fig. 12 of a wafer placed in a furnace of Fig. 7 wherein the spacing between adjacent wafers is on 50 mil centers and the wafers are 20 mils thick; --Fig. 14 shows the maximum variations of deposited poly-crystalline silicon over the wafer surface as a function of the spacing of the wafers.
BRIEF DESCRIPTION OF THE INVENTION
In the prior art system of depositing polycrystalline silicon, as shown with reference to Fig~ 1, there is shown a source 1 of nitrogen gas which is the carrier gas for the system and a source 3 of silicon tetrahydride which is a source of silicon. The furnace tube 5 can be heated by resistance heater coils 7 adjusted to give a temperature profile as shown in Fig. 2. This temperature profile has been chosen in combination with the deposition profile as shown in Fig. 3 such that the highest degree of uniformity of polycrystalline deposition is achieved on the wafers 9 which are placed within the fallout range of the tube as indicated by the line 11 shown in Fig. 1. The fallout range is that area of the tube 5 at which the polycrystalline silicon deposits out of the gas flow through the tube. The temperature within the furnace is such as to decompose the silicon tetrachloride causing the silicon to rainout from the gas stream onto the wafers positioned below. The top view of the wafer having polycrystalline silicon deposited thereon shown in Fig. 4 while a cross section through the wafer taken on the lines 5-5 perpendicular to the gas flow is shown in Fig. 5 and shows the variation in thickness lQ47850 across a single representative wafer. The coverage of the wafers is greatest at the center of the wafer and tapers off t~ a thinnest portion on the edge of the wafers. Fig. 6 shows the variation in thickness of polycrystalline silicon depending on the location of the wafer within the fallout zone 11.
Referring again to Fig. 2, this view shows the tempera-ture profile of the prior art deposition tube. The tempera-ture is established as a ramp beginning at 625C at the source end of the fallout zone identified as A. The central portion B of the fallout zone is set at 650C, while the exhaust end C of the fallout zone is held at 675C.
Referring again to Fig. 3, this view shows the deposi-tion thickness profile as a measure of the position of the wafer surface in the fallout zone. This figure shows a variation of first a plus 3000 Angstroms and then a minus 3000 Angstroms along the fallout zone, The source end of the fallout zone A shows a thickness of 3000 Angstroms, while the central point B shows a thickness of 6000 Ang-stroms and the exhaust end shows a thickness of 3000 Ang-stroms. While it is possible to build devices with the thickness of polycrystalline silicon over the entire range as shown in Fig. 3, it is impractical from a commercial viewpoint to identify and sort the individual die according to thickness. It is not uncommon to have several hundred die to a wafer. The actual identification and sorting of these die is too costly. Again the profile is a typical profile for a fixed run of 30 minutes, Larger or shorter runs would give different numbers. Also other factors such as flow rates and temperatures would give different numbers from run to run if minute differences in such run parameters occurred.
- 8 - ;
' 1~47850 Fig. 4 shows the top view of a typical two-inch wafer.
Larger or smaller size wafers would have similar shaped pro-files in all the views, both in the prior art and in the new , system. The source gas is flowing from left to right in Fig. 4.
Fig. 5 shows the variation of the polycrystalline depo-sition across a single wafer along a line perpendicular to the source gas flow. This figure shows that the target thickness is identified as ~ Angstroms. This target thick-ness is exceeded,by a figure of approximately 500 Angstroms in the center Q of the wafer, and the actual thickness falls short by about 1000 Angstroms at both edges P and R of the wafer.
Fig. 6 shows the variation of polycrystalline silicon thickness across the wafer taken along the direction of gas ,~
flow at the center N of a wafer and at both the first edge M
and txailing edge O depending upon the placement of the wafer in the fallout zone 11. Curve C shows a generally decreas- ' ing thickness for a wafer placed at the exhaust end. Curve B
shows a concave variation'for the center of the fallout zone.
Curve A shows a generally increasing thickness for wafers placed at the source end of the tube.
In operation, a medium thickness of 4500 Angstroms is selected such that the thickest portion of the wafer along the line 6-6 of Fig. 4 is approximately 6000 Angstroms thick, Fig. 3, while the thinnest part of the wafer along the line 5-5 is at 3000 Angstroms thick, Fig. 3. This variation in thickness guarantees that certain regions of the wafer have an optimum thickness of the polycrystalline material at 4500 Angstroms. With the optimum thickness, certain usable devices can be made on the wafer. However, it has been found that 1~47850 3000 Angstroms can be too thin and 6000 Angstroms can be too thick for usable device performance.
Accordingly, it is desirable to form a polycrystalline layer with a more optimum thickness over a greater portion of the wafer. In the system shown in Fig. 1 only 12 to 20 wafers can be passed through the system at one time because of the size of the tube and the size of the fallout zone. ~-Since the wafers must lie on a major surface with the poly-crystalline material raining out from the gas stream upon the upper or opposite major surface of a substrate, the physical limitation of the system is 12 to 20 wafers.
Another drawback on the system shown with reference to Fig. 1 is the fact that the wafers are put in through the -exhaust end 13 of the tube. When the wafers are being put in, as well as when the wafers are taken out, some of the powdered silicon material flecks off of the walls of the tube at the end 13 and become deposited on the wafers. This means that any polycrystalline material grown over that powdered piece of silicon would be unsuitable for the forma-tion of semiconductor devices. Also, any flecks of powdered -silicon fallingon a newly grown polycrystalline layer adversely affects the use of that area for an active device. ~-Referring to Fig. 7 there is shown a schematic view of -~
the present system wherein the preferred source 20 of semi-conductor material is silane in a gaseous form. Other ~
sources can be used as SiCl2H2, SiClH3 or SiC14. A flow- ~ -meter 22 i8 provided for metering the correct amount of silane gas flow into the tube and over the wafers. A first source 24 of nitrogen is provided along with a nitrogen flowmeter 26. This flow is normally used at a low flow level to backflush any residual silane remaining within the , , : ............................. ~ . : .
:, :' . - : : ~ .
:1~)478SO :
plumbing lines outside of the furnace since silane is explo- -sive when above a certain temperature and exposed to air.
A second source 28 of nitrogen is provided along with a flowmeter 30 for measuring the flow of nitrogen from the source 30 into a tube 32. This source of nitrogen is used for rapidly bringing the evacuated tube 32 up to atmospheric pressure as well as aiding in the initial heating of the wafers. While nitrogen is shown, any inert gas normally used in the processing of semiconductor wafers can be used;
i.e., argon, etc. Best results are achieved when the source gas 20 is used alone during the deposition of the ~
polycrystalline material. All gases flow in the direction ~-of the arrow 34. An end cap 36 is in engagement with the tube to provide a vacuum seal with the tube. The N2 and SiH4 flows enter the tube 32 at the point where the line 38 passes through an appropriate fitting in the end cap 36. A
pressure sensor and vacuum gauge 40 is also attached to the ~ --input line 38 for reading the pressure and vacuum at this point. The furnace tube 32 is profiled to exhibit a flat ~
temperature profile as shown in Fig. 8 while the deposition - -profile is shown with reference to Fig. 9. This means that the flattened curve shown in Fig. 9 represents the variation in the thickness of polycrystalline silicon material deposited on a wafer when positioned at any location within the entire heated zone of the furnace. The usable range of the furnace proyides a thickness variation of only 500 Angstroms from the front to the back of the furnace. Refer- ~ -ring to Fig. 13 briefly, this figure shows that for any one wafer the thickness is substantially constant over the entire wafer surface when the wafers are stood on edge perpendicular to the gas flow. The embodiment shown with , . . . . .
- , . :
.- , , ,.,,: . : ' . .
1~47850 reference to Fig. 7 provides this improved thickness control.
The profiling temperature for the furnace shown in Fig. 7 can lie within a temperature range anywhere from 600-700 for giving practical results. At temperatures lower than 600, the rate of deposition slows to the point where the run takes too long. However, in those instances where a slow deposition rate can be tolerated, temperatures can be lowered to the minimum temperature at which the silence decomposes. At the upper end of the temperature spectrum; i.e., above 700C, crystalline imperfections are formed on the surface of the wafers. Such imperfections or outgrowths are formed in a deposition atmosphere in the absence of hydrogen. Fig. 8 shows the preferred temperature profile of the furnace 32 wherein the temperature of 600C
is established at the source end A, the center B and the exhaust end C of the deposition zone indicated in Fig. 7 by a line 41.
Fig. 9 shows the deposition profile of the system shown in Fig. 7 when the tube is heated to 600C and the deposi-tion run lasts for thirty minutes. The variation from the source end A to the exhaust end B of the deposition zone is 500 Angstroms as indicated by a line 42. The deposition profile within the preferred deposition zone of the tube plu9 a leading and trailing edge is shown by the curve 43.
It has been found that the best results are achieved when the maximum deposition thickness is set at the target thick-ness and the variations occur on the downward side as shown in Fig. 9. Similar deposition curves are achieved using a target thickness other than 4500 Angstroms.
In some early experiments a cold trap cooled by liquid nitrogen was used to remove the silane before it was vented into the vacuum pump 44 shown in Fig. 7. This was to pre-.
- 1~47850 -vent damage to the vacuum apparatus. However, the cold trap was allowed to warm after the deposition run was completed it was damaged by the spontaneous burning of the silane as it warmed and became exposed to air.
Accordingly, optical baffles 45 are attached at the exhaust end 46 of the quartz tube 32 to trap out the powdered silicon at this point. Wafers 47 are placed into a quartz boat 49 and the loaded boat is loaded into the tube through the source ~nd 51 of the quartz tube 32. In this way contact with the deposited powdered silicon material at the exhaust end 45 of the quartz tube is avoided. The silicon boat carrying the wafers is placed within the pre-ferred portion of the deposition curve, as discussed with reference to Fig. 9. The wafers are placed on end and are placed with their broad surface perpendicular to the gas .... .... . .
flow.
In earlîer experiments, wafers were placed at greater distances and wafers were manufactured having the top view as shown in Fig. 10. The upper portion of the wafer indi-cated by the line S-S has a uniform amount of material deposited thereon, as shown by a comparison curve S-S' in -Fig. 11, but the lower portion indicated by the line R-R was substantially non-uniform and unusable as shown by the comparison curve R-R' in Fig. 11. Additionally, a thickness variation also occurred from the top to the bottom of the wafer as indicated by the line T-T in Figs, 10 and 11. The spacing which gave the results illustrated in Fig. 11 was 3000 mils~ It should be kept in mind that the length of the spacing between wafers is that distances between midpoints - - -of the thickness of adjacent wafers. When two wafers are 20 mils thick and the spacing is given as 50 mils, there is actually a 30 mil open area between the rear surface of the .
~V47850 first wafer and the front surface of the next wafer.
Accordingly, if thicker wafers are used, the spacings would change also. This change would only be significant at the upper and lower limits as in between it does not matter. It is recommended that the actual spacing of 30 mils from surface to surface should not be made smaller. At the upper limit, minimum acceptable depositions on the top half of wafers were achieved at actual back surface to front surface spacing of 2980 mils.
Accordingly, many experiments were run to ascertain the optimum spacing of the wafers side-by-side. This informa-tion is shown in Fig. 14 by the line 53. This curve shows the maximum variation across the wafer as a function of wafer spacing. A preferable open space distance of 30 mils between adjacent surfaces of adjacent wafers has been selected as the preferable distance. A polycrystalline silicon layer is formed on a wafer shown in Fig. 12 having a deposition profile as shown in Fig. 13. A line 55 shows the thickness variation in both the X-X~ and Y-Y~ directions as shown in Fig. 12. This shows an essentially uniform thickness of polycrystalline silicon material deposited across the major portion of the wafer. It is only at the edge points 61a and 61b of the curve 55 shown in Fig. 13 that a slight increase in thickness is found, It should be emphasized that the thickness of the polycrystalline - -material across the major surface between the lines is -essentially uniform while the difference in thickness from ~ -wafer to wafer from the source end of the deposition zone to the exhaust end of the deposition zone differs by a total - -of 500 Angstroms as shown with reference to Fig. 9.
In the impro~ed system as shown with reference to Fig. 7, approximately 250 wafers can be placed on a 12-inch .. . . .
1~47BSO
boat. This is a throughput greater than 10 to 1 as compared with the prior art method of forming polycrystalline silicon material.
The operation of the system shown in Fig. 7 has the following special steps. The vacuum identified as the preferred vacuum level lies within the range of 600 to 1600 millitorr. Nitrogen from source 24 is always used to purge : ,, .
any residual SiH4 left in the system once the SiH4 is turned off. Nitrogen from the source 28 is used to b~eak the vacuum and establish atmospheric pressure within the tube 32.
Although specific embodiments of the invention have been described herein, it is not intended to limit the invention solely thereto but to include all of the varia-tions and modifications which suggest themselves to one skilled in the art within the spirit and scope of the appended claims, " - :"' ' :
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Claims (14)
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a method for depositing polycrystalline silicon material onto a substrate from a gaseous silicon source flow-ing through a furnace tube, and the furnace is provided with heating means, and is further provided with a first end through which the gaseous silicon source is admitted into the tube, and is further provided with a second end from which the residual gaseous silicon is exhausted, the improve-ment comprising the steps of:
introducing a plurality of substrates into the furnace through the first end;
placing said plurality of substrates into the stream of gaseous silicon such that the broad surface of each of said substrates upon which the polycrystalline material is to deposit is placed perpendicular to the direc-tion of the gas flow;
spacing the substrates a minimum of 30 mils between adjacent surfaces;
heating the substrates to a temperature under 700°C for a time sufficient to grow the desired thickness of polycrystalline silicon material;
establishing a vacuum at the exhaust end of the tube for drawing the gaseous silicon over the substrates;
continuing the flow of the gaseous silicon for a predetermined period and then closing off the flow of said gaseous silicon; and withdrawing said substrates from the furnace by said first end.
introducing a plurality of substrates into the furnace through the first end;
placing said plurality of substrates into the stream of gaseous silicon such that the broad surface of each of said substrates upon which the polycrystalline material is to deposit is placed perpendicular to the direc-tion of the gas flow;
spacing the substrates a minimum of 30 mils between adjacent surfaces;
heating the substrates to a temperature under 700°C for a time sufficient to grow the desired thickness of polycrystalline silicon material;
establishing a vacuum at the exhaust end of the tube for drawing the gaseous silicon over the substrates;
continuing the flow of the gaseous silicon for a predetermined period and then closing off the flow of said gaseous silicon; and withdrawing said substrates from the furnace by said first end.
2. The method recited in claim 1 wherein the furnace tube and substrates are heated to the predetermined operat-ing temperature before the gaseous silicon is passed into the furnace under the influence of the vacuum.
3. The method recited in claim 1, wherein the spacing of the substrates lies between 50 to 3000 mils on center.
4. The method recited in claim 1 wherein the gaseous silicon source is selected from SiH4, SiCl2H2, SiCl3 and SiCl4.
5. The method recited in claim 1 wherein the sub-strate to be covered with polycrystalline silicon is select-ed from silicon, germanium, sapphire, spinel, ceramic, silicon dioxide, tungsten and molybdenum.
6. The method recited in claim 1, and further includes the step of:
providing an optical baffle at the exhaust end of the furnace tube for removing residual silane prior to entering the vacuum pump.
providing an optical baffle at the exhaust end of the furnace tube for removing residual silane prior to entering the vacuum pump.
7. The method for depositing polycrystalline silicon as recited in claim 1, wherein after the step of closing off the flow of silane, the method further includes the step of:
flushing with an inert gas any residual gaseous silane which remains between the silicon source and the vacuum source.
flushing with an inert gas any residual gaseous silane which remains between the silicon source and the vacuum source.
8. The method for depositing polycrystalline silicon as recited in claim 1, wherein after the step of closing off the flow of gaseous silicon, the method further includes the step of:
establishing atmospheric pressure within the furnace tube by deactivating the vacuum source and introducing an inert gas into the tube.
establishing atmospheric pressure within the furnace tube by deactivating the vacuum source and introducing an inert gas into the tube.
9. A method of forming a polycrystalline silicon layer upon a plurality of silicon wafers, comprising the steps of:
placing a plurality of silicon wafers in a closed container;
heating said wafers to a temperature less than 700°C;
passing a gas stream of silane over the heated wafers under the motivation of a vacuum established between the range of 600 to 1600 millitorr; and placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance greater than 30 mils.
placing a plurality of silicon wafers in a closed container;
heating said wafers to a temperature less than 700°C;
passing a gas stream of silane over the heated wafers under the motivation of a vacuum established between the range of 600 to 1600 millitorr; and placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance greater than 30 mils.
10. In a method for depositing polycrystalline sili-con material onto a wafer which has a layer of silicon dioxide formed on a first major surface of the wafer, and the silicon is obtained from a gaseous silane source flow-ing through a heated furnace tube, and the tube has a first end into which the gaseous silicon is added to the tube, and the tube is further equipped with a second end from which the residual gaseous silane is exhausted, the improve-ment comprising the steps of:
introducing a plurality of wafers into the furnace through the first end of the furnace, and said wafers being oriented such that the first major surface of each wafer faces the first end of the furnace tube and is perpendicular to the direction of gas flow through the furnace tube, and said wafers are spaced more than 30 mils between adjacent surfaces;
establishing a vacuum at the exhaust end of the tube to a level within the range of 600 to 1600 millitorr for drawing gases through the furnace;
introducing a flow of an inert gas into the tube while heating the wafers to a predetermined temperature under 700°C;
upon reaching the predetermined temperature, shutting off the flow of inert gas and exposing the silane to the effects of the vacuum;
continuing the flow of silane for a predetermined period and then closing off the flow of silane; and withdrawing the wafers from the furnace by said first end.
introducing a plurality of wafers into the furnace through the first end of the furnace, and said wafers being oriented such that the first major surface of each wafer faces the first end of the furnace tube and is perpendicular to the direction of gas flow through the furnace tube, and said wafers are spaced more than 30 mils between adjacent surfaces;
establishing a vacuum at the exhaust end of the tube to a level within the range of 600 to 1600 millitorr for drawing gases through the furnace;
introducing a flow of an inert gas into the tube while heating the wafers to a predetermined temperature under 700°C;
upon reaching the predetermined temperature, shutting off the flow of inert gas and exposing the silane to the effects of the vacuum;
continuing the flow of silane for a predetermined period and then closing off the flow of silane; and withdrawing the wafers from the furnace by said first end.
11. The method for depositing polycrystalline silicon as recited in claim 10, wherein after the step of closing off the flow of silane, the method further includes the step of:
flushing with an inert gas any residual silane which remains between the silane source and the source of vacuum.
flushing with an inert gas any residual silane which remains between the silane source and the source of vacuum.
12. The method for depositing polycrystalline silicon as recited in claim 10, wherein after the step of closing off the flow of silane, the method further includes the step of:
establishing atmospheric pressure within the furnace tube by deactivating the vacuum source and introducing an inert gas into the furnace tube.
establishing atmospheric pressure within the furnace tube by deactivating the vacuum source and introducing an inert gas into the furnace tube.
13. The method for depositing polycrystalline silicon as recited in claim 10, and further includes the step of;
providing an optical baffle at the exhaust end of the furnace tube for removing residual silane prior to entering the vacuum pump.
providing an optical baffle at the exhaust end of the furnace tube for removing residual silane prior to entering the vacuum pump.
14. A method of forming a polycrystalline silicon layer upon a plurality of silicon wafers, comprising the steps of:
placing a plurality of silicon wafers in a closed container;
heating said wafers to a temperature less than 700°C, placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance 600 to 1600 millitorr; and passing a gas stream of silane over the heated wafers under the motivation of a vacuum.
placing a plurality of silicon wafers in a closed container;
heating said wafers to a temperature less than 700°C, placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance 600 to 1600 millitorr; and passing a gas stream of silane over the heated wafers under the motivation of a vacuum.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US426396A US3900597A (en) | 1973-12-19 | 1973-12-19 | System and process for deposition of polycrystalline silicon with silane in vacuum |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1047850A true CA1047850A (en) | 1979-02-06 |
Family
ID=23690641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA216,252A Expired CA1047850A (en) | 1973-12-19 | 1974-12-19 | System and process for deposition of polycrystalline silicon with silane in vacuum |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3900597A (en) |
| JP (1) | JPS5095185A (en) |
| CA (1) | CA1047850A (en) |
| DE (1) | DE2460211B2 (en) |
| FR (1) | FR2255707B1 (en) |
| GB (1) | GB1470614A (en) |
| HK (1) | HK68380A (en) |
Families Citing this family (54)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2539434A1 (en) * | 1975-09-04 | 1977-03-17 | Siemens Ag | DEVICE FOR ALL-ROUND COATING OF SMALL METALLIC PARTS |
| GB1518564A (en) * | 1975-11-25 | 1978-07-19 | Motorola Inc | Method for the low pressure pyrolytic deposition of silicon nitride |
| US4027053A (en) * | 1975-12-19 | 1977-05-31 | Motorola, Inc. | Method of producing polycrystalline silicon ribbon |
| US4053335A (en) * | 1976-04-02 | 1977-10-11 | International Business Machines Corporation | Method of gettering using backside polycrystalline silicon |
| US4098923A (en) * | 1976-06-07 | 1978-07-04 | Motorola, Inc. | Pyrolytic deposition of silicon dioxide on semiconductors using a shrouded boat |
| US4062318A (en) * | 1976-11-19 | 1977-12-13 | Rca Corporation | Apparatus for chemical vapor deposition |
| JPS5423386A (en) * | 1977-07-22 | 1979-02-21 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS584811B2 (en) * | 1978-10-31 | 1983-01-27 | 富士通株式会社 | Manufacturing method of semiconductor device |
| US4203387A (en) * | 1978-12-28 | 1980-05-20 | General Signal Corporation | Cage for low pressure silicon dioxide deposition reactors |
| JPS55110032A (en) * | 1979-02-19 | 1980-08-25 | Fujitsu Ltd | Method for high-frequency heated epitaxial growth |
| DE2907371C2 (en) * | 1979-02-24 | 1981-03-12 | Heraeus Quarzschmelze Gmbh, 6450 Hanau | High temperature resistant protective tube for heat treatment of semiconductor components |
| US4228004A (en) * | 1979-04-12 | 1980-10-14 | Thermco Products Corporation | Method and apparatus for removal of by-products of chemical vapor deposition from oil for vacuum pump |
| JPS55158623A (en) * | 1979-05-29 | 1980-12-10 | Hitachi Ltd | Method of controlling semiconductor vapor phase growth |
| GB2049643B (en) * | 1979-05-30 | 1983-07-20 | Siemens Ag | Process for the production of silicon having semiconducting proprties |
| US4263336A (en) * | 1979-11-23 | 1981-04-21 | Motorola, Inc. | Reduced pressure induction heated reactor and method |
| US4315968A (en) * | 1980-02-06 | 1982-02-16 | Avco Corporation | Silicon coated silicon carbide filaments and method |
| US4444812A (en) * | 1980-07-28 | 1984-04-24 | Monsanto Company | Combination gas curtains for continuous chemical vapor deposition production of silicon bodies |
| DD206687A3 (en) * | 1981-07-28 | 1984-02-01 | Mikroelektronik Zt Forsch Tech | METHOD AND DEVICE FOR FUELING LP CVD PROCESSES IN A PIPE REACTOR |
| US4401687A (en) * | 1981-11-12 | 1983-08-30 | Advanced Semiconductor Materials America | Plasma deposition of silicon |
| JPS58172217A (en) * | 1982-03-31 | 1983-10-11 | Toshiba Corp | Formation of polycrystalline silicon film |
| US4547404A (en) * | 1982-08-27 | 1985-10-15 | Anicon, Inc. | Chemical vapor deposition process |
| US4489103A (en) * | 1983-09-16 | 1984-12-18 | Rca Corporation | SIPOS Deposition method |
| JPS60200523A (en) * | 1984-03-26 | 1985-10-11 | Agency Of Ind Science & Technol | Manufacture of silicon thin film |
| US4556584A (en) * | 1984-05-03 | 1985-12-03 | Btu Engineering Corporation | Method for providing substantially waste-free chemical vapor deposition of thin-film on semiconductor substrates |
| FR2572312B1 (en) * | 1984-10-30 | 1989-01-20 | Rhone Poulenc Spec Chim | PROCESS FOR MANUFACTURING ULTRA-PUR SILICON BARS |
| US4744863A (en) * | 1985-04-26 | 1988-05-17 | Wisconsin Alumni Research Foundation | Sealed cavity semiconductor pressure transducers and method of producing the same |
| US4853669A (en) * | 1985-04-26 | 1989-08-01 | Wisconsin Alumni Research Foundation | Sealed cavity semiconductor pressure transducers and method of producing the same |
| US4597160A (en) * | 1985-08-09 | 1986-07-01 | Rca Corporation | Method of fabricating a polysilicon transistor with a high carrier mobility |
| GB2193976B (en) * | 1986-03-19 | 1990-05-30 | Gen Electric Plc | Process for depositing a polysilicon film on a substrate |
| US5298452A (en) * | 1986-09-12 | 1994-03-29 | International Business Machines Corporation | Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers |
| US5607511A (en) * | 1992-02-21 | 1997-03-04 | International Business Machines Corporation | Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers |
| US4897360A (en) * | 1987-12-09 | 1990-01-30 | Wisconsin Alumni Research Foundation | Polysilicon thin film process |
| US5024972A (en) * | 1990-01-29 | 1991-06-18 | Motorola, Inc. | Deposition of a conductive layer for contacts |
| US5181964A (en) * | 1990-06-13 | 1993-01-26 | International Business Machines Corporation | Single ended ultra-high vacuum chemical vapor deposition (uhv/cvd) reactor |
| US5112773A (en) * | 1991-04-10 | 1992-05-12 | Micron Technology, Inc. | Methods for texturizing polysilicon utilizing gas phase nucleation |
| US5614257A (en) * | 1991-08-09 | 1997-03-25 | Applied Materials, Inc | Low temperature, high pressure silicon deposition method |
| US5695819A (en) * | 1991-08-09 | 1997-12-09 | Applied Materials, Inc. | Method of enhancing step coverage of polysilicon deposits |
| JP3121131B2 (en) * | 1991-08-09 | 2000-12-25 | アプライド マテリアルズ インコーポレイテッド | Low temperature and high pressure silicon deposition method |
| US5753559A (en) * | 1996-01-16 | 1998-05-19 | United Microelectronics Corporation | Method for growing hemispherical grain silicon |
| KR100652909B1 (en) * | 1998-03-06 | 2006-12-01 | 에이에스엠 아메리카, 인코포레이티드 | Method of depositing silicon with high step coverage |
| US6479166B1 (en) | 1998-10-06 | 2002-11-12 | Case Western Reserve University | Large area polysilicon films with predetermined stress characteristics and method for producing same |
| US6268068B1 (en) | 1998-10-06 | 2001-07-31 | Case Western Reserve University | Low stress polysilicon film and method for producing same |
| US6666924B1 (en) | 2000-03-28 | 2003-12-23 | Asm America | Reaction chamber with decreased wall deposition |
| US6564810B1 (en) | 2000-03-28 | 2003-05-20 | Asm America | Cleaning of semiconductor processing chambers |
| EP1421607A2 (en) | 2001-02-12 | 2004-05-26 | ASM America, Inc. | Improved process for deposition of semiconductor films |
| US7026219B2 (en) | 2001-02-12 | 2006-04-11 | Asm America, Inc. | Integration of high k gate dielectric |
| US6957741B2 (en) * | 2001-08-07 | 2005-10-25 | Manfred Franz Axel Freissle | Screening arrangement |
| JP5005170B2 (en) * | 2002-07-19 | 2012-08-22 | エーエスエム アメリカ インコーポレイテッド | Method for forming ultra-high quality silicon-containing compound layer |
| US7186630B2 (en) | 2002-08-14 | 2007-03-06 | Asm America, Inc. | Deposition of amorphous silicon-containing films |
| US6936086B2 (en) * | 2002-09-11 | 2005-08-30 | Planar Systems, Inc. | High conductivity particle filter |
| US9443730B2 (en) | 2014-07-18 | 2016-09-13 | Asm Ip Holding B.V. | Process for forming silicon-filled openings with a reduced occurrence of voids |
| US9837271B2 (en) | 2014-07-18 | 2017-12-05 | Asm Ip Holding B.V. | Process for forming silicon-filled openings with a reduced occurrence of voids |
| US10460932B2 (en) | 2017-03-31 | 2019-10-29 | Asm Ip Holding B.V. | Semiconductor device with amorphous silicon filled gaps and methods for forming |
| CN115613007A (en) * | 2022-10-13 | 2023-01-17 | 上海中欣晶圆半导体科技有限公司 | Film forming method for improving warping |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1138481C2 (en) * | 1961-06-09 | 1963-05-22 | Siemens Ag | Process for the production of semiconductor arrangements by single-crystal deposition of semiconductor material from the gas phase |
| US3409483A (en) * | 1964-05-01 | 1968-11-05 | Texas Instruments Inc | Selective deposition of semiconductor materials |
| US3446936A (en) * | 1966-01-03 | 1969-05-27 | Sperry Rand Corp | Evaporant source |
| DE1614893C3 (en) * | 1967-11-28 | 1979-08-09 | Telefunken Patentverwertungs Gmbh, 7900 Ulm | Method for improving and stabilizing the characteristic curve of a semiconductor component and applications thereof |
| JPS509471B1 (en) * | 1968-10-25 | 1975-04-12 | ||
| DE1900116C3 (en) * | 1969-01-02 | 1978-10-19 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Process for the production of high-purity monocrystalline layers consisting of silicon |
| JPS5311051B2 (en) * | 1973-06-29 | 1978-04-19 |
-
1973
- 1973-12-19 US US426396A patent/US3900597A/en not_active Expired - Lifetime
-
1974
- 1974-12-17 GB GB5447774A patent/GB1470614A/en not_active Expired
- 1974-12-18 JP JP49145507A patent/JPS5095185A/ja active Pending
- 1974-12-19 CA CA216,252A patent/CA1047850A/en not_active Expired
- 1974-12-19 DE DE2460211A patent/DE2460211B2/en not_active Ceased
-
1975
- 1975-01-09 FR FR7500576A patent/FR2255707B1/fr not_active Expired
-
1980
- 1980-12-04 HK HK683/80A patent/HK68380A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| US3900597A (en) | 1975-08-19 |
| DE2460211A1 (en) | 1975-11-06 |
| DE2460211B2 (en) | 1979-05-23 |
| GB1470614A (en) | 1977-04-14 |
| JPS5095185A (en) | 1975-07-29 |
| FR2255707A1 (en) | 1975-07-18 |
| FR2255707B1 (en) | 1978-06-23 |
| HK68380A (en) | 1980-12-12 |
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