US20230146758A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20230146758A1
US20230146758A1 US17/914,713 US202117914713A US2023146758A1 US 20230146758 A1 US20230146758 A1 US 20230146758A1 US 202117914713 A US202117914713 A US 202117914713A US 2023146758 A1 US2023146758 A1 US 2023146758A1
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Prior art keywords
power lead
semiconductor device
semiconductor
semiconductor element
layer
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US17/914,713
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English (en)
Inventor
Tatsuya Miyazaki
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Rohm Co Ltd
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Rohm Co Ltd
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Assigned to ROHM CO., LTD. reassignment ROHM CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MIYAZAKI, TATSUYA
Publication of US20230146758A1 publication Critical patent/US20230146758A1/en
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Definitions

  • the present disclosure relates to a semiconductor device including a semiconductor element.
  • Patent document 1 discloses a conventional semiconductor device.
  • the semiconductor device described in Patent document 1 includes a semiconductor element, an island, a lead, a plurality of bonding members, a connecting plate, and a sealing resin.
  • the semiconductor element in the semiconductor device is a transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • an object of the present disclosure is to provide a semiconductor device capable of suppressing ringing.
  • a semiconductor device provided by the present disclosure includes: at least one semiconductor element having a switching function; a conductive member that forms a path of a current switched by the semiconductor element, and that is made of a first material; and a covering layer that covers at least a portion of the conductive member, and that is made of a second material.
  • the second material satisfies at least one of the following three requirements: (a) having a magnetic permeability higher than the first material; (b) having an electrical resistivity higher than the first material; and (c) having a dielectric loss tangent larger than zero.
  • the second material is a magnetic conductor having a magnetic permeability higher than the first material and having an electrical resistivity higher than the first material.
  • the second material has a dielectric loss tangent larger than zero.
  • the second material has a magnetic permeability higher than the first material, and has a dielectric loss tangent larger than zero.
  • the second material has an electrical resistivity higher than the first material, and has a dielectric loss tangent larger than zero.
  • the covering layer has a thickness of 1 ⁇ m to 5 ⁇ m.
  • a relative magnetic permeability of the second material is not less than 10.
  • the electrical resistivity of the second material is not less than twice the electrical resistivity of the first material.
  • the dielectric loss tangent of the second material is not less than 0.01.
  • the semiconductor device further includes a capacitor having a first end and a second end for electrical connection.
  • the at least one semiconductor element includes a plurality of semiconductor elements that form a half-bridge including at least a pair of upper arm and lower arm, where the plurality of semiconductor elements include a first semiconductor element in the upper arm and a second semiconductor element in the lower arm.
  • the conductive member includes a first metal layer connected to a drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to a source electrode of the second semiconductor element.
  • the first end of the capacitor is connected to the first power lead, and the second end of the capacitor is connected to the second power lead.
  • the covering layer includes a first portion covering the first power lead and a second portion covering the second power lead.
  • the first power lead includes a portion forming a path between the first semiconductor element and the capacitor, and the portion of the first power lead is not covered with the first portion.
  • the second power lead includes a portion forming a path between the second semiconductor element and the capacitor, and the portion of the second power lead is not covered with the second portion.
  • the covering layer includes a third portion covering the first metal layer.
  • the conductive member includes a second metal layer connected to a drain electrode of the second semiconductor element, and a third power lead connected to the second metal layer, and the second metal layer and the third power lead are not covered with the covering layer.
  • the conductive member includes an intermediate lead connected to a source electrode of the first semiconductor element and the second metal layer, and the intermediate lead is not covered with the covering layer.
  • the conductive member includes a first spacer interposed between the first metal layer and the first power lead, and the covering layer includes a fourth portion covering the first spacer.
  • the conductive member includes a conductor interposed between the source electrode of the second semiconductor element and the second power lead.
  • the semiconductor element is one of a SiC MOSET, a SiC IGBT, a Si MOSFET, a Si IGBT, and a GaN HEMT.
  • the semiconductor device according to the present disclosure can suppress ringing, simplify a snubber circuit, and improve reliability.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment.
  • FIG. 2 is a perspective view showing main parts of the semiconductor device according to the first embodiment.
  • FIG. 3 is a plan view showing the semiconductor device according to the first embodiment.
  • FIG. 4 is a plan view corresponding to FIG. 3 , with a sealing resin indicated by an imaginary line.
  • FIG. 5 is a partially enlarged plan view showing a part of
  • FIG. 4 is a diagrammatic representation of FIG. 4 .
  • FIG. 6 is a front view showing the semiconductor device according to the first embodiment.
  • FIG. 7 is a bottom view showing the semiconductor device according to the first embodiment.
  • FIG. 8 is a left side view showing the semiconductor device according to the first embodiment.
  • FIG. 9 is a right side view showing the semiconductor device according to the first embodiment.
  • FIG. 10 is a cross-sectional view along line X-X in FIG. 4 .
  • FIG. 11 is a cross-sectional view along line XI-XI in FIG. 10 .
  • FIG. 12 is a cross-sectional view showing a first variation of the semiconductor device according to the first embodiment.
  • FIG. 13 is a cross-sectional view showing a second variation of the semiconductor device according to the first embodiment.
  • FIG. 14 is a perspective view showing main parts of a semiconductor device according to a second embodiment.
  • FIG. 15 is a plan view showing the semiconductor device according to the second embodiment.
  • FIG. 16 is a cross-sectional view along line XVI-XVI in FIG. 15 .
  • FIG. 17 is a perspective view showing main parts of a semiconductor device according to a third embodiment.
  • FIG. 18 is a plan view showing the semiconductor device according to the third embodiment.
  • FIG. 19 is a cross-sectional view along line XIX-XIX in FIG. 18 .
  • FIG. 20 is a plan view showing a semiconductor device according to a fourth embodiment.
  • FIG. 21 is a cross-sectional view along line XXI-XXI in FIG. 20 .
  • FIGS. 1 to 11 show a semiconductor device according to a first embodiment.
  • a semiconductor device A 1 according to the first embodiment includes a plurality of semiconductor elements 10 , a support substrate 20 , a plurality of leads, a plurality of intermediate leads 40 , a plurality of wire members 50 , a plurality of conductive blocks 60 , a sealing resin 70 , a capacitor 81 , and a covering layer 90 .
  • the plurality of leads include a first power lead 31 , a second power lead 32 , a third power lead 33 , a pair of gate leads 34 A and 34 B, a pair of driver source leads 35 A and 35 B, and a plurality of dummy leads 36 .
  • the conductive blocks 60 include a plurality of first blocks 61 and a plurality of second blocks 62 .
  • FIG. 1 is a perspective view showing the semiconductor device A 1 .
  • FIG. 2 is a perspective view corresponding to FIG. 1 but omitting the sealing resin 70 .
  • the wire members 50 are omitted in FIG. 2 .
  • FIG. 3 is a plan view showing the semiconductor device A 1 .
  • FIG. 4 is a plan view corresponding to FIG. 3 , with the sealing resin 70 indicated by an imaginary line (two-dot chain line).
  • FIG. 5 is a partially enlarged view showing a part of FIG. 4 .
  • FIG. 6 is a front view showing the semiconductor device A 1 .
  • FIG. 7 is a bottom view showing the semiconductor device A 1 .
  • FIG. 8 is a left side view showing the semiconductor device A 1 .
  • FIG. 9 is a right side view showing the semiconductor device A 1 .
  • FIG. 10 is a cross-sectional view along line X-X in FIG. 4 .
  • FIG. 11 is a cross-sectional view along line XI-XI in FIG. 10 .
  • a plurality of dots are depicted in the covering layer 90 to facilitate understanding.
  • the z direction corresponds to the thickness direction of the semiconductor device A 1 .
  • the x direction corresponds to the horizontal direction in the plan views (see FIGS. 3 and 4 ) of the semiconductor device A 1 .
  • the y direction corresponds to the vertical direction in the plan views (see FIGS. 3 and 4 ) of the semiconductor device A 1 .
  • one sense of the x direction is defined as x1 direction, and the other sense as x2 direction.
  • one sense of the y direction is defined as y1 direction, and the other sense as y2 direction.
  • One sense of the z direction is defined as z1 direction, and the other sense as z2 direction.
  • Each of the semiconductor elements 10 has a function of switching the main circuit current, and is not limited to any specific configuration.
  • the semiconductor elements 10 may be silicon carbide (SiC) MOSETs, SiC insulated gate bipolar transistors (IGBTs), Si MOSFETs, Si IGBTs, and gallium nitride (GaN) high electron mobility transistors (HEMTs).
  • SiC silicon carbide
  • IGBT SiC insulated gate bipolar transistors
  • GaN gallium nitride
  • HEMTs gallium nitride
  • Each of the semiconductor elements 10 has a rectangular shape as viewed in the z direction (also referred to as “plan view”), but the present disclosure is not limited to this.
  • each of the semiconductor elements 10 has an element obverse surface 101 and an element reverse surface 102 .
  • the element obverse surface 101 and the element reverse surface 102 are spaced apart and face away from each other in the z direction.
  • the element obverse surface 101 faces in the z2 direction
  • the element reverse surface 102 faces in the z1 direction.
  • each of the semiconductor elements 10 has an obverse surface electrode 11 , a reverse surface electrode 12 , and an insulating film 13 .
  • the obverse surface electrode 11 is provided on the element obverse surface 101 .
  • the obverse surface electrode 11 includes a source electrode 111 , a gate electrode 112 , and a driver source electrode 113 .
  • the source electrode 111 is an electrode through which a source current flows.
  • the gate electrode 112 is an electrode to which a gate voltage for driving the semiconductor element 10 is applied.
  • the driver source electrode 113 provides a reference potential for the gate voltage.
  • the source electrode 111 is larger than each of the gate electrode 112 and the driver source electrode 113 .
  • the gate electrode 112 and the driver source electrode 113 have substantially the same size.
  • the source electrode 111 includes a single region. However, the source electrode 111 may be divided into multiple regions.
  • the reverse surface electrode 12 is provided on the element reverse surface 102 .
  • the reverse surface electrode 12 is formed over the entirety of the element reverse surface 102 .
  • the reverse surface electrode 12 is an electrode through which a drain current flows.
  • the reverse surface electrode 12 is also referred to as a drain electrode 12 .
  • the insulating film 13 is provided on the element obverse surface 101 .
  • the insulating film 13 is electrically insulative.
  • the insulating film 13 surrounds the obverse surface electrode 11 in plan view.
  • the insulating film 13 insulates the source electrode 111 and the gate electrode 112 from each other.
  • the insulating film 13 may be formed by stacking a silicon dioxide (SiO 2 ) layer, a silicon nitride (Si 3 N 4 ) layer, and a polybenzoxazole layer in this order on the element obverse surface 101 , with the polybenzoxazole layer being a surface layer.
  • the polybenzoxazole layer in the insulating film 13 may be replaced with a polyimide layer.
  • the insulating film 13 is not limited to having the configuration described above.
  • the plurality of semiconductor elements 10 include a plurality of first semiconductor elements 10 A and a plurality of second semiconductor elements 10 B.
  • the semiconductor device A 1 is configured as a half-bridge switching circuit.
  • the first semiconductor elements 10 A constitute an upper arm circuit of the switching circuit
  • the second semiconductor elements 10 B constitute a lower arm circuit of the switching circuit.
  • the semiconductor device A 1 includes four first semiconductor elements 10 A and four second semiconductor elements 10 B.
  • the number of semiconductor elements 10 is not limited to the above, and may be selected appropriately according to the performance required for the semiconductor device A 1 .
  • the first semiconductor elements 10 A are mounted on the support substrate 20 (conductive substrate 22 A).
  • the first semiconductor elements 10 A are aligned and spaced apart from each other in the y direction.
  • the element reverse surfaces 102 face the conductive substrate 22 A.
  • the first semiconductor elements 10 A are electrically bonded to the support substrate 20 (conductive substrate 22 A) via, for example, element bonding members (not illustrated) that are electrically conductive. Examples of the element bonding members include solder, sintered silver, and silver paste.
  • the second semiconductor elements 10 B are mounted on the support substrate 20 (conductive substrate 22 B).
  • the second semiconductor elements 10 B are aligned and spaced apart from each other in the y direction.
  • the element reverse surfaces 102 face the conductive substrate 22 B.
  • the second semiconductor elements 10 B are electrically bonded to the support substrate 20 (conductive substrate 22 B) via, for example, element bonding members (not illustrated) that are electrically conductive.
  • the first semiconductor elements 10 A and the second semiconductor elements 10 B overlap with each other as viewed in the x direction.
  • the first semiconductor elements 10 A and the second semiconductor elements 10 B may not overlap with each other as viewed in the x direction.
  • the support substrate 20 is a support member that supports the semiconductor elements 10 .
  • the support substrate 20 includes an insulating substrate 21 , two conductive substrates 22 A and 22 B, a pair of insulating layers 23 A and 23 B, a pair of gate layers 24 A and 24 B, a pair of driver source layers 25 A and 25 B, a first spacer 26 A, and a second spacer 26 B.
  • the insulating substrate 21 is a plate-like member that is electrically insulative.
  • the insulating substrate 21 supports the two conductive substrates 22 A and 22 B.
  • the insulating substrate 21 includes two insulating substrates 21 A and 21 B that each have a flat plate-like shape.
  • the insulating substrate 21 is not limited to having the configuration described above, and may be a single flat plate instead of being divided into the two insulating substrates 21 A and 21 B.
  • Each of the insulating substrates 21 A and 21 B is made of a ceramic material having excellent thermal conductivity, for example. Examples of the ceramic material include aluminum nitride (AlN), silicon nitride (SiN), and aluminum oxide (Al 2 O 3 ).
  • Each of the insulating substrates 21 A and 21 B has a rectangular shape in plan view.
  • the insulating substrate 21 A supports the conductive substrate 22 A
  • the insulating substrate 21 B supports the conductive substrate 22 B.
  • the insulating substrates 21 A and 21 B are spaced apart from each other.
  • the insulating substrate 21 A and the insulating substrate 21 B are spaced apart from each other and aligned in the x direction, as shown in FIGS. 2 , 4 , and 10 .
  • the insulating substrate 21 A has an obverse surface 211 A and a reverse surface 212 A.
  • the obverse surface 211 A and the reverse surface 212 A are spaced apart and face away from each other in the z direction.
  • the obverse surface 211 A faces in the z2 direction, and the reverse surface 212 A faces in the z1 direction.
  • the obverse surface 211 A faces the conductive substrate 22 A, and the reverse surface 212 A is exposed from the sealing resin 70 .
  • another conductive substrate may be bonded to the reverse surface 212 A of the insulating substrate 21 A. In this case, the reverse surface of the conductive substrate is exposed from the sealing resin 70 .
  • the insulating substrate 21 B has an obverse surface 211 B and a reverse surface 212 B.
  • the obverse surface 211 B and the reverse surface 212 B are spaced apart and face away from each other in the z direction.
  • the obverse surface 211 B faces in the z2 direction, and the reverse surface 212 B faces in the z1 direction.
  • the obverse surface 211 B faces the conductive substrate 22 B, and the reverse surface 212 B is exposed from the sealing resin 70 .
  • another conductive substrate may be bonded to the reverse surface 212 B of the insulating substrate 21 B. In this case, the reverse surface of the conductive substrate is exposed from the sealing resin 70 .
  • the conductive substrates 22 A and 22 B are plate-like members that are electrically conductive. As shown in FIG. 10 , each of the conductive substrates 22 A and 22 B according to the present embodiment is a composite substrate including a graphite substrate 220 m and copper films 220 n formed on the respective surfaces of the graphite substrate 220 m in the z direction. Each of the conductive substrates 22 A and 22 B is not limited to having the configuration described above, and may be made of Cu or a Cu alloy. The surfaces of the conductive substrates 22 A and 22 B may be covered with silver plating.
  • the conductive substrates 22 A and 22 B constitute a conductive path to the semiconductor elements 10 , together with the leads (the first power lead 31 , the second power lead 32 , the third power lead 33 , the pair of gate leads 34 A and 34 B, the pair of driver source leads 35 A and 35 B, and the dummy leads 36 ).
  • the conductive substrates 22 A and 22 B are spaced apart from each other. As shown in FIGS. 4 and 10 , the conductive substrate 22 A and the conductive substrate 22 B are spaced apart from each other and aligned in the x direction. As shown in FIG. 4 , each of the conductive substrates 22 A and 22 B has a rectangular shape in plan view.
  • Each of the conductive substrates 22 A and 22 B has a dimension of about 1.0 to 3.5 mm in the z direction.
  • the graphite substrate 220 m has a dimension of about 0.5 to 2.5 mm in the z direction
  • each of the copper films 220 n has a dimension of about 0.25 to 0.5 mm in the z direction.
  • These dimensions in the z direction are not limited to those described above.
  • One of the copper films 220 n of the conductive substrate 22 A, which is located on the upper side in FIG. 10 is an example of the “first metal layer”.
  • One of the copper films 220 n of the conductive substrate 22 B, which is located on the upper side in FIG. 10 is an example of the “second metal layer”.
  • the copper film 220 n of the conductive substrate 22 A located on the upper side in FIG. 10 and the copper film 220 n of the conductive substrate 22 B located on the upper side in FIG. 10 are each an example of the “conductive member”.
  • the material of the copper film 220 n of the conductive substrate 22 A located on the upper side in FIG. 10 and the material of the copper film 220 n of the conductive substrate 22 B located on the upper side in FIG. 10 are each an example of the “first material”.
  • the conductive substrate 22 A is bonded to the insulating substrate 21 A via a substrate bonding member 220 A.
  • the substrate bonding member 220 A may be a conductive bonding member such as silver paste, solder, or sintered metal, or may be an insulating bonding member.
  • the conductive substrate 22 A is offset in the x1 direction relative to the conductive substrate 22 B. The conductive substrate 22 A entirely overlaps with the conductive substrate 22 B as viewed in the x direction.
  • the conductive substrate 22 A has an obverse surface 221 A and a reverse surface 222 A.
  • the obverse surface 221 A and the reverse surface 222 A are spaced apart and face away from each other in the z direction.
  • the obverse surface 221 A faces in the z2 direction, and the reverse surface 222 A faces in the z1 direction.
  • the first semiconductor elements 10 A are mounted on the obverse surface 221 A.
  • the insulating layer 23 A is bonded to the obverse surface 221 A.
  • the conductive substrate 22 B is bonded to the insulating substrate 21 B via a substrate bonding member 220 B.
  • the substrate bonding member 220 B may be a conductive bonding member such as silver paste, solder, or sintered metal, or may be an insulating bonding member.
  • the insulating substrate 22 B has an obverse surface 221 B and a reverse surface 222 B.
  • the obverse surface 221 B and the reverse surface 222 B are spaced apart and face away from each other in the z direction.
  • the obverse surface 221 B faces in the z2 direction, and the reverse surface 222 B faces in the z1 direction.
  • the second semiconductor elements 10 B are mounted on the obverse surface 221 B.
  • the insulating layer 23 B and one end of each intermediate lead 40 are bonded to the obverse surface 221 B.
  • the pair of insulating layers 23 A and 23 B are electrically insulative, and are made of glass epoxy resin or ceramic. As shown in FIG. 4 , each of the pair of insulating layers 23 A and 23 B has a band shape extending in the y direction. As shown in FIGS. 4 and 10 , the insulating layer 23 A is bonded to the obverse surface 221 A of the conductive substrate 22 A. The insulating layer 23 A is offset in the x1 direction relative to the first semiconductor elements 10 A. Alternatively, the insulating layer 23 A may be offset in the x2 direction relative to the first semiconductor elements 10 A. As shown in FIGS.
  • the insulating layer 23 B is bonded to the obverse surface 221 B of the conductive substrate 22 B.
  • the insulating layer 23 B is offset in the x2 direction relative to the second semiconductor elements 10 B.
  • the insulating layer 23 B may be offset in the x1 direction relative to the second semiconductor elements 10 B.
  • the pair of gate layers 24 A and 24 B are electrically conductive and made of, for example, copper or a copper alloy. As shown particularly in FIG. 4 , each of the gate layers 24 A and 24 B includes a band-shaped portion extending in the y direction, and hook-shaped portions protruding from the band-shaped portion.
  • the shape of each of the pair of gate layers 24 A and 24 B is not limited to the shape shown in FIG. 4 .
  • each of the gate layers 24 A and 24 B may be made of only the band-shaped portion without the hook-shaped portions.
  • the gate layer 24 A is provided on the insulating layer 23 A.
  • the gate layer 24 A is electrically connected to the gate electrodes 112 of the first semiconductor elements 10 A via some of the wire members 50 (gate wires 51 described below).
  • the gate layer 24 B is provided on the insulating layer 23 B.
  • the gate layer 24 B is electrically connected to the gate electrodes 112 of the second semiconductor elements 10 B via some of the wire members 50 (gate wires 51 described below).
  • the pair of driver source layers 25 A and 25 B are electrically conductive, and may be made of Cu or a Cu alloy. As shown particularly in FIG. 4 , each of the driver source layers 25 A and 25 B includes a band-shaped portion extending in the y direction, and hook-shaped portions protruding from the band-shaped portion.
  • the shape of each of the pair of driver source layers 25 A and 25 B is not limited to the shape shown in FIG. 4 .
  • each of the driver source layers 25 A and 25 B may be made of only the band-shaped portion without the hook-shaped portions.
  • the driver source layer 25 A is provided on the insulating layer 23 A, together with the gate layer 24 A.
  • the driver source layer 25 A is adjacent to and spaced apart from the gate layer 24 A on the insulating layer 23 A.
  • the driver source layer 25 A is closer to the first semiconductor elements 10 A than the gate layer 24 A in the x direction. Accordingly, the driver source layer 25 A is offset in the x2 direction relative to the gate layer 24 A. Note that the positions of the gate layer 24 A and the driver source layer 25 A in the x direction may be switched around.
  • the driver source layer 25 A is electrically connected to the driver source electrodes 113 of the first semiconductor elements 10 A via some of the wire members 50 (driver source wires 52 ). As shown in FIGS.
  • the driver source layer 25 B is provided on the insulating layer 23 B, together with the gate layer 24 B.
  • the driver source layer 25 B is adjacent to and spaced apart from the gate layer 24 B on the insulating layer 23 B.
  • the driver source layer 25 B is closer to the second semiconductor elements 10 B than the gate layer 24 B. Accordingly, the driver source layer 25 B is offset in the x1 direction relative to the gate layer 24 B. Note that the positions of the gate layer 24 B and the driver source layer 25 B in the x direction may be switched around.
  • the driver source layer 25 B is electrically connected to the driver source electrodes 113 of the second semiconductor elements 10 B via some of the wire members 50 (driver source wires 52 ).
  • the first spacer 26 A and the second spacer 26 B are electrically conductive, and may be made of Cu or a Cu alloy.
  • the material of each of the first spacer 26 A and the second spacer 26 B is not limited to the material described above, and may be a composite of Cu molybdenum (CuMo) or a composite of copper-inver-copper (CIC).
  • the first spacer 26 A and the second spacer 26 B may be made of different materials.
  • Each of the first spacer 26 A and the second spacer 26 B is an example of the “conductive member”, and the material of each of the first spacer 26 A and the second spacer 26 B is an example of the “first material”.
  • the first spacer 26 A is interposed between the conductive substrate 22 A and the first power lead 31 .
  • the first spacer 26 A has a rectangular shape extending in the y direction in plan view.
  • the first spacer 26 A is electrically bonded to the conductive substrate 22 A.
  • the first spacer 26 A is positioned near the edge of the conductive substrate 22 A in the x1 direction in plan view.
  • the first spacer 26 A is provided so that the first power lead 31 is substantially at the same position as the second power lead 32 in the z direction.
  • the first power lead 31 may be bonded directly to the conductive substrate 22 A without the first spacer 26 A.
  • the shape of the first spacer 26 A is not particularly limited.
  • the second spacer 26 B is interposed between the conductive substrate 22 B and the third power lead 33 .
  • the second spacer 26 B has a rectangular shape extending in the y direction in plan view.
  • the second spacer 26 B is electrically bonded to the conductive substrate 22 B.
  • the second spacer 26 B is positioned near the edge of the conductive substrate 22 B in the x2 direction in plan view.
  • the second spacer 26 B is provided so that the third power lead 33 is substantially at the same position as the second power lead 32 in the z direction.
  • the third power lead 33 may be bonded directly to the conductive substrate 22 B without the second spacer 26 B.
  • the shape of the second spacer 26 B is not particularly limited.
  • Each of the leads includes a portion inside the sealing resin 70 and a portion outside the sealing resin 70 . That is, each of the leads includes a portion covered with the sealing resin 70 and a portion exposed from the sealing resin 70 .
  • the leads are used when the semiconductor device A 1 is mounted on the circuit board of an electronic device or the like.
  • the first power lead 31 and the second power lead 32 are metal plates. Each of the metal plates is made of Cu or a Cu alloy.
  • the material of the first power lead 31 and the second power lead 32 is not limited to Cu or a Cu alloy, and may be aluminum, for example.
  • each of the first power lead 31 and the second power lead 32 has a dimension of about 0.8 mm in the z direction. However, the present disclosure is not limited to this.
  • the first power lead 31 and the second power lead 32 are offset in the x1 direction in the semiconductor device A 1 . Source voltage is applied across the first power lead 31 and the second power lead 32 , for example.
  • the first power lead 31 is a positive terminal (P terminal), and the second power lead 32 is a negative terminal (N terminal).
  • the first power lead 31 and the second power lead 32 are spaced apart from each other.
  • the second power lead 32 is spaced apart from the conductive substrate 22 A.
  • Each of the first power lead 31 and the second power lead 32 is an example of the “conductive member”, and the material of each of the first power lead 31 and the second power lead 32 is an example of the “first material”.
  • the first power lead 31 includes a pad portion 311 and a terminal portion 312 .
  • the pad portion 311 is the portion of the first power lead 31 that is covered with the sealing resin 70 .
  • the pad portion 311 is electrically connected to the conductive substrate 22 A via the first spacer 26 A. As shown in FIGS. 2 , 4 , and 10 , the pad portion 311 is electrically bonded to the first spacer 26 A.
  • the method for the electrical bonding is not particularly limited, and may be laser bonding, or bonding with a conductive bonding member, for example.
  • the terminal portion 312 is the portion of the first power lead 31 that is exposed from the sealing resin 70 . As shown in FIGS. 3 , 4 , 6 , 7 and 10 , the terminal portion 312 extends from the sealing resin 70 in the x1 direction.
  • the second power lead 32 includes a pad portion 321 and a terminal portion 322 .
  • the pad portion 321 is the portion of the second power lead 32 that is covered with the sealing resin 70 .
  • the pad portion 321 includes a joining portion 321 a , a plurality of extending portions 321 b , and a connecting portion 321 c.
  • the joining portion 321 a has a band shape extending in the y direction.
  • the joining portion 321 a connects the extending portions 321 b.
  • Each of the extending portions 321 b has a band shape extending from the joining portion 321 a in the x2 direction.
  • each of the extending portions 321 b extends from the joining portion 321 a in the x direction to overlap with a second semiconductor element 10 B in plan view.
  • the extending portions 321 b extend across the conductive substrate 22 A and the conductive substrate 22 B in plan view.
  • the tip of each of the extending portions 321 b overlaps with a second block 62 in plan view.
  • the extending portions 321 b are aligned and spaced apart from each other in the y direction.
  • the extending portions 321 b are electrically connected to the source electrodes 111 (source electrodes) of the respective second semiconductor elements 10 B via the conductive blocks 60 . As shown in FIGS. 4 and 10 , the tip of each of the extending portions 321 b is electrically bonded to a second block 62 .
  • the method for the electrical bonding is not particularly limited, and may be laser bonding, or bonding with a conductive bonding member, for example.
  • the connecting portion 321 c connects the joining portion 321 a and the terminal portion 322 .
  • the connecting portion 321 c extends in the x1 direction from an edge of the joining portion 321 a , specifically from a portion of the edge that is offset in the y2 direction and in the x1 direction in plan view, as shown in FIG. 4 .
  • the terminal portion 322 is the portion of the second power lead 32 that is exposed from the sealing resin 70 . As shown in FIGS. 1 , 3 , 4 , and 7 , the terminal portion 322 extends from the sealing resin 70 in the x1 direction.
  • the terminal portion 322 has a rectangular shape in plan view. As shown in FIGS. 3 , 4 , and 7 , the terminal portion 322 is offset in the y2 direction relative to the terminal portion 312 of the first power lead 31 in plan view. In the present embodiment, the terminal portion 322 has the same shape as the terminal portion 312 , but the present disclosure is not limited to this.
  • the third power lead 33 is a metal plate.
  • the metal plate is made of Cu or a Cu alloy.
  • the material of the third power lead 33 is not limited to Cu or a Cu alloy, and may be aluminum, for example.
  • the third power lead 33 is offset in the x2 direction in the semiconductor device A 1 .
  • the third power lead 33 outputs AC power (voltage) converted by the semiconductor elements 10 .
  • the third power lead 33 includes a pad portion 331 and a terminal portion 332 .
  • the pad portion 331 is the portion of the third power lead 33 that is covered with the sealing resin 70 .
  • the pad portion 331 is electrically connected to the conductive substrate 22 B via the second spacer 26 B. As shown in FIGS. 2 , 4 , and 10 , the pad portion 331 is electrically bonded to the second spacer 26 B.
  • the method for the electrical bonding is not particularly limited, and may be laser bonding, or bonding with a conductive bonding member, for example.
  • the terminal portion 332 is the portion of the third power lead 33 that is exposed from the sealing resin 70 . As shown in FIGS. 3 , 4 , 6 , 7 and 10 , the terminal portion 332 extends from the sealing resin 70 in the x2 direction.
  • the pair of gate leads 34 A and 34 B are positioned adjacent to the conductive substrates 22 A and 22 B in the y direction.
  • a gate voltage for driving the first semiconductor elements 10 A is applied to the gate lead 34 A.
  • a gate voltage for driving the second semiconductor elements 10 B is applied to the gate lead 34 B.
  • the pair of gate leads 34 A and 34 B each include a pad portion 341 and a terminal portion 342 .
  • the pad portion 341 of each of the gate leads 34 A and 34 B is covered with the sealing resin 70 .
  • the gate leads 34 A and 34 B are supported by the sealing resin 70 .
  • Each of the terminal portions 342 is connected to the corresponding pad portion 341 and exposed from the sealing resin 70 .
  • Each of the terminal portions 342 has an L-shape as viewed in the x direction. In the present embodiment, each of the terminal portions 342 protrudes from the surface of the sealing resin 70 that faces in the y1 direction (resin side surface 733 ).
  • the pair of driver source leads 35 A and 35 B are positioned adjacent to the pair of gate leads 34 A and 34 B in the x direction.
  • the driver source lead 35 A provides a reference potential for the gate voltage for driving the first semiconductor elements 10 A.
  • the driver source lead 35 B provides a reference potential for the gate voltage for driving the second semiconductor elements 10 B.
  • the pair of driver source leads 35 A and 35 B each include a pad portion 351 and a terminal portion 352 .
  • the pad portion 351 of each of the driver source leads 35 A and 35 B is covered with the sealing resin 70 .
  • the driver source leads 35 A and 35 B are supported by the sealing resin 70 .
  • Each of the terminal portions 352 is connected to the corresponding pad portion 351 and exposed from the sealing resin 70 .
  • Each of the terminal portions 352 has an L-shape as viewed in the x direction. In the present embodiment, each of the terminal portions 352 protrudes from the surface of the sealing resin 70 that faces in the y1 direction (resin side surface 733 ).
  • each of the dummy leads 36 is positioned opposite the driver source lead 35 A or 35 B with respect to the gate lead 34 A or 34 B in the x direction.
  • the number of dummy leads 36 is four. Two of the four dummy leads 36 are offset in one sense of the x direction (i.e., x2 direction). The other two of the four dummy leads 36 are offset in the other sense of the x direction (i.e., x1 direction).
  • Each of the dummy leads 36 is not limited to the configuration described above. It is possible to omit the dummy leads 36 .
  • each of the dummy leads 36 includes a pad portion 361 and a terminal portion 362 .
  • the pad portion 361 of each of the dummy leads 36 is covered with the sealing resin 70 .
  • the dummy leads 36 are supported by the sealing resin 70 .
  • Each of the terminal portions 362 is connected to the corresponding pad portion 361 and exposed from the sealing resin 70 .
  • Each of the terminal portions 362 has an L-shape as viewed in the x direction. In the present embodiment, each of the terminal portions 362 protrudes from the surface of the sealing resin 70 that faces in the y1 direction (resin side surface 733 ).
  • the gate leads 34 A and 34 B, the driver source leads 35 A and 35 B, and the dummy leads 36 have substantially the same shape. As shown in FIGS. 1 to 7 , these leads are aligned along the x direction. In the semiconductor device A 1 , the leads (the first power lead 31 , the second power lead 32 , the third power lead 33 , the pair of gate leads 34 A and 34 B, the pair of driver source leads 35 A and 35 B, and the dummy leads 36 ) are formed from the same lead frame.
  • the intermediate leads 40 connect the first semiconductor elements 10 A and the conductive substrate 22 B.
  • the intermediate leads 40 are made of Cu or a Cu alloy, for example.
  • the material of the intermediate leads 40 is not limited to Cu or a Cu alloy, and may be a clad material such as CIC, or aluminum.
  • Each of the intermediate leads 40 is a connecting member having a flat plate-like shape. As shown in FIG. 4 , each of the intermediate leads 40 has a rectangular shape extending in the x direction in plan view. The intermediate leads 40 overlap with the extending portions 321 b of the second power lead 32 in plan view.
  • Each of the intermediate leads 40 is an example of the “conductive member”, and the material of each of the intermediate leads 40 is an example of the first material”.
  • each of the intermediate leads 40 includes a first bonding portion 41 , a second bonding portion 42 , and a communicating portion 43 .
  • the first bonding portion 41 is a portion bonded to the first block 61 .
  • the first bonding portion 41 and the first block 61 are electrically bonded to each other.
  • the method for the electrical bonding is not particularly limited, and may be laser bonding, or bonding with a conductive bonding member, for example.
  • the second bonding portion 42 is a portion bonded to the conductive substrate 22 B.
  • the second bonding portion 42 and the conductive substrate 22 B are electrically bonded to each other.
  • the method for the electrical bonding is not particularly limited, and may be laser bonding, or bonding with a conductive bonding member, for example.
  • the communicating portion 43 is connected to the first bonding portion 41 and the second bonding portion 42 .
  • the communicating portion 43 has the same dimension in the z direction as each of the first bonding portion 41 and the second bonding portion 42 .
  • the communicating portion 43 is partially bent in the z direction. With this bent portion, the communicating portion 43 can connect the first bonding portion 41 and the second bonding portion 42 that are located at different positions in the z direction.
  • the wire members 50 are wires (bonding wires).
  • the wire members 50 are electrically conductive, and may be made of aluminum, gold, or Cu.
  • the wire members 50 in the present embodiment include a plurality of gate wires 51 , a plurality of driver source wires 52 , a pair of first connecting wires 53 , and a pair of second connecting wires.
  • each of the gate wires 51 has one end (first end) bonded to the gate electrode 112 of a semiconductor element 10 and the other end (second end) bonded to either one of the gate layers 24 A and 24 B.
  • the gate wires 51 include those electrically connecting the gate electrodes 112 of the first semiconductor elements 10 A and the gate layer 24 A, and those electrically connecting the gate electrodes 112 of the second semiconductor elements 10 B and the gate layer 24 B.
  • each of the driver source wires 52 has one end bonded to the driver source electrode 113 of a semiconductor element 10 and the other end bonded to either one of the driver source layers 25 A and 25 B.
  • the driver source wires 52 include those electrically connecting the driver source electrodes 113 of the first semiconductor elements 10 A and the driver source layer 25 A, and those electrically connecting the driver source electrodes 113 of the second semiconductor elements 10 B and the driver source layer 25 B.
  • one of the pair of first connecting wires 53 connects the gate layer 24 A and the gate lead 34 A, and the other connects the gate layer 24 B and the gate lead 34 B.
  • One of the first connecting wires 53 has one end bonded to the gate layer 24 A and the other end bonded to the pad portion 341 of the gate lead 34 A.
  • the other one of the first connecting wires 53 has one end bonded to the gate layer 24 B and the other end bonded to the pad portion 341 of the gate lead 34 B.
  • one of the pair of second connecting wires connects the driver source layer 25 A and the driver source lead 35 A, and the other connects the driver source layer 25 B and the driver source lead 35 B.
  • One of the second connecting wires has one end bonded to the driver source layer 25 A and the other end bonded to the pad portion 351 of the driver source lead 35 A.
  • the other one of the second connecting wires 54 has one end bonded to the driver source layer 25 B and the other end bonded to the pad portion 351 of the driver source lead 35 B.
  • the conductive blocks 60 are electrically conductive.
  • the conductive blocks 60 are bonded to the respective semiconductor elements 10 .
  • Each of the conductive blocks 60 has a dimension of about 0.1 to 2.0 mm in the z direction, but the present disclosure is not limited to this.
  • the conductive blocks 60 include the first blocks 61 and the second blocks 62 .
  • the first blocks 61 are bonded to the respective first semiconductor elements 10 A.
  • the first blocks 61 are electrically bonded to the first semiconductor elements 10 A by solder, for example.
  • the first blocks 61 face the element obverse surfaces 101 of the respective first semiconductor elements 10 A.
  • each of the first blocks 61 in the present embodiment is in the form of a columnar body and has a rectangular shape in plan view.
  • the shape of each of the first blocks 61 in plan view is not limited to this, and may be circular, elliptical, or polygonal.
  • the first blocks 61 are made of Cu or a Cu alloy, for example.
  • the second blocks 62 are bonded to the respective second semiconductor elements 10 B.
  • the second blocks 62 are electrically bonded to the second semiconductor elements 10 B by solder, for example.
  • the second blocks 62 face the element obverse surfaces 101 of the respective second semiconductor elements 10 B.
  • each of the second blocks 62 has a dimension of about 1.83 mm in the z direction, for example.
  • the present disclosure is not limited to this.
  • each of the second blocks 62 in the present embodiment is in the form of a columnar body and has a rectangular shape in plan view.
  • the shape of each of the second blocks 62 in plan view is not limited to this, and may be circular, elliptical, or polygonal.
  • the second blocks 62 are made of Cu or a Cu alloy, for example.
  • each first block 61 in the z direction is smaller than the dimension of each second block 62 in the z direction.
  • the dimension of each second block 62 in the z direction is about 1.83 mm as described above. Accordingly, the dimension of each first block 61 in the z direction is smaller than this value. In this way, the extending portions 321 b of the second power lead 32 can be arranged above the intermediate leads 40 .
  • the capacitor 81 is a chip-type capacitor having a first end and a second end, where the first end is placed on the pad portion 311 of the first power lead 31 and the second end is placed on the joining portion 321 a of the second power lead 32 . Bonding between the capacitor 81 and each of the power leads 31 and 32 may be achieved with a conductive bonding member, for example. Electrically connecting the capacitor 81 to the first power lead 31 and the second power lead 32 can stabilize the source voltage (input voltage) applied across the first power lead 31 and the second power lead 32 .
  • the capacitor 81 may also be referred to as a DC-link capacitor. Unlike the present embodiment, it is possible to omit the capacitor 81 .
  • the sealing resin 70 covers the semiconductor elements 10 , a portion of the support substrate 20 , portions of the leads (the first power lead 31 , the second power lead 32 , the third power lead 33 , the pair of gate leads 34 A and 34 B, the pair of driver source leads 35 A and 35 B, and the dummy leads 36 ), the intermediate leads 40 , the wire members 50 , and the conductive blocks 60 .
  • the sealing resin 70 is made of epoxy resin, for example.
  • the sealing resin 70 has a resin obverse surface 71 , a resin reverse surface 72 , and a plurality of resin side surfaces 731 to 734 .
  • the resin obverse surface 71 and the resin reverse surface 72 are spaced apart and face away from each other in the z direction.
  • the resin obverse surface 71 faces in the z2 direction
  • the resin reverse surface 72 faces in the z1 direction.
  • the resin reverse surface 72 has a frame shape surrounding the reverse surface 212 A of the insulating substrate 21 A and the reverse surface 212 B of the insulating substrate 21 B in plan view. The reverse surfaces 212 A and 212 B are exposed from the resin reverse surface 72 .
  • each of the resin side surfaces 731 to 734 is connected to the resin obverse surface 71 and the resin reverse surface 72 and sandwiched between them in the z direction.
  • the resin side surfaces 731 and 732 are spaced apart and face away from each other in the x direction.
  • the resin side surface 731 faces in the x1 direction, and the resin side surface 732 faces in the x2 direction.
  • the resin side surfaces 733 and 734 are spaced apart and face away from each other in the y direction.
  • the resin side surface 733 faces in the y1 direction, and the resin side surface 734 faces in the y2 direction.
  • the covering layer 90 covers at least a portion of the “conductive member”, and is made of a second material.
  • the second material satisfies at least one of the following three requirements: (1) having a magnetic permeability higher than the first material of the “conductive member”; (2) having an electrical resistivity higher than the first material; and (3) having a dielectric loss tangent larger than zero (larger than the dielectric loss tangent of an ideal dielectric material).
  • the first material is Cu, for example.
  • the second material having a magnetic permeability higher than the first material may be a magnetic metal such as Ni, Co, or Fe.
  • the second material having an electrical resistivity higher than the first material may be a metal such as Ni, W, or Mo, a conductive polymer, or a transparent conductive film.
  • the second material having a dielectric loss tangent larger than zero may be a dielectric material.
  • the magnetic permeability of the second material is set higher than the magnetic permeability of the first material, the relative magnetic permeability of the second material is preferably not less than 10, for example.
  • the electrical resistivity of the second material is set higher than the electrical resistivity of the first material, the electrical resistivity of the second material is preferably not less than twice the electrical resistivity of the first material, for example. Concerning the requirement (3) above, the dielectric loss tangent of the second material is preferably not less than 0.01.
  • the thickness of the covering layer 90 is not particularly limited, and may be 1 ⁇ m to 5 ⁇ m, for example. When the covering layer 90 is made of metal, the covering layer 90 can be formed by plating such as magnetic plating.
  • the second material constituting the covering layer 90 may be a magnetic metal that has a magnetic permeability higher than the first material and also an electrical resistivity higher than the first material.
  • the covering layer 90 may be configured such that the magnetic permeability of the second material is higher than the magnetic permeability of the first material, and that the dielectric loss tangent of the second material is larger than zero.
  • the covering layer 90 may be configured such that the electrical resistivity of the second material is higher than the electrical resistivity of the first material, and that the dielectric loss tangent of the second material is larger than zero.
  • the covering layer 90 may be configured such that the magnetic permeability of the second material is higher than the magnetic permeability of the first material, that the electrical resistivity of the second material is higher than the electrical resistivity of the first material, and that the dielectric loss tangent of the second material is larger than zero.
  • the covering layer 90 in the present embodiment has a first portion 91 and a second portion 92 .
  • the first portion 91 covers at least a portion of the first power lead 31 .
  • the first portion 91 covers the entirety of the first power lead 31 .
  • the second portion 92 covers at least a portion of the second power lead 32 .
  • the second portion 92 covers the entirety of the second power lead 32 .
  • the first portion 91 when the second power lead 32 functions as the path of the main circuit current, the entire periphery of the cross section of the second power lead 32 is covered with the second portion 92 .
  • the covering layer 90 is provided for the conductive member that forms the path of the main circuit current in the semiconductor device A 1 . More specifically, the covering layer 90 is provided at a portion having a high alternating current density due to the skin effect.
  • the magnetic permeability of the second material constituting the covering layer 90 is higher than the magnetic permeability of the first material (e.g., Cu) constituting the conductive member (e.g., the first power lead 31 and the second power lead 32 ), the skin effect becomes more prominent, thus causing an increase in the alternating-current resistance of the current path. This makes it possible to attenuate the alternating current flowing through the covering layer 90 and suppress ringing.
  • skin effect is relatively unlikely to occur in the low-frequency component of the current. Accordingly, the low-frequency component of the current is not unduly attenuated by the covering layer 90 . Since ringing can be suppressed, it is possible to simplify the snubber circuit in the semiconductor device A 1 and improve the reliability of the semiconductor device A 1 per se.
  • the electrical resistivity of the second material constituting the covering layer 90 is higher than the electrical resistivity of the first material (e.g., Cu) constituting the conductive member (e.g., the first power lead 31 and the second power lead 32 ), it is possible to attenuate the alternating current flowing through the covering layer 90 and suppress ringing. As described above, the low-frequency component of the current is not unduly attenuated by the covering layer 90 .
  • the dielectric loss tangent of the second material constituting the covering layer 90 is larger than zero (larger than the dielectric loss tangent of an ideal dielectric material), it is possible to consume the energy of the alternating current flowing through the covering layer 90 as dielectric loss and suppress ringing.
  • the above-described advantages of the second material which are obtained by the requirements relating to the magnetic permeability, the electrical resistivity, and the dielectric loss tangent, can be achieved independently of each other. Accordingly, while ringing can be suppressed effectively when only one of the requirements relating to the magnetic permeability, electrical resistivity, and dielectric loss tangent of the second material is satisfied, it can be suppressed more effectively when two of the requirements are satisfied, and even more so when all of the three requirements are satisfied.
  • FIGS. 12 to 21 show variations and other embodiments according to the present disclosure.
  • elements identical or similar to those in the above embodiment are provided with the same reference signs.
  • FIG. 12 shows a first variation of the semiconductor device A 1 .
  • the configuration of the covering layer 90 is different from the above example.
  • the first portion 91 which is a portion of the covering layer 90 , covers only a portion of the periphery, rather than the entire periphery, of the cross section of the first power lead 31 through which the main circuit current flows. More specifically, the first portion 91 covers only three sides (top side and two lateral sides) of the rectangular cross section of the first power lead 31 , and does not cover the remaining side (bottom side) thereof (i.e., the bottom side is exposed from the first portion 91 ). The three sides (the top side and the two lateral sides) are fully covered with the first portion 91 .
  • FIG. 13 shows a second variation of the semiconductor device A 1 .
  • the first portion 91 which is a portion of the covering layer 90 , covers the entire periphery of the cross section of the first power lead 31 through which the main circuit current flows, with each of the sides (the top side, the two lateral sides, and the bottom side) partially exposed from the first portion 91 (i.e., with each of the sides partially covered by the first portion 91 ).
  • the first portion 91 has a plurality of gaps arranged at intervals along the entire periphery of the rectangular cross section. The gaps include one or more gaps at each side of the cross section.
  • the first portion 91 (covering layer 90 ) having such a configuration may be formed with a plurality of small holes or slits.
  • the first portion 91 (covering layer 90 ) may be a group of small regions that are spaced apart from each other.
  • the semiconductor devices A 11 and A 12 can also suppress ringing.
  • the covering layer 90 is not limited to a specific configuration. Even when the covering layer 90 covers a portion of the conductive member (see FIGS. 12 and 13 ), ringing can be suppressed depending on the position and size of the region formed with the covering layer 90 .
  • FIGS. 14 to 16 show a semiconductor device according to a second embodiment of the present disclosure.
  • the covering layer 90 has a configuration different from the covering layer 90 of the semiconductor device A 1 .
  • the first portion 91 covers a portion of the first power lead 31
  • the second portion 92 covers a portion of the second power lead 32 . More specifically, the first portion 91 does not cover the portion of the first power lead 31 that forms the path between the first semiconductor elements 10 A and the capacitor 81 . In other words, the first portion 91 covers the terminal portion 312 of the first power lead 31 , but does not cover the pad portion 311 .
  • the second portion 92 does not cover the portion of the second power lead 32 that forms the path between the second semiconductor elements 10 B and the capacitor 81 .
  • the second portion 92 covers the terminal portion 322 of the second power lead 32 and the connecting portion 321 c of the pad portion 321 , but does not cover the joining portion 321 a or the extending portions 321 b.
  • the second embodiment can also suppress ringing.
  • the portions of the first power lead 31 and the second power lead 32 that constitute the path in which only the charge/discharge current of the capacitor 81 flows have a resistance equivalent to the ESR of the capacitor 81 .
  • the path is where an abrupt charge/discharge current flows to the capacitor 81 , it is not preferable for the AC resistance to be too high.
  • the configuration described above where the first portion 91 and the second portion 92 do not cover the portions of the first power lead 31 and the second power lead 32 is preferable to perform abrupt charge and discharge to the capacitor 81 .
  • FIGS. 17 to 19 show a semiconductor device according to a third embodiment of the present disclosure.
  • the covering layer 90 has a configuration different from the covering layers 90 of the semiconductor devices A 1 and A 2 .
  • the covering layer 90 includes a first portion 91 , a second portion 92 , a third portion 93 , a fourth portion 94 , a fifth portion 95 , and a sixth portion 96 .
  • the first portion 91 and the second portion 92 have the same configurations as the first portion 91 and the second portion 92 in the semiconductor device A 1 .
  • the third portion 93 covers the first metal layer, namely one of the copper films 220 n of the conductive substrate 22 A.
  • the fourth portion 94 covers the first spacer 26 A.
  • the fifth portion 95 covers the second metal layer, namely one of the copper films 220 n of the conductive substrate 22 B.
  • the sixth portion 96 covers the intermediate leads 40 .
  • the third portion 93 covers every surface of the copper film 220 n except the surface to which the graphite substrate 220 m is bonded.
  • the fifth portion 95 covers every surface of the copper film 220 n except the surface to which the graphite substrate 220 m is bonded.
  • the third embodiment can also suppress ringing.
  • the areas where the covering layer 90 is provided can be changed appropriately depending on a desired degree of ringing suppression and the configuration of the semiconductor device.
  • FIGS. 20 and 21 show a semiconductor device according to a fourth embodiment of the present disclosure.
  • the configuration of the first power lead 31 and the second power lead 32 is different from the examples in the above embodiments.
  • the terminal portion 312 of the first power lead 31 and the terminal portion 322 of the second power lead 32 overlap with each other as viewed in the z direction.
  • the terminal portion 312 is covered with the first portion 91
  • the terminal portion 322 is covered with the second portion 92 .
  • An insulator 89 is provided between the terminal portion 312 and the terminal portion 322 .
  • the insulator 89 is provided to insulate the terminal portion 312 and the terminal portion 322 from each other when an expected voltage is applied across the terminal portion 312 and the terminal portion 322 .
  • the second material of the covering layer 90 has at least a dielectric loss tangent larger than 0 (larger than the dielectric loss tangent of an ideal dielectric material), such as a dielectric loss tangent of not less than 0.01.
  • a dielectric loss tangent larger than 0 (larger than the dielectric loss tangent of an ideal dielectric material), such as a dielectric loss tangent of not less than 0.01.
  • the fourth embodiment can also suppress ringing.
  • the capacitance formed by the terminal portion 312 , the terminal portion 322 , and the covering layer 90 and the insulator 89 that are provided therebetween is expected to achieve a synergistic effect with the capacitor 81 , and can enhance the effect of stabilizing the source voltage (input voltage) applied across the first power lead 31 and the second power lead 32 .
  • the semiconductor device according to the present disclosure is not limited to the above embodiments and variations. Various design changes can be made to the specific configurations of the elements of the semiconductor device according to the present disclosure.
  • a semiconductor device includes embodiments described in the following clauses.
  • a semiconductor device comprising:
  • a conductive member that forms a path of a current switched by the semiconductor element, and that is made of a first material
  • a covering layer that covers at least a portion of the conductive member, and that is made of a second material
  • the second material satisfies at least one of the following three requirements:
  • the second material is a magnetic conductor having a magnetic permeability higher than the first material and having an electrical resistivity higher than the first material.
  • the at least one semiconductor element includes a plurality of semiconductor elements that form a half-bridge including at least a pair of upper arm and lower arm,
  • the plurality of semiconductor elements include a first semiconductor element in the upper arm and a second semiconductor element in the lower arm,
  • the conductive member includes a first metal layer connected to a drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to a source electrode of the second semiconductor element,
  • the first end of the capacitor is connected to the first power lead, and the second end of the capacitor is connected to the second power lead, and
  • the covering layer includes a first portion covering the first power lead and a second portion covering the second power lead.
  • the first power lead includes a portion forming a path between the first semiconductor element and the capacitor, and the portion of the first power lead is not covered with the first portion.
  • the second power lead includes a portion forming a path between the second semiconductor element and the capacitor, and the portion of the second power lead is not covered with the second portion.
  • the covering layer includes a third portion covering the first metal layer.
  • the conductive member includes a second metal layer connected to a drain electrode of the second semiconductor element, and a third power lead connected to the second metal layer, and
  • the second metal layer and the third power lead are not covered with the covering layer.
  • the conductive member includes an intermediate lead connected to a source electrode of the first semiconductor element and the second metal layer, and the intermediate lead is not covered with the covering layer.
  • the conductive member includes a first spacer interposed between the first metal layer and the first power lead, and
  • the covering layer includes a fourth portion covering the first spacer.
  • the conductive member includes a conductor interposed between the source electrode of the second semiconductor element and the second power lead.
  • the semiconductor element is one of a SiC MOSET, a SiC IGBT, a Si MOSFET, a Si IGBT, and a GaN HEMT.

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