CN113228265A - 半导体组件的电路构造 - Google Patents

半导体组件的电路构造 Download PDF

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Publication number
CN113228265A
CN113228265A CN202080007759.6A CN202080007759A CN113228265A CN 113228265 A CN113228265 A CN 113228265A CN 202080007759 A CN202080007759 A CN 202080007759A CN 113228265 A CN113228265 A CN 113228265A
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Prior art keywords
circuit pattern
circuit
wiring member
straight portion
disposed
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CN202080007759.6A
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矶崎诚
高桥圣一
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

扩大额定电流并且还抑制电路图案的异常过热。半导体组件(1)的电路构造包括：绝缘电路基板(3)，其在绝缘板(30)的上表面形成电路图案(31)而成；以及半导体元件(4)，其配置于电路图案的上表面。电路图案具有：直部(35a)，其沿规定方向延伸；以及角部(35b)，其向与直部的延伸方向不同的方向弯曲。在直部的上表面配置有布线构件(W6)，该布线构件(W6)偏向角部的外周侧地沿着直部的延伸方向配置。

Description

半导体组件的电路构造
技术领域
本发明涉及一种半导体组件的电路构造。
背景技术
半导体装置具有基板，在该基板设置有IGBT(Insulated Gate BipolarTransistor：绝缘栅双极晶体管)、功率MOSFET(Metal Oxide Semiconductor FieldEffect Transistor：金属氧化物半导体场效应晶体管)、FWD(Free Wheeling Diode：续流二极管)等半导体元件，半导体装置被用于变换器装置等。
在民生、工业用的马达驱动用等中被广泛使用的变换器装置由MOSFET、IGBT等半导体开关元件(开关元件)和驱动该半导体开关元件的驱动用集成电路(IC芯片)构成。另外，作为用于使设备小型化以及保护电路内置的方式，使用将上述的开关元件和IC芯片一体封装而成的IPM(Intelligent Power Module：智能功率模块)。
然而，在以下所示的专利文献1、2中，提案有一种在导电图案上配置导电构件(接合线)从而能够在半导体组件或集成电路中流通大电流的技术。另外，在专利文献3中，为了削减基板上的电路图案导电层的电阻值，在电路图案导电层上配置有金属线布线。而且，在专利文献4中，为了防止由浪涌电流导致的导电路径的熔断，在导电路径上接合连接有金属线。
现有技术文献
专利文献
专利文献1：日本特开2010－251551号公报
专利文献2：日本特开平6－29646号公报
专利文献3：日本特开2001－85611号公报
专利文献4：日本特开平6－338668号公报
发明内容
发明要解决的问题
另外，近年来，开发有一种将IGBT元件的功能和FWD元件的功能一体化而成的RC(Reverse Conducting：反向导通)－IGBT元件。根据RC－IGBT元件，以与以往相同的额定电流进行比较时，芯片面积缩小，能够进行更高密度的安装。即，在以与以往相同的芯片面积进行比较时，能够扩大额定电流。
如此，通过采用RC－IGBT元件，能够实现在以往的封装尺寸下无法实现的额定电流，另一方面，伴随通电量的进一步扩大(高电流密度化)，电路网的发热量与电流的平方成比例地增加。其结果，可能产生在以往的额定电流中不成为问题的电路图案的异常过热。
本发明即是鉴于这一点而做成的，目的之一在于提供一种能够扩大额定电流并且还能够抑制电路图案的异常过热的半导体组件的电路构造。
用于解决问题的方案
本发明的一技术方案的半导体组件的电路构造的特征在于，该半导体组件的电路构造包括：绝缘电路基板，其在绝缘板的上表面形成电路图案而成；以及半导体元件，其配置于所述电路图案的上表面，所述电路图案具有：直部，其沿规定方向延伸；以及角部，其向与所述直部的延伸方向不同的方向弯曲，在所述直部的上表面配置有布线构件，该布线构件偏向所述角部的外周侧地沿着所述直部的延伸方向配置。
另外，本发明的另一技术方案的半导体组件的电路构造的特征在于，该半导体组件的电路构造包括：绝缘电路基板，其在绝缘板的上表面形成电路图案而成；以及半导体元件，其配置于所述电路图案的上表面，所述电路图案具有：直部，其沿规定方向延伸；以及角部，其向与所述直部的延伸方向不同的方向弯曲，在所述角部的上表面配置有布线构件，该布线构件偏向外周侧地沿着弯曲方向配置。
发明的效果
根据本发明，能够扩大额定电流并且还能够抑制电路图案的异常过热。
附图说明
图1是表示本实施方式的半导体组件的一个例子的俯视示意图。
图2是表示本实施方式的半导体组件的一个例子的剖视示意图。
图3是本实施方式的半导体组件的电路构造的局部放大图。
图4是表示第1变形例的半导体组件的电路构造的示意图。
图5是表示第2变形例的半导体组件的电路构造的示意图。
图6是表示第3变形例的半导体组件的电路构造的示意图。
图7是表示第4变形例的半导体组件的电路构造的示意图。
图8是表示第5变形例的半导体组件的电路构造哦示意图。
具体实施方式
以下，说明能够应用本发明的半导体组件。图1是表示本实施方式的半导体组件的一个例子的俯视示意图。图2是表示本实施方式的半导体组件的一个例子的剖视示意图。具体而言，图2是沿着图1的A－A剖切的剖视图。此外，以下所示的半导体组件仅为一个例子，并不限定于此，能够进行适当变更。在本说明书中，俯视是指自与后述的绝缘电路基板垂直的方向观察半导体组件的情况。
半导体组件1例如被应用于功率模块等电力转换装置。如图1和图2所示，半导体组件1构成为包含散热板2、绝缘电路基板3、多个半导体元件4等。
散热板2起到作为绝缘电路基板3的基底板的作用，由铜、铝等导热性良好的金属板形成为俯视矩形形状。
在散热板2的上表面(主表面)配置绝缘电路基板3。绝缘电路基板3通过层叠金属层和绝缘层而构成，形成为俯视方形形状。在本实施方式中，两个绝缘电路基板3在散热板2的长度方向上排列配置。两个绝缘电路基板3例如经由焊锡等接合材料(未图示)配置于散热板2的上表面。
绝缘电路基板3例如由DCB(Direct Copper Bonding：直接铜键合)基板、AMB(Active Metal Brazing：活性金属钎焊)基板构成。具体而言，绝缘电路基板3具有：绝缘板30，其具有上表面和下表面；电路图案31，其形成于绝缘板30的上表面(主表面)；以及金属板32，其形成于绝缘板30的下表面。绝缘板30由陶瓷、树脂等绝缘材料形成为俯视方形形状。对于绝缘材料，例如使用氧化铝(Al2O3)、氮化铝(AlN)、氮化硅(Si3N4)等陶瓷材料、环氧等树脂材料、或使用陶瓷材料作为填料而成的环氧树脂材料。
电路图案31由规定厚度的导电体构成。电路图案31的厚度可以为50μm以上且2.0mm以下。优选为100μm以上且500μm以下。若电路图案31过薄，则电阻变大而可能产生损失、发热。若电路图案31过厚，则可能在与绝缘板30之间的应力的作用下产生翘曲、破损。电路图案31的材质例如为铜、铝或至少以其中一种材质为主要成分的合金。此外，对于电路图案31的表面，例如也可以形成有镍、或镍合金。电路图案31具有俯视呈独立的岛状(彼此电绝缘的状态)的多个电路图案33～36。在图1中，在位于纸面左侧的绝缘板30上形成有3个独立的电路图案33～35，在位于纸面右侧的绝缘板30上形成有4个独立的电路图案33～36。此外，为了方便说明，由共用的附图标记表示在左右的各个绝缘板30上对应的电路图案31。另外，对于各电路图案31，后述进行说明。
金属板32与电路图案31相同地由利用铜箔等形成的规定厚度的金属层构成。金属板32具有平面，并具有覆盖绝缘板30的下表面的大致整体的俯视方形形状。具体而言，金属板32的外缘部位于比绝缘板30的外缘部略靠内侧的位置。金属板32的下表面朝向散热板2的上表面。金属板32经由未图示的接合材料与散热板2的上表面接合。
在电路图案33的上表面配置有4个半导体元件4。半导体元件4例如利用硅(Si)、碳化硅(SiC)等的半导体基板形成为俯视方形形状。在本实施方式中，半导体元件4由将IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极晶体管)元件和FWD(Free WheelingDiode：续流二极管)元件的功能一体化而成的RC(Reverse Conducting：反向导通)－IGBT元件构成。
此外，半导体元件4并不限定于此，也可以单独使用IGBT、功率MOSFET(MetalOxide Semiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)等开关元件、FWD(Free Wheeling Diode：续流二极管)等二极管。另外，还可以使用对反偏压具有充分的耐压性的RB(Reverse Blocking：逆阻型)－IGBT等。另外，半导体元件4的形状、配置个数、配置部位等能够适当变更。
在半导体元件4的上表面作为主电极设有未图示的输入电极(阳极电极)。在半导体元件4的下表面作为主电极设有未图示的输出电极(阴极电极)。半导体元件4的下表面例如经由焊锡等接合材料(未图示)与电路图案33的上表面电接合。
另外，在散热板2的外周侧的上表面配置有框状的壳体构件5。壳体构件5例如利用合成树脂成形，并经由粘接剂(未图示)与散热板2接合。壳体构件5具有包围两个绝缘电路基板3的外周的环状壁部50。环状壁部50形成为沿着散热板2的外形的俯视四方环状。另外，环状壁部50在半导体组件1的厚度方向(铅垂方向)上立起。在环状壁部50的上表面的内周侧形成有下降了一个台阶的台阶部51。台阶部51由四方环状的凹部形成，台阶部51的上表面设于低于环状壁部50的上表面的位置。
另外，在环状壁部50的沿长度方向相对的一对壁部分别埋入有端子构件6。与该端子构件6对应地，在环状壁部50的上缘部形成有朝向水平方向外侧突出的板状的突出片52。
端子构件6例如通过将金属制的板状体弯折而形成。端子构件6具有在台阶部51的上表面暴露的内侧端子部60和在突出片52的上表面暴露的外侧端子部61。位于图1的纸面左侧的端子构件6以一个内侧端子部60和两个外侧端子部61在环状壁部50内电连接的方式一体地形成。另外，位于图1的纸面右侧的端子构件6以一个内侧端子部60和一个外侧端子部61在环状壁部50内电连接的方式一体地形成。即，在图1的纸面右侧，电气独立的两个端子构件6在环状壁部50的宽度方向上排列配置。
各半导体元件4、电路图案31以及端子构件6利用布线构件(金属线)电连接。具体而言，半导体元件4和电路图案34利用布线构件W1电连接。
另外，在图1的纸面左侧，隔着电路图案35相对的一对半导体元件4利用布线构件W2电连接。同样地，在图1的纸面右侧，隔着电路图案36相对的一对半导体元件4利用布线构件W2电连接。
在图1的纸面左侧，内侧端子部60与供半导体元件4安装的电路图案33利用布线构件W3电连接。同样地，在图1的纸面右侧，一个内侧端子部60与供半导体元件4安装的电路图案33利用布线构件W3电连接。另外，在图1的纸面右侧，电路图案35与另一个内侧端子部60利用布线构件W3电连接。
图1的纸面左侧的电路图案33与纸面右侧的电路图案36利用布线构件W4电连接。同样地，图1的纸面左侧的电路图案35与纸面右侧的电路图案35利用布线构件W4电连接。
另外，在图1的纸面左侧，电路图案35与半导体元件4利用布线构件W5电连接。同样地，在图1的纸面右侧，电路图案36与半导体元件4利用布线构件W5电连接。
另外，在电路图案35，沿着延伸方向配置有多个布线构件W6，详细情况之后叙述。布线构件W6在俯视时在电路图案35的宽度方向(与延伸方向正交的方向)上排列地配置有多根(图1中为两根)。另外，各布线构件W6在多个部位与电路图案35电连接。
上述的布线构件W1～W6使用具有导电性的线状的金属线。金属线可以是截面呈圆形且直径为25μm以上且600μm以下。导电金属线的材质能够使用金、铜、铝、金合金、铜合金、铝合金中的任一者或它们的组合。布线构件W1～W6可以与各个电路图案及半导体元件以楔形键合(日文：ウェッジボンディング)的方式接合。
在电路图案35上沿着延伸方向配置的布线构件W6可以是具有直径为100μm以上且600μm以下的截面圆形的线状的金属线。另外，作为布线构件W6，还能够使用金属线以外的构件。例如，作为布线构件W6，能够使用具有导电性的薄带状的带。带的宽度为500μm以上且2.5mm以下。带的厚度为50μm以上且250μm以下。这样的布线构件W6的材质能够使用铜、铝、铜合金、铝合金中的任一者或它们的组合。而且，为了调整电阻，还可以添加硅、铁、钨、钛中的任一者或它们的组合。这样的布线构件W6使用楔形键合、激光接合在多个部位与电路图案35连接。
壳体构件5的由环状壁部50规定的内部空间被密封树脂密封，图中未特别示出。具体而言，密封树脂被填充到在壳体构件5的内侧将绝缘电路基板3、半导体元件4、布线构件以及内侧端子部60充分埋入的程度。此外，密封树脂能够使用环氧树脂、硅凝胶。
然而，如上所述，近年来，对将IGBT元件的功能和FWD元件的功能一体化而成的RC－IGBT元件进行开发。根据RC－IGBT元件，相比于通过将IGBT元件和FWD元件组合为一对而构成单一的开关元件的情况，相同的额定电流的芯片面积缩小，能够进行更高密度的安装。
更具体而言，相比于以单体组合IGBT元件和FWD元件的情况，RC－IGBT元件能够使相同的额定电流的芯片面积缩小约20％。因而，具有能够缩小半导体组件的产品尺寸并获得与以往相同的额定电流的优点。
即，若使用与以单体组合IGBT元件和FWD元件的芯片面积相同的面积的RC－IGBT元件，则能够使额定电流进一步扩大(约25％)。该情况下，能够在半导体组件的产品尺寸与以往相同的状态下扩大额定电流。
然而，与以往相比，额定电流被扩大，其结果，电路网的发热量与电流的平方呈比例地增加，因而，可能发生在以往的额定电流的情况下不成为问题的电路图案的异常过热。这被认为是由于流过电路图案的电流产生了位置上的偏移。
在此，参照图3说明本实施方式的半导体组件1的电路构造。图3是本实施方式的半导体组件的电路构造的局部放大图。更具体而言，图3A是图1的电路图案35周边的局部放大图，图3B是图2的电路图案35周边的局部放大图。
如图3A所示，电路图案35具有沿规定方向延伸的第1直部35a、向与第1直部35a的延伸方向不同的方向弯曲的角部35b以及沿角部35b的弯曲方向延伸的第2直部35c。
第1直部35a例如沿着半导体组件1的长度方向(图3的纸面左右方向)延伸。角部35b自第1直部35a的端部呈直角弯曲。第2直部35c自角部35b的端部例如沿半导体组件1的宽度方向(图3的纸面上下方向)延伸。即，第1直部35a和第2直部35c在角部35b以形成直角的方式连结。
通常，电路图案31(35)使用铜等导电性较高的金属材料，具有规定的电阻。特别是如图3A所示，在电路图案35具有角部35b的情况下，在电路图案35中流动的电流具有在电阻更低的部位流动的倾向。即，电流要流过电路图案35中的电阻减小的路径。更具体而言，电流要流过电路图案35(角部35b)的内周侧(参照图3A中的箭头)。该情况下，与电路图案35的内周侧相比，电流难以在电路图案35的外周侧流动。如此，可以说，在电路图案35中流动的电流因路径不同而产生了偏差。
于是，本申请发明人着眼于上述那样在电路图案中流动的电流产生位置上的偏移的情况，想到了本发明。具体而言，在本实施方式中，在第1直部35a的上表面沿着第1直部35a的延伸方向配置有多个(例如3个)布线构件W6。另外，多个布线构件W6偏向角部35b的外周侧地配置。
根据该结构，使布线构件W6偏向电路图案35的外周侧地配置，从而能够降低电路图案35的外周侧的电阻。其结果，能够使电流也容易在电路图案35的外周侧流动。更具体而言，电流不仅在电路图案35的内周侧流动，还在包含布线构件W6的电路图案35的外周侧流动。
如此，通过使在电路图案35中流动的电流分流化，能够抑制在电路图案35中流动的电流的位置上的偏移。其结果，使电路图案35中的电流密度降低，电流容易在电路图案35整体中流动。因此，电路图案35的热分布变得均匀，能够防止局部的异常过热。
这样的异常过热防止效果在包括将IGBT元件的功能和FWD元件的功能一体化而成的RC－IGBT元件的半导体组件1中表现得更加显著。因而，根据本实施方式，能够扩大额定电流并且抑制电路图案的异常过热。
接着，参照图4至图8说明变形例的半导体组件的电路构造。图4是表示第1变形例的半导体组件的电路构造的示意图。图5是表示第2变形例的半导体组件的电路构造的示意图。图6是表示第3变形例的半导体组件的电路构造的示意图。图7是表示第4变形例的半导体组件的电路构造的示意图。图8是表示第5变形例的半导体组件的电路构造的示意图。
在上述实施方式中，设为布线构件W6配置于第1直部35a的上表面的结构，但并不限定于该结构。例如，还可以是图4所示的结构。如图4所示，布线构件W6也可以配置于角部35b的上表面。布线构件W6以沿着角部35b的弯曲方向形成俯视字母L状的方式配置。另外，布线构件W6在电路图案35的宽度方向上排列设置有两个。此外，两个布线构件W6偏向角部35b的外周侧地配置。这样的布线结构也能够与上述相同地降低电路图案35的外周侧的电阻。能够防止局部的异常过热。
另外，还能够组合图3和图4的布线图案，如图5所示地在电路图案35的外周侧配置布线构件W6。由此，电路图案35的热分布变得均匀而能够得到进一步抑制异常过热的效果。
另外，如图6所示，布线构件W6相对于电路图案35连接的连接部位W6a的个数可以随着朝向电路图案35的宽度方向外周侧去而增多。例如，对于布线构件W6的连接部位W6a之间的间隔，可以是，在将最内周侧的布线构件W6设为1时，最外周侧的布线构件W6为0.5，它们之间的布线构件W6在大于1且小于0.5的范围内随着朝向外周侧去而依次减小。电路图案35的外周侧的连接部位W6a越增多，则越能够降低电路图案35的外周侧的电阻，因此，电路图案35的热分布变得均匀而能够得到进一步抑制异常过热的效果。另外，在上述实施方式中，说明了布线构件W6形成于电路图案35的直部35a的情况，但并不限定于此，在图4的形成于角部35b以及图5的形成于外周侧的情况下，能够适当变更。
另外，未特别图示，但也可以是，在图3的形成于电路图案35的直部35a、图4的形成于角部35b以及图5的形成于外周侧的布线构件W6中，在电路图案35的宽度方向上排列配置的多个布线构件W6的越靠外周侧的布线构件的材质的导电率越高。例如，内周侧可以为铝或铝合金，外周侧可以为铜或铜合金。此外，多个布线构件W6的线径的越靠外周侧的布线构件的线径越大。例如，可以是，多个布线构件W6为金属线，内周侧的直径为100μm以上且小于300μm，外周侧的直径为300μm以上且500um以下。如此，能够适当变更随着朝向外周侧去而降低电路图案35的电阻的结构。即，通过在随着朝向外周侧去而电阻下降的方面对度(日文：軽重)进行设置，能够更灵活地抑制异常过热。
另外，在上述实施方式中，说明了电路图案35形成为俯视字母L状的情况，但电路图案35的形状并不限定于此，能够适当变更。例如，如图7和图8所示，也可以由俯视形成为曲柄状的电路图案37构成。
具体而言，电路图案37具有沿规定方向(图7和图8中为纸面上下方向)延伸的第1直部37a以及自第1直部37a的两端向与第1直部37a的延伸方向不同的方向(直角方向)弯曲的第1角部37b和第2角部37c。第1角部37b和第2角部37c以朝向彼此相反的一侧的方式弯曲。
在图7中，在第1角部37b的上表面配置有两个布线构件W7。布线构件W7以沿着第1角部37b的弯曲方向形成俯视字母L状的方式配置。另外，布线构件W7在电路图案37的宽度方向上排列设置有两个。而且，两个布线构件W7偏向第1角部37b的外周侧地配置。另外，布线构件W7的相对于电路图案37的连接部位W7a各设有4处。
同样，在第2角部37c的上表面也配置有两个布线构件W7。布线构件W7以沿着第2角部37c的弯曲方向形成俯视字母L状的方式配置。另外，布线构件W7在电路图案37的宽度方向上排列设置有两个。而且，两个布线构件W7偏向第2角部37c的外周侧地配置。另外，布线构件W7的相对于电路图案37的连接部位W7a各设有4处。
在图8中，在第1直部37a的上表面配置有布线构件W7。具体而言，两个布线构件W7偏向第1角部37b的外周侧地沿着第1直部37a的延伸方向配置于第1直部37a的靠近第1角部37b侧的位置。两个布线构件W7在第1直部37a的宽度方向上排列配置。
另外，两个布线构件W7偏向第2角部37c的外周侧地沿着第1直部37a的延伸方向配置于第1直部37a的靠近第2角部37c侧的位置。两个布线构件W7在第1直部37a的宽度方向上排列配置。
如图7和图8所示，在曲柄形状的电路图案37中，通过在预想为电流不易流动的部位设置布线构件W7，能够使电流容易在电路图案37整体中流动。因此，电路图案37的热分布变得均匀，能够防止局部的异常过热。
如以上说明那样，根据本发明，通过在电路图案中成为电流难以流动的部位配置布线构件，能够扩大额定电流并且抑制电路图案的异常过热。
另外，在上述实施方式中，绝缘电路基板3、半导体元件4的个数和配置部位并不限定于上述结构，能够适当变更。布线构件的配置个数、布线构件的相对于电路图案的连接部位的个数也同样能够适当变更。
另外，在上述实施方式中，电路图案的个数和布局并不限定于上述结构，能够适当变更。
另外，在上述实施方式中，设为绝缘电路基板3、半导体元件4形成为俯视矩形形状或方形形状的结构，但并不限定于该结构。绝缘电路基板3、半导体元件4也可以形成为上述以外的多边形形状。
另外，说明了本实施方式和变形例，但作为其他的实施方式，还可以整体或局部地组合上述实施方式和变形例。
另外，本实施方式并不限定于上述的实施方式和变形例，也可以在不偏离技术思想的主旨的范围内以各种方式进行变更、置换、变形。此外，若通过技术上的进步或派生的其他技术能够以其他的方式实现技术思想，则也可以使用该方法来实施。因而，权利要求书涵盖可包含在技术思想的范围内的全部实施方式。
以下，整理上述实施方式的特征点。
上述实施方式所记载的半导体组件的电路构造的特征在于，该半导体组件的电路构造包括：绝缘电路基板，其在绝缘板的上表面形成电路图案而成；以及半导体元件，其配置于所述电路图案的上表面，所述电路图案具有：直部，其沿规定方向延伸；以及角部，其向与所述直部的延伸方向不同的方向弯曲，在所述直部的上表面配置有布线构件，该布线构件偏向所述角部的外周侧地沿着所述直部的延伸方向配置。
另外，上述实施方式中记载的另一半导体组件的电路构造的特征在于，该半导体组件的电路构造包括：绝缘电路基板，其在绝缘板的上表面形成电路图案而成；以及半导体元件，其配置于所述电路图案的上表面，所述电路图案具有：直部，其沿规定方向延伸；以及角部，其向与所述直部的延伸方向不同的方向弯曲，在所述角部的上表面配置有布线构件，该布线构件偏向外周侧地沿着弯曲方向配置。
另外，在上述实施方式记载的另一半导体组件的电路构造中，其特征在于，所述布线构件还以偏向外周侧地沿着弯曲方向的方式配置于所述角部的上表面。
另外，在上述实施方式记载的半导体组件的电路构造中，其特征在于，所述布线构件在多个部位与所述电路图案连接。
另外，在上述实施方式记载的半导体组件的电路构造中，其特征在于，所述布线构件在所述电路图案的宽度方向上排列配置有多个。
另外，在上述实施方式记载的半导体组件的电路构造中，其特征在于，所述布线构件的相对于所述电路图案的连接部位的个数随着朝向所述电路图案的宽度方向外周侧去而增多。
另外，在上述实施方式记载的半导体组件的电路构造中，其特征在于，在所述电路图案的宽度方向上排列配置的多个所述布线构件的越靠外周侧的所述布线构件的材质的导电率越高。
另外，在上述实施方式记载的半导体组件的电路构造中，其特征在于，在所述电路图案的宽度方向上排列配置的多个所述布线构件的越靠外周侧的所述布线构件的线径越大。
另外，在上述实施方式记载的半导体组件的电路构造中，其特征在于，所述半导体元件为将IGBT元件和FWD元件的功能一体化而成的RC－IGBT元件。
产业上的可利用性
如以上说明那样，本发明具有能够扩大额定电流并且还能够抑制电路图案的异常过热的效果，特别是对于半导体组件的电路构造是有用的。
本申请基于2019年7月3日申请的日本特愿2019－124452。其内容全部包含在本说明书中。

Claims (9)

1.一种半导体组件的电路构造，其特征在于，
该半导体组件的电路构造包括：
绝缘电路基板，其在绝缘板的上表面形成电路图案而成；以及
半导体元件，其配置于所述电路图案的上表面，
所述电路图案具有：
直部，其沿规定方向延伸；以及
角部，其向与所述直部的延伸方向不同的方向弯曲，
在所述直部的上表面配置有布线构件，该布线构件偏向所述角部的外周侧地沿着所述直部的延伸方向配置。
2.一种半导体组件的电路构造，其特征在于，
该半导体组件的电路构造包括：
绝缘电路基板，其在绝缘板的上表面形成电路图案而成；以及
半导体元件，其配置于所述电路图案的上表面，
所述电路图案具有：
直部，其沿规定方向延伸；以及
角部，其向与所述直部的延伸方向不同的方向弯曲，
在所述角部的上表面配置有布线构件，该布线构件偏向外周侧地沿着弯曲方向配置。
3.根据权利要求1所述的半导体组件的电路构造，其特征在于，
所述布线构件还以偏向外周侧地沿着弯曲方向的方式配置于所述角部的上表面。
4.根据权利要求1～3中任一项所述的半导体组件的电路构造，其特征在于，
所述布线构件在多个部位与所述电路图案连接。
5.根据权利要求4所述的半导体组件的电路构造，其特征在于，
所述布线构件在所述电路图案的宽度方向上排列配置有多个。
6.根据权利要求5所述的半导体组件的电路构造，其特征在于，
所述布线构件的相对于所述电路图案的连接部位的个数随着朝向所述电路图案的宽度方向外周侧去而增多。
7.根据权利要求5或6所述的半导体组件的电路构造，其特征在于，
在所述电路图案的宽度方向上排列配置的多个所述布线构件的越靠外周侧的所述布线构件的材质的导电率越高。
8.根据权利要求5～7中任一项所述的半导体组件的电路构造，其特征在于，
在所述电路图案的宽度方向上排列配置的多个所述布线构件的越靠外周侧的所述布线构件的线径越大。
9.根据权利要求1～8中任一项所述的半导体组件的电路构造，其特征在于，
所述半导体元件为将IGBT元件和FWD元件的功能一体化而成的RC－IGBT元件。
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Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629646A (ja) * 1992-07-09 1994-02-04 Shinko Electric Co Ltd ハイブリッド集積回路
JP2000277872A (ja) * 1999-03-24 2000-10-06 Kyocera Corp 配線基板
JP2001085611A (ja) * 1999-09-10 2001-03-30 Mitsubishi Electric Corp パワーモジュール
EP1739740A2 (en) * 2005-06-30 2007-01-03 Hitachi, Ltd. Power semiconductor
US20080054491A1 (en) * 2006-09-06 2008-03-06 Kabushiki Kaisha Toshiba Semiconductor device, relay chip, and method for producing relay chip
KR20080096483A (ko) * 2007-04-27 2008-10-30 가부시끼가이샤 르네사스 테크놀로지 반도체 장치
CN101334679A (zh) * 2007-06-06 2008-12-31 通用汽车环球科技运作公司 用于动力电子装置的温度感应装置
JP2010251551A (ja) * 2009-04-16 2010-11-04 Nichicon Corp 電子回路基板およびパワー半導体モジュール
CN102969306A (zh) * 2011-08-31 2013-03-13 株式会社日立制作所 电源模块及其制造方法
CN103021979A (zh) * 2011-09-21 2013-04-03 株式会社东芝 半导体装置
CN103247301A (zh) * 2012-02-03 2013-08-14 日东电工株式会社 布线电路基板及其制造方法以及连接端子
CN108321129A (zh) * 2018-03-30 2018-07-24 深圳赛意法微电子有限公司 功率器件的封装方法及其封装模块、引线框架

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2013211B (en) 1978-01-26 1982-06-30 Technicon Instr Immunoassays using f(ab')2 fragments
JPS6029646B2 (ja) 1981-01-20 1985-07-11 堺化学工業株式会社 磁性酸化鉄粉末の製造方法
JP2846792B2 (ja) 1993-05-28 1999-01-13 三洋電機株式会社 混成集積回路装置
DE102010030317B4 (de) 2010-06-21 2016-09-01 Infineon Technologies Ag Schaltungsanordnung mit Shuntwiderstand
US11073313B2 (en) 2018-01-11 2021-07-27 Carrier Corporation Method of managing compressor start for transport refrigeration system
JP2020021619A (ja) 2018-07-31 2020-02-06 株式会社Ｊｏｌｅｄ 発光装置および電子機器

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629646A (ja) * 1992-07-09 1994-02-04 Shinko Electric Co Ltd ハイブリッド集積回路
JP2000277872A (ja) * 1999-03-24 2000-10-06 Kyocera Corp 配線基板
JP2001085611A (ja) * 1999-09-10 2001-03-30 Mitsubishi Electric Corp パワーモジュール
EP1739740A2 (en) * 2005-06-30 2007-01-03 Hitachi, Ltd. Power semiconductor
US20080054491A1 (en) * 2006-09-06 2008-03-06 Kabushiki Kaisha Toshiba Semiconductor device, relay chip, and method for producing relay chip
KR20080096483A (ko) * 2007-04-27 2008-10-30 가부시끼가이샤 르네사스 테크놀로지 반도체 장치
CN101334679A (zh) * 2007-06-06 2008-12-31 通用汽车环球科技运作公司 用于动力电子装置的温度感应装置
JP2010251551A (ja) * 2009-04-16 2010-11-04 Nichicon Corp 電子回路基板およびパワー半導体モジュール
CN102969306A (zh) * 2011-08-31 2013-03-13 株式会社日立制作所 电源模块及其制造方法
CN103021979A (zh) * 2011-09-21 2013-04-03 株式会社东芝 半导体装置
CN103247301A (zh) * 2012-02-03 2013-08-14 日东电工株式会社 布线电路基板及其制造方法以及连接端子
CN108321129A (zh) * 2018-03-30 2018-07-24 深圳赛意法微电子有限公司 功率器件的封装方法及其封装模块、引线框架

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US20210327781A1 (en) 2021-10-21
JP7136355B2 (ja) 2022-09-13

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