US20150099368A1 - Dry etching method - Google Patents

Dry etching method Download PDF

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Publication number
US20150099368A1
US20150099368A1 US14/447,681 US201414447681A US2015099368A1 US 20150099368 A1 US20150099368 A1 US 20150099368A1 US 201414447681 A US201414447681 A US 201414447681A US 2015099368 A1 US2015099368 A1 US 2015099368A1
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US
United States
Prior art keywords
etching
gas
layers
sige
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/447,681
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English (en)
Inventor
Ze SHEN
Tetsuo Ono
Hisao YASUNAMI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi High Tech Corp
Original Assignee
Hitachi High Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi High Technologies Corp filed Critical Hitachi High Technologies Corp
Assigned to HITACHI HIGH-TECHNOLOGIES CORPORATION reassignment HITACHI HIGH-TECHNOLOGIES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ONO, TETSUO, YASUNAMI, HISAO, SHEN, Ze
Publication of US20150099368A1 publication Critical patent/US20150099368A1/en
Priority to US15/196,284 priority Critical patent/US11018014B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H01J37/32201—Generating means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas

Definitions

  • SiGe silicon-germanium
  • FIG. 3A As semiconductor device structure employing such SiGe there is known laminated structure with Si layers and SiGe layers as shown in FIG. 3A , which is expected to be applied for semiconductor devices in the 22 nm generation and thereafter. In this laminated structure with Si layers and SiGe layers it is required to isotropically etch each of the SiGe layers selectively relative to each of the Si layers.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)
US14/447,681 2013-10-08 2014-07-31 Dry etching method Abandoned US20150099368A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/196,284 US11018014B2 (en) 2013-10-08 2016-06-29 Dry etching method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-210656 2013-10-08
JP2013210656A JP6138653B2 (ja) 2013-10-08 2013-10-08 ドライエッチング方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/196,284 Division US11018014B2 (en) 2013-10-08 2016-06-29 Dry etching method

Publications (1)

Publication Number Publication Date
US20150099368A1 true US20150099368A1 (en) 2015-04-09

Family

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Family Applications (2)

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US14/447,681 Abandoned US20150099368A1 (en) 2013-10-08 2014-07-31 Dry etching method
US15/196,284 Active US11018014B2 (en) 2013-10-08 2016-06-29 Dry etching method

Family Applications After (1)

Application Number Title Priority Date Filing Date
US15/196,284 Active US11018014B2 (en) 2013-10-08 2016-06-29 Dry etching method

Country Status (4)

Country Link
US (2) US20150099368A1 (zh)
JP (1) JP6138653B2 (zh)
KR (2) KR20150041567A (zh)
TW (1) TWI667707B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170330934A1 (en) * 2016-05-16 2017-11-16 Globalfoundries Inc. Devices and methods of forming self-aligned, uniform nano sheet spacers
CN110021524A (zh) * 2017-12-27 2019-07-16 东京毅力科创株式会社 蚀刻方法
US10600889B2 (en) * 2017-12-22 2020-03-24 International Business Machines Corporation Nanosheet transistors with thin inner spacers and tight pitch gate
US10892158B2 (en) 2019-04-01 2021-01-12 Hitachi High-Tech Corporation Manufacturing method of a semiconductor device and a plasma processing apparatus
WO2021216283A1 (en) * 2020-04-21 2021-10-28 Praxair Technology, Inc. Novel methods for gas phase selective etching of silicon-germanium layers
WO2022039848A1 (en) * 2020-08-18 2022-02-24 Applied Materials, Inc. Methods for etching structures with oxygen pulsing
WO2022039849A1 (en) * 2020-08-18 2022-02-24 Applied Materials, Inc. Methods for etching structures and smoothing sidewalls
WO2022173633A1 (en) * 2021-02-09 2022-08-18 Tokyo Electron Limited Plasma etching techniques

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6516542B2 (ja) * 2015-04-20 2019-05-22 東京エレクトロン株式会社 被エッチング層をエッチングする方法
JP6619703B2 (ja) * 2016-06-28 2019-12-11 株式会社Ｓｃｒｅｅｎホールディングス エッチング方法
US10043674B1 (en) * 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
JP7145740B2 (ja) * 2018-01-22 2022-10-03 東京エレクトロン株式会社 エッチング方法
CN110071040B (zh) 2018-01-22 2024-04-09 东京毅力科创株式会社 蚀刻方法
KR102258361B1 (ko) * 2019-09-10 2021-05-28 포항공과대학교 산학협력단 펄스형 전력을 사용한 플라즈마 활성종 생성방법
JP7345334B2 (ja) * 2019-09-18 2023-09-15 東京エレクトロン株式会社 エッチング方法及び基板処理システム
CN114616650A (zh) * 2019-10-29 2022-06-10 东京毅力科创株式会社 基板处理方法、基板处理装置和纳米线或纳米片的晶体管的制造方法
WO2021181613A1 (ja) * 2020-03-12 2021-09-16 株式会社日立ハイテク プラズマ処理方法
CN115707347A (zh) 2021-06-17 2023-02-17 株式会社日立高新技术 等离子体处理方法及半导体装置的制造方法
US20230360921A1 (en) * 2022-05-09 2023-11-09 Tokyo Electron Limited Selective and isotropic etch of silicon over silicon-germanium alloys and dielectrics; via new chemistry and surface modification
JP2024083014A (ja) * 2022-12-09 2024-06-20 東京エレクトロン株式会社 基板処理方法及び基板処理装置

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US20080073635A1 (en) * 2006-09-21 2008-03-27 Masahiro Kiyotoshi Semiconductor Memory and Method of Manufacturing the Same
US20090008705A1 (en) * 2007-07-05 2009-01-08 International Business Machines Corporation Body-contacted finfet
US20130119018A1 (en) * 2011-11-15 2013-05-16 Keren Jacobs Kanarik Hybrid pulsing plasma processing systems
US20130153970A1 (en) * 2011-12-20 2013-06-20 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Transistor structure, method for manufacturing a transistor structure, force-measuring system
US20130241028A1 (en) * 2012-03-16 2013-09-19 Semiconductor Manufacturing International Corp. Silicon-on-insulator substrate and fabrication method

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JP2654003B2 (ja) * 1986-06-30 1997-09-17 株式会社東芝 ドライエツチング方法
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US7317434B2 (en) * 2004-12-03 2008-01-08 Dupont Displays, Inc. Circuits including switches for electronic devices and methods of using the electronic devices
JP4738194B2 (ja) * 2006-02-09 2011-08-03 芝浦メカトロニクス株式会社 エッチング方法及び半導体装置の製造方法
US20090068844A1 (en) * 2006-04-10 2009-03-12 Solvay Fluor Gmbh Etching Process
US7863124B2 (en) * 2007-05-10 2011-01-04 International Business Machines Corporation Residue free patterned layer formation method applicable to CMOS structures
JP2012521078A (ja) * 2009-03-17 2012-09-10 アイメック プラズマテクスチャ方法
US10658161B2 (en) * 2010-10-15 2020-05-19 Applied Materials, Inc. Method and apparatus for reducing particle defects in plasma etch chambers
KR20120073727A (ko) 2010-12-27 2012-07-05 삼성전자주식회사 스트레인드 반도체 영역을 포함하는 반도체 소자와 그 제조방법, 및 그것을 포함하는 전자 시스템
JP5774428B2 (ja) * 2011-09-28 2015-09-09 株式会社日立ハイテクノロジーズ ドライエッチング方法およびプラズマエッチング装置
TWI581304B (zh) 2011-07-27 2017-05-01 日立全球先端科技股份有限公司 Plasma etching apparatus and dry etching method
CN103531475A (zh) * 2012-07-03 2014-01-22 中国科学院微电子研究所 半导体器件及其制造方法

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
US20080073635A1 (en) * 2006-09-21 2008-03-27 Masahiro Kiyotoshi Semiconductor Memory and Method of Manufacturing the Same
US20090008705A1 (en) * 2007-07-05 2009-01-08 International Business Machines Corporation Body-contacted finfet
US20130119018A1 (en) * 2011-11-15 2013-05-16 Keren Jacobs Kanarik Hybrid pulsing plasma processing systems
US20130153970A1 (en) * 2011-12-20 2013-06-20 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Transistor structure, method for manufacturing a transistor structure, force-measuring system
US20130241028A1 (en) * 2012-03-16 2013-09-19 Semiconductor Manufacturing International Corp. Silicon-on-insulator substrate and fabrication method

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10388729B2 (en) * 2016-05-16 2019-08-20 Globalfoundries Inc. Devices and methods of forming self-aligned, uniform nano sheet spacers
US20170330934A1 (en) * 2016-05-16 2017-11-16 Globalfoundries Inc. Devices and methods of forming self-aligned, uniform nano sheet spacers
US11329143B2 (en) 2017-12-22 2022-05-10 International Business Machines Corporation Nanosheet transistors with thin inner spacers and tight pitch gate
US10600889B2 (en) * 2017-12-22 2020-03-24 International Business Machines Corporation Nanosheet transistors with thin inner spacers and tight pitch gate
CN110021524A (zh) * 2017-12-27 2019-07-16 东京毅力科创株式会社 蚀刻方法
US10892158B2 (en) 2019-04-01 2021-01-12 Hitachi High-Tech Corporation Manufacturing method of a semiconductor device and a plasma processing apparatus
WO2021216283A1 (en) * 2020-04-21 2021-10-28 Praxair Technology, Inc. Novel methods for gas phase selective etching of silicon-germanium layers
WO2022039848A1 (en) * 2020-08-18 2022-02-24 Applied Materials, Inc. Methods for etching structures with oxygen pulsing
WO2022039849A1 (en) * 2020-08-18 2022-02-24 Applied Materials, Inc. Methods for etching structures and smoothing sidewalls
US11527414B2 (en) 2020-08-18 2022-12-13 Applied Materials, Inc. Methods for etching structures with oxygen pulsing
US11658042B2 (en) 2020-08-18 2023-05-23 Applied Materials, Inc. Methods for etching structures and smoothing sidewalls
WO2022173633A1 (en) * 2021-02-09 2022-08-18 Tokyo Electron Limited Plasma etching techniques
US11538690B2 (en) 2021-02-09 2022-12-27 Tokyo Electron Limited Plasma etching techniques

Also Published As

Publication number Publication date
KR101826642B1 (ko) 2018-02-07
US20160307765A1 (en) 2016-10-20
US11018014B2 (en) 2021-05-25
TW201515092A (zh) 2015-04-16
KR20150041567A (ko) 2015-04-16
JP2015076459A (ja) 2015-04-20
KR20160100287A (ko) 2016-08-23
TWI667707B (zh) 2019-08-01
JP6138653B2 (ja) 2017-05-31

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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHEN, ZE;ONO, TETSUO;YASUNAMI, HISAO;SIGNING DATES FROM 20140619 TO 20140620;REEL/FRAME:033430/0267

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION