M348426 八、新型說明： . 【新型所屬之技術領域】 本創作係有關一種電壓位準移位器，尤指利用一差動放大器、一拉升電晶 體、一反相器以及一拉降電晶體所組成，以求獲得精確電壓位準轉換之電子電 路0 【先前技術】 電壓位準移位器係一種用來溝通不同的積體電路(IntegratedCircuit，簡稱1C) 之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準 4較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電壓位準移位器就負責將 低電壓工作信號轉換成高電壓工作信號。 第1圖係顯示一先前技藝(priorart)之一閂鎖型電壓位準移位器電路，其係使 用一第一PMOS(P-channel metal oxide semiconductor，P通道金屬氧化物半導體） 電晶體(MP1)、.一第 一PMOS 電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor ’ N通道金屬氧化物半導體)電晶體(MN1)、一第二_〇8電晶體 (MN2)及一反相器(INV)來構成一電壓位準移位器電路，其中，該反相器(_) 的偏壓是第二高電位電壓(VDDL)及地(GND)，而輸入電壓(V(IN))的電位亦在地 (GND)與第二高電位電壓(VDDL)之間。輸入電壓(v(IN))及經過反相器(INV)輸出 .的反相輸入電壓信號分別連接至第一 NM〇S電晶體(MN1)及第二_〇8電晶體 _ (MN2)的閘極(gate)。因此，在同一時間内，第一麵〇s電晶體(丽!)及第二丽〇；§ -電晶體(MN2)之中只有一個會導通(on)。此外，由於第一pM〇s電晶體(撕丨)和 第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電壓位準移位器 的輸出(OUT)處於一個穩定的狀態時，問鎖型的電壓位準移位器中沒有靜態電流 (static current)產生。尤其，當第一nm〇s電晶體(MN1)關閉(OFF)而第二NMOS 電晶體(MN2)導通(〇N)a寺，第一 PMOS電晶體(MP1)的閘極電位被拉降(pUU down) 並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2) 的閘極電位而關閉第二PM〇S電晶體(MP2);再者，當第一NMOS電晶體(MN1) 導通而第二NMOS電晶體(MN2)關閉時，第二PMOS電晶體(MP2)的閘極電位被 拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘 5 M348426 極電位而關閉第一PMOS電晶體(MPl)。因此，在第一pm〇S電晶體(MP1)和第一 NM〇S電晶體(Mm)之間或第二pM〇s電晶體(Mp2)和第二_〇8電晶體(MN2) 之間就不會存在一個電流路徑。 然而，上述習知電壓位準移位器在第二pMOS電晶體(MP2)趨近於導通(或關 閉)與在第二NM〇S電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出節點 (OUT)上的電位之拉升及拉降有互相競爭(c〇ntenti〇n)的現象，因此輸出電壓信號 (V(〇UT))在轉變成低電位時速度較慢。此外，考慮當輸入電壓(V(IN))由0伏特改 變至L8伏特時，第一nm〇s電晶體(_丨)導通，而第二pM〇s電晶體(縱2)的閘 •極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電位 電壓(VDDH)。但是，由於〇伏特無法瞬間轉換至18伏特，因此，在轉換期間的 ί較低輸入電壓(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體 (MP2)、第一NM〇s電晶體(_1)及第二NMOS電晶體(MN2)達到完全導通或完 全關閉，如此會造成在第一高電位電壓(VDDH)與地(GND)之間存在一靜態電流 (staticcurrent) ’此靜態電流會增加功率的損耗。 再者’閂鎖型的電壓位準移位器的性能是受到第一高電位電壓(YQDH)的影 響，由於第一 PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為 第一咼電位電壓(VDDH)，而第一 NMOS電晶體(MN1)和第二NMOS電晶體 (MN2)的閘-源極電壓是第二高電位電壓(VDDL)。因此，限制了可以使閂鎖型電 壓位準移位器正常運作的第一高電位電壓(VDDH)的範圍。 I 第2圖係顯示另一先前技藝之一鏡像型電壓位準移位器電路，該電壓位準移 位器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一 起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二 PMOS電晶體(MP2)形成電流鏡電路，第一PM0S電晶體(MP1)是處於飽和區，並 且其閘極電壓使得飽和電流等於流入第電晶體(_〇之電流，而流經第 一 PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電 壓位準移位器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的 電流來決定，因此，即使輸出的第一高電位電壓(VDDH)改變，電壓位準移位器 的性能也不會有太大的改變。因此，鏡像型的電壓位準移位器可以適用在各種 輸出電壓電路。 然而，當第一NMOS電晶體(MN1)導通而第二_〇8電晶體(_2)關閉時， 6 M348426 第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一 PMOS電晶體(MP1)和第一PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶 體(MP 1)和第一 NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 有鑑於此，本創作之主要目的係提出一種新穎架構之電壓位準移位器，其 不但能精確且快速地將第一信號轉換為一第二信號，並且可較先前之電壓位準 移位器具有更低之功率消耗。 【新型内容】 ' 本創作提出一種新穎架構之電壓位準移位器，其係由一差動放大器(1)、一 拉升電晶體(2)、一反相器(3)以及一拉降電晶體(4)所組成，其中，該差動放大器 壽》(1)係做為比較器使用，且該差動放大器之兩輸入端係分別接受輸入電壓信號 (V(IN))及輸出電壓回授信號(V(0UT))，並提供適當之充電電流給拉升電晶體 (2)，該拉升電晶體(2)係用以將輸出端(〇υτ)之電位拉升至第一高電位電壓 (VDDH);該反相器⑶係用來控制該拉降電晶體⑷之導通㈣或關閉(〇均；而該 拉降電晶體(4)係用來提供一放電路徑，以便將輸出端(〇υχ)之電位拉降至地 (GND)〇 由模擬結果證實，本創作所提出之電壓位準移位器，不但能精確且快速地 將第一信號轉換為一第二信號，並且兼具電路結構簡單、使用的電晶體數量較 少以及有利於裝置之小型化等多重功效，同時亦能有效地減少功率消耗。 【實施方式】 根據上述之目的，本創作提出一種電壓位準移位器，如第3圖所示，其係 由一差動放大器(1)、一拉升電晶體(2)、一反相器以及一拉降電晶體(句所組 成。該差動放大器(1)係由一第一 PM0S電晶體(MP1)、一第二pM〇s電晶體 (MP2)、一第一 NMOS電晶體(MN1)以及一第二NMOS電晶體(MN2)所組成， 其中，该第一 NMOS電晶體(MN1)和第二nm〇S電晶體(MN2)係做為驅動器 (driver)之用，該第一 PM0S電晶體(Μρι)係做為負載電晶體之用，且該負載電晶 體與拉升電晶體(2)構成一電流鏡(current mirror)。該第一 PMOS電晶體(MP1)之 源極連接至第一高電位電壓(VDDH)，閘極與汲極連接在一起，並連接至拉升電 晶體(2)之閘極；該第一 NM〇s電晶體(_丨)之源極與第二_〇§電晶體(_2) 7 M348426 之源極相連接並連接至地(GND) ’其閘極用以接受輸入電壓(v(in))信號，而其 汲極則與該拉升電晶體(2)之閘極以及該第一 PM〇s電晶體(MP1)之汲極相連 接；該第二PMOS電晶體(MP2)之源極連接至第一高電位電壓，閘極連 接至第二PMOS電晶體(MP3)的沒極、第三NMOS電晶體(MN3)的没極以及輸出 端(OUT)，而其汲極與第二NMOS電晶體(MN2)之汲極連接在一起；該第二 NM〇S電晶體(_2)之源極與第一 _08電晶體(_丨)之源極相連接並連接至 地(GND)，其閘極用以接受反相器(3)之輸出電壓信號，而其汲極連接至第二 PMOS電曰曰體(MP2)的沒極，該拉升電晶體⑺係由第三pM〇s電晶體(Mp3)所組 ‘成，其源極it接至第-高電位電壓(VDDH)，其閘極與第—PM〇s電晶體(刪)的 .閘極以及第一 NMOS電晶體(丽1)的汲極相連接，而其汲極則連接至第三麵〇s 電阳體(MN3)的汲極、第三PMOS電晶體(MP2)的閘極以輸出端(out);該拉降 電晶體(4)係由-第三NM〇S電晶體(MN3)組成，其源極連接至地(gnd)，沒極 連接至拉升電晶體(2)的汲極以及輸出端(〇υχ)，而其間極則連接至第二 (INB) ° ® 請再參閱第3圖，_考慮輸人電壓(V(IN))為低電位(G伏特)時，電壓位準 移位器的穩祕作情形：第-輸人端(IN)上的低電位使得第__麵〇§電晶體 (MN1)關閉，第- PMOS電晶體(MP1)至第一 nm〇s f晶體(MN1)之電流路^將 會因第一 NMOS電晶體(MN1)關閉而沒有電流流過，因此，在第三pM〇s電$ 體(MP3)上也不會有鏡像電流產生；而經過反相器(3)輸出的第二高電位電』 (VDDL)使得第三NM〇S電晶體_3)導通’由於第三刪〇 極接地_) ’其汲極連接到輸出端(_，因此，輸出端位被 至-低電位(〇伏特）。再考慮輸入電壓(v_為第二高電位電壓(a伏 壓位準移位H樣_作_ 輸人端㈣上_二高電位電壓(卿 得第- NMOS電晶體(画)導通，因此，在第一 PM〇s f晶體(Μρι)至第一 NM〇S電晶體(MN1)之電流路徑上將會有電流流過，使得在第三pM〇 (MP3)上會有鏡像電流產生；而經過反相器(3)輸出的低電位電壓使得第二^曰 電晶體(_2)和第三NM〇S電晶體_3)都關閉，因此，由第三 (廳)產生的鏡像電流將使得輸出端(〇υτ)被拉升至第—高電位電壓⑽阳;曰 綜上所述，輸入電壓(V(INM低電位(0伏特)時，輸^ M348426 (ν(ουτ))為第—高# 电1 立電壓(3.3伏特）。如此，電壓位準轉換的目的便實現。 【創作功效】 ⑴提出之龍鱗移位器，具有如下功效： (1)咼集積度及有利於裝 77 用了3個PMOS B教置之小型化：由於本創作所提出之電壓位準移位器僅使 構新穎、簡單電晶體、3個1^08電晶體以及1個反相器，因此不但電路架 而且借右二I使用的電晶體數量較少，並且因不需使用運算放大器，因 ⑺積度及有利於裝置之小型化等優點; 將第一$號轉換提出之電壓位準移位器經模擬結果註實，確實能精確地 ⑺低裤^耗：本^此也具有高精確度之優點； 降低差動放大器之雷'…電壓位準移位器經模擬結果驻實，確實能有效 電‘耗，因此可有效降低電壓辦移位器之功率損耗。 雖然本創作特別揭露並 圍。因 士可明瞭任姻轉以了fm實蝴’但軌減本技術之人 此，所有相關技術範疇内之改=纟未脫離本創作的精神與範 勒之改變都包括在本創作之中請專利範圍内。 M348426 【圖式簡單說明】 第1圖係顯示第一先前技藝中電壓位準移位器之電路圖； 第2圖係顯示第二先前技藝中電壓位準移位器之電路圖； 第3圖係顯示本創作較佳實施例之電壓位準移位器之電路圖； 第4圖係顯示本創作較佳實施例之輸入電壓信號及輸出電壓信號之暫態分析時 序圖。 【主要元件符號說明】 1 差動放大器 2 拉升電晶體 3 反相器 4 拉降電晶體 MP1 第一 PMOS電晶體 MP2 第二PMOS電晶體 MP3 第三PMOS電晶體 MP4 第四PMOS電晶體 MN1 第一 NMOS電晶體 MN2 第二NMOS電晶體 MN3 第三NMOS電晶體 MN4 第四NMOS電晶體 IN 第一輸入端 INB 第二輸入端 OUT 輸出端 V(IN) 輸入電壓 V(OUT) 輸出電壓 VDDH 第一高電位電壓 VDDL 第二高電位電壓M348426 VIII. New description: . [New technical field] This creation is related to a voltage level shifter, especially using a differential amplifier, a pull-up transistor, an inverter and a pull-down crystal. An electronic circuit that is configured to obtain accurate voltage level conversion. [Prior Art] A voltage level shifter is an electronic circuit for communicating signals between different integrated circuits (Integrated Circuits, 1C). In many applications, when an application system needs to transfer a signal from a core logic with a lower voltage level 4 to a peripheral device with a higher voltage level, the voltage level shifter is responsible for converting the low voltage operating signal to a high voltage. Working signal. Figure 1 shows a prior art latch-type voltage level shifter circuit using a first PMOS (P-channel metal oxide semiconductor) transistor (MP1). a first PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor 'N-channel metal oxide semiconductor) transistor (MN1), a second _8 transistor (MN2), and An inverter (INV) is used to form a voltage level shifter circuit, wherein the bias voltage of the inverter (_) is the second high potential voltage (VDDL) and the ground (GND), and the input voltage (V) The potential of (IN)) is also between ground (GND) and the second high potential voltage (VDDL). The input voltage (v(IN)) and the inverted input voltage signal output through the inverter (INV) are respectively connected to the first NM〇S transistor (MN1) and the second_〇8 transistor_MN2 Gate. Therefore, at the same time, only one of the first face 电s transistor (L!) and the second 〇; § - transistor (MN2) will be on. In addition, due to the cross-coupled manner of the first pM〇s transistor (tear) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level shifter is in a stable state In the state, there is no static current generated in the lock type voltage level shifter. In particular, when the first nm 〇s transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (〇N)a, the gate potential of the first PMOS transistor (MP1) is pulled down ( pUU down) and causing the first PMOS transistor (MP1) to be turned on, so as to pull up the gate potential of the second PMOS transistor (MP2) and turn off the second PM〇S transistor (MP2); When the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that The first PMOS transistor (MP1) is turned off by pulling up the gate 5 M348426 of the first PMOS transistor (MP1). Therefore, between the first pm〇S transistor (MP1) and the first NM〇S transistor (Mm) or between the second pM〇s transistor (Mp2) and the second _〇8 transistor (MN2) There will be no current path. However, the above-described conventional voltage level shifter approaches the process of approaching (or turning off) the second pMOS transistor (MP2) and approaching (or turning on) the second NM〇S transistor (MN2). In the case that the pull-up and pull-down of the potential on the output node (OUT) compete with each other (c〇ntenti〇n), the output voltage signal (V(〇UT)) is slower when it is converted to a low potential. . In addition, consider that when the input voltage (V(IN)) is changed from 0 volts to L8 volts, the first nm 〇s transistor (_丨) is turned on, and the second pM 〇s transistor (vertical 2) is gated. It becomes low, causing the second PMOS transistor (MP2) to be turned on. Therefore, the output is a first high potential voltage (VDDH). However, since volts cannot be instantaneously converted to 18 volts, the lower input voltage (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NM〇s transistor (_1) and the second NMOS transistor (MN2) are fully turned on or completely turned off, which causes a quiescent current between the first high potential voltage (VDDH) and ground (GND) ( Staticcurrent) 'This quiescent current increases power loss. Furthermore, the performance of the 'latch-type voltage level shifter is affected by the first high potential voltage (YQDH) due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The pole voltage is the first zeta potential voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) which can make the latch type voltage level shifter operate normally is limited. I Fig. 2 shows another mirror type voltage level shifter circuit of another prior art by using a first PMOS transistor (MP1) and a second PMOS transistor (MP2) The gates are connected together and connected to the drain of the first PMOS transistor (MP1) such that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) It is in the saturation region, and its gate voltage is such that the saturation current is equal to the current flowing into the transistor (_〇), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror type voltage level shifter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes The performance of the voltage level shifter does not change much. Therefore, the mirror type voltage level shifter can be applied to various output voltage circuits. However, when the first NMOS transistor (MN1) is turned on, When the second _8 transistor (_2) is turned off, 6 M348426 first PMOS transistor (MP1) and second PMOS transistor The gate potential of the body (MP2) is pulled down, so that both the first PMOS transistor (MP1) and the first PMOS transistor (MP2) are turned on. Thus, in the first PMOS transistor (MP 1) and the first NMOS battery A quiescent current path is generated between the crystals (MN1). In view of this, the main purpose of this creation is to propose a novel architecture voltage level shifter that not only accurately and quickly converts the first signal into a first Two signals, and can have lower power consumption than the previous voltage level shifter. [New content] 'This creation proposes a novel architecture voltage level shifter, which is a differential amplifier (1) , a pull-up transistor (2), an inverter (3) and a pull-down transistor (4), wherein the differential amplifier life (1) is used as a comparator, and the difference The two input terminals of the dynamic amplifier respectively receive an input voltage signal (V(IN)) and an output voltage feedback signal (V(0UT)), and provide an appropriate charging current to the pull-up transistor (2), which pulls up the power The crystal (2) is used to pull the potential of the output terminal (〇υτ) to the first high potential voltage (VDDH); the inverter (3) is used To control the conduction (4) or turn off (〇) of the pull-down transistor (4); and the pull-down transistor (4) is used to provide a discharge path to pull the potential of the output (〇υχ) to ground (GND It is confirmed by the simulation results that the voltage level shifter proposed by the present invention can not only accurately and quickly convert the first signal into a second signal, but also has a simple circuit structure and a small number of transistors used. It also contributes to multiple functions such as miniaturization of the device, and also effectively reduces power consumption. [Embodiment] According to the above object, the present invention proposes a voltage level shifter, as shown in Fig. 3, which is composed of a differential amplifier (1), a pull-up transistor (2), and an inversion. And a pull-down transistor (sentence of the sentence. The differential amplifier (1) is composed of a first PMOS transistor (MP1), a second pM 〇s transistor (MP2), and a first NMOS transistor ( MN1) and a second NMOS transistor (MN2), wherein the first NMOS transistor (MN1) and the second nm 〇S transistor (MN2) are used as a driver, the first The PM0S transistor (Μρι) is used as a load transistor, and the load transistor and the pull-up transistor (2) form a current mirror. The source connection of the first PMOS transistor (MP1) To the first high potential voltage (VDDH), the gate is connected to the drain and connected to the gate of the pull-up transistor (2); the source of the first NM〇s transistor (_丨) and the first The source of the diode (_2) 7 M348426 is connected and connected to ground (GND) 'the gate is used to receive the input voltage (v(in)) signal, and the drain is connected to the pull-up Gate of crystal (2) And connecting the drain of the first PM〇s transistor (MP1); the source of the second PMOS transistor (MP2) is connected to the first high potential voltage, and the gate is connected to the second PMOS transistor (MP3) a poleless pole, a third NMOS transistor (MN3) having a pole and an output (OUT), and a drain connected to a drain of the second NMOS transistor (MN2); the second NM〇S transistor The source of (_2) is connected to the source of the first _08 transistor (_丨) and connected to the ground (GND), and the gate is used to receive the output voltage signal of the inverter (3), and the 汲The pole is connected to the second pole of the second PMOS electric body (MP2), and the pull-up transistor (7) is formed by the third pM〇s transistor (Mp3), and the source is connected to the first high potential The voltage (VDDH) is connected to the gate of the first PM〇s transistor (deletion) and the drain of the first NMOS transistor (Li1), and the drain is connected to the third plane. s the drain of the electric anode (MN3), the gate of the third PMOS transistor (MP2) as the output terminal (out); the pull-down transistor (4) is the transistor of the third NM〇S transistor (MN3) Composition, the source is connected to the ground (gnd), and the pole is connected to the drain of the pull-up transistor (2) Output (〇υχ), while the pole is connected to the second (INB) ° ® Please refer to Figure 3, _ consider the input voltage (V (IN)) is low (G volts), the voltage level The stable operation of the shifter: the low potential on the first input terminal (IN) causes the first _ _ 〇 电 transistor (MN1) to be turned off, the first PMOS transistor (MP1) to the first nm 〇sf crystal The current path of (MN1) will be turned off by the first NMOS transistor (MN1) and no current will flow. Therefore, no mirror current will be generated on the third pM〇s body (MP3). The second high potential of the inverter (3) is output (VDDL) so that the third NM〇S transistor _3) is turned on 'because the third gate is grounded _) 'the drain is connected to the output (_, Therefore, the output terminal is turned to - low potential (〇 volts). Consider again the input voltage (v_ is the second high potential voltage (a volt-voltage level shift H-like _ _ input terminal (four) _ two high potential voltage (Qingde first - NMOS transistor (paint) is turned on, therefore , a current will flow in the current path of the first PM〇sf crystal (Μρι) to the first NM〇S transistor (MN1), so that a mirror current will be generated on the third pM〇(MP3); The low potential voltage outputted through the inverter (3) causes both the second transistor (_2) and the third NM〇S transistor _3) to be turned off, so that the mirror current generated by the third (office) will cause The output (〇υτ) is pulled up to the first-high potential voltage (10) yang; in summary, the input voltage (V (INM low potential (0 volts), the input ^ M348426 (ν (ουτ)) is the first - High #Electrical 1 vertical voltage (3.3 volts). Thus, the purpose of voltage level conversion is achieved. [Creation efficiency] (1) The proposed dragon scale shifter has the following effects: (1) 咼 accumulation degree and favorable for loading 77 Miniaturization with three PMOS B teachings: Since the voltage level shifter proposed in this creation only makes a novel, simple transistor, three 1^08 transistors, and one inverter, However, the circuit frame and the number of transistors used by the right second I are less, and because the operational amplifier is not needed, the advantages of (7) integration and miniaturization of the device are favored; The positioner is accurately impressed by the simulation result, and it can accurately (7) low pants consumption: this also has the advantage of high precision; reduce the differential amplifier's thunder'... voltage level shifter through the simulation results, indeed It can effectively reduce the power consumption, so it can effectively reduce the power loss of the voltage shifter. Although this creation is particularly exposed, it is clear that the marriage has changed to the fm real butterfly, but the person who reduced the technology, this Changes in the relevant technical areas = 纟 without the spirit of this creation and the changes of Fan Le are included in the scope of this creation. M348426 [Simple diagram of the diagram] Figure 1 shows the voltage level in the first prior art Circuit diagram of a quasi-shifter; FIG. 2 is a circuit diagram showing a voltage level shifter in a second prior art; FIG. 3 is a circuit diagram showing a voltage level shifter of the preferred embodiment of the present invention; Show this creation Transient analysis timing diagram of input voltage signal and output voltage signal of the embodiment. [Main component symbol description] 1 Differential amplifier 2 Pull-up transistor 3 Inverter 4 Pull-down transistor MP1 First PMOS transistor MP2 Second PMOS transistor MP3 third PMOS transistor MP4 fourth PMOS transistor MN1 first NMOS transistor MN2 second NMOS transistor MN3 third NMOS transistor MN4 fourth NMOS transistor IN first input terminal INB second input terminal OUT Output terminal V(IN) Input voltage V(OUT) Output voltage VDDH First high potential voltage VDDL Second high potential voltage