TWI819592B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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TWI819592B
TWI819592B TW111116754A TW111116754A TWI819592B TW I819592 B TWI819592 B TW I819592B TW 111116754 A TW111116754 A TW 111116754A TW 111116754 A TW111116754 A TW 111116754A TW I819592 B TWI819592 B TW I819592B
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metal oxide
oxide semiconductor
semiconductor layer
gate
layer
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TW202341448A (en
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楊謹嘉
陳文斌
陳祖偉
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友達光電股份有限公司
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Abstract

A semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor is disposed above the substrate and includes a first metal-oxide-semiconductor layer and a first gate. The second transistor is disposed above the substrate and includes a second metal-oxide-semiconductor layer, a second gate and a first insulating layer. The second metal-oxide-semiconductor layer and the first metal-oxide-semiconductor layer belong to the same layer, and an oxygen concentration of the first metal-oxide-semiconductor layer is lower than an oxygen concentration of the second metal-oxide-semiconductor layer. The first insulating layer encapsulates the second metal-oxide-semiconductor layer and is not located between the first metal-oxide-semiconductor layer and the first gate. A manufacturing method of a semiconductor device is also provided.

Description

半導體裝置及其製作方法Semiconductor device and manufacturing method thereof

本發明是有關於一種半導體裝置及其製作方法。The present invention relates to a semiconductor device and a manufacturing method thereof.

一般而言，電子裝置中都包含有許多的半導體元件。舉例來說，顯示裝置中常包含有許多薄膜電晶體，這些薄膜電晶體利用在基板上沉積各種不同的薄膜（例如半導體、金屬、介電層等）來形成。在顯示裝置中，薄膜電晶體可以設置於畫素結構中，也可設置於驅動電路中。Generally speaking, electronic devices contain many semiconductor components. For example, display devices often include many thin film transistors, which are formed by depositing various thin films (such as semiconductors, metals, dielectric layers, etc.) on a substrate. In the display device, the thin film transistor can be disposed in the pixel structure or in the driving circuit.

隨著顯示裝置的解析度增加，薄膜電晶體的尺寸不斷縮小。為了使小尺寸的薄膜電晶體能提供足夠大的電流，薄膜電晶體中的半導體層需要有高的載子遷移率（carrier mobility）。然而，具有高載子遷移率的薄膜電晶體通常伴隨有較大的漏電流（leakage），導致可靠度（reliability）不佳，因而不適合作為畫素結構中的開關元件。As the resolution of display devices increases, the size of thin film transistors continues to shrink. In order for a small-sized thin film transistor to provide a large enough current, the semiconductor layer in the thin film transistor needs to have high carrier mobility. However, thin film transistors with high carrier mobility are usually accompanied by large leakage, resulting in poor reliability, and are therefore not suitable as switching elements in pixel structures.

本發明提供一種半導體裝置，提供具有高載子遷移率的薄膜電晶體及高可靠度的薄膜電晶體。The present invention provides a semiconductor device, a thin film transistor with high carrier mobility and a high reliability thin film transistor.

本發明提供一種半導體裝置的製作方法，提供具有高載子遷移率的薄膜電晶體及高可靠度的薄膜電晶體。The present invention provides a method for manufacturing a semiconductor device, and provides a thin film transistor with high carrier mobility and a high reliability thin film transistor.

本發明的一個實施例提出一種半導體裝置，包括：基板；第一電晶體，設置於基板之上，且第一電晶體包括第一金屬氧化物半導體層以及重疊於第一金屬氧化物半導體層的第一閘極；以及第二電晶體，設置於基板之上，且第二電晶體包括第二金屬氧化物半導體層、重疊於第二金屬氧化物半導體層的第二閘極以及第一絕緣層，其中，第二金屬氧化物半導體層與第一金屬氧化物半導體層屬於相同膜層，且第一金屬氧化物半導體層的氧濃度低於第二金屬氧化物半導體層的氧濃度，第一絕緣層包覆第二金屬氧化物半導體，且不位於第一金屬氧化物半導體與第一閘極之間。One embodiment of the present invention provides a semiconductor device, including: a substrate; a first transistor disposed on the substrate, and the first transistor includes a first metal oxide semiconductor layer and a first metal oxide semiconductor layer overlapping the first metal oxide semiconductor layer. a first gate; and a second transistor disposed on the substrate, and the second transistor includes a second metal oxide semiconductor layer, a second gate overlapping the second metal oxide semiconductor layer, and a first insulating layer , wherein the second metal oxide semiconductor layer and the first metal oxide semiconductor layer belong to the same film layer, and the oxygen concentration of the first metal oxide semiconductor layer is lower than the oxygen concentration of the second metal oxide semiconductor layer, and the first insulation The layer covers the second metal oxide semiconductor and is not located between the first metal oxide semiconductor and the first gate.

本發明的一個實施例提出一種半導體裝置的製作方法，包括：形成第一金屬氧化物半導體層及第二金屬氧化物半導體層於基板之上，且第一金屬氧化物半導體層與第二金屬氧化物半導體層屬於相同膜層；形成第一絕緣層以包覆第二金屬氧化物半導體，且第一絕緣層不接觸第一金屬氧化物半導體；進行退火處理，以使第一金屬氧化物半導體的氧濃度低於第二金屬氧化物的氧濃度；以及形成第一閘極及第二閘極於基板之上，且第一閘極及第二閘極分別重疊第一金屬氧化物半導體層及第二金屬氧化物半導體層。One embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a first metal oxide semiconductor layer and a second metal oxide semiconductor layer on a substrate, and the first metal oxide semiconductor layer and the second metal oxide semiconductor layer. The physical semiconductor layer belongs to the same film layer; a first insulating layer is formed to cover the second metal oxide semiconductor, and the first insulating layer does not contact the first metal oxide semiconductor; an annealing treatment is performed to make the first metal oxide semiconductor The oxygen concentration is lower than the oxygen concentration of the second metal oxide; and the first gate and the second gate are formed on the substrate, and the first gate and the second gate respectively overlap the first metal oxide semiconductor layer and the second gate. Two metal oxide semiconductor layers.

圖1A至圖1H是依照本發明一實施例的半導體裝置10的製作方法的步驟流程的剖面示意圖。以下，配合圖1A至圖1H說明半導體裝置10的製作方法。1A to 1H are schematic cross-sectional views of the steps of a method of manufacturing a semiconductor device 10 according to an embodiment of the present invention. Hereinafter, the method of manufacturing the semiconductor device 10 will be described with reference to FIGS. 1A to 1H .

請參照圖1A，首先，提供基板110。舉例而言，基板110的材料可以包括玻璃、石英、有機聚合物、或是不透光/反射材料（例如：導電材料、金屬、晶圓、陶瓷或其他可適用的材料）或是其他可適用的材料。Referring to FIG. 1A , first, a substrate 110 is provided. For example, the material of the substrate 110 may include glass, quartz, organic polymers, or opaque/reflective materials (such as conductive materials, metals, wafers, ceramics, or other applicable materials) or other applicable materials. s material.

接著，形成緩衝層112於基板110上。形成緩衝層112的方法例如為物理氣相沉積法、化學氣相沉積法或其他合適的方法。緩衝層112可以為單層或多層絕緣層，且絕緣層可以包括氧化矽（SiOx）、氮化矽（SiNx）、氮氧化矽（oxynitrides，SiONx）或其他合適的材料或上述材料的堆疊層。Next, the buffer layer 112 is formed on the substrate 110 . The method of forming the buffer layer 112 is, for example, physical vapor deposition, chemical vapor deposition, or other suitable methods. The buffer layer 112 may be a single layer or a multi-layer insulating layer, and the insulating layer may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitrides (SiONx) or other suitable materials or stacked layers of the above materials.

接著，形成第一金屬氧化物半導體層121及第二金屬氧化物半導體層122於基板110及緩衝層112上。舉例而言，第一金屬氧化物半導體層121及第二金屬氧化物半導體層122的形成方法可以包括以下步驟：首先，在基板110及緩衝層112上形成毯覆的半導體材料層（未繪示）；接著，利用微影製程，在半導體材料層上形成圖案化光阻（未繪示）；繼之，利用圖案化光阻作為罩幕，來對半導體材料層進行濕式或乾式蝕刻製程，以形成第一金屬氧化物半導體層121及第二金屬氧化物半導體層122；之後，移除圖案化光阻。也就是說，第一金屬氧化物半導體層121及第二金屬氧化物半導體層122可以由同一膜層經圖案化而形成。Then, the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 are formed on the substrate 110 and the buffer layer 112 . For example, the method of forming the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 may include the following steps: first, forming a blanket semiconductor material layer (not shown) on the substrate 110 and the buffer layer 112 ); then, use a photolithography process to form a patterned photoresist (not shown) on the semiconductor material layer; then, use the patterned photoresist as a mask to perform a wet or dry etching process on the semiconductor material layer. To form the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122; after that, the patterned photoresist is removed. That is to say, the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 can be formed by patterning the same film layer.

第一金屬氧化物半導體層121及第二金屬氧化物半導體層122中可以包括相同的金屬元素，例如皆含有銦元素、鋅元素、鎢元素、錫元素、鎵元素中的至少一者。舉例而言，第一金屬氧化物半導體層121及第二金屬氧化物半導體層122的材質可以包括銦鋅氧化物（InZnO，IZO）、銦鎢氧化物（InWO，IWO）、銦鎢鋅氧化物（InWZnO，IWZO）、銦鋅錫氧化物（InZnSnO，IZTO）、銦鎵錫氧化物（InGaSnO，IGTO）或銦鎵鋅錫氧化物（InGaZnSnO，IGZTO），但本發明不以此為限。The first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 may include the same metal element, for example, both contain at least one of indium element, zinc element, tungsten element, tin element, and gallium element. For example, the materials of the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 may include indium zinc oxide (InZnO, IZO), indium tungsten oxide (InWO, IWO), indium tungsten zinc oxide (InWZnO, IWZO), indium zinc tin oxide (InZnSnO, IZTO), indium gallium tin oxide (InGaSnO, IGTO) or indium gallium zinc tin oxide (InGaZnSnO, IGZTO), but the present invention is not limited to this.

請參照圖1B，接著，形成第一絕緣層130於第二金屬氧化物半導體層122及緩衝層112上。第一絕緣層130可以完全包覆第二金屬氧化物半導體層122的頂面以及側面，且第一絕緣層130不接觸第一金屬氧化物半導體121。舉例而言，第一絕緣層130的形成方法可以包括以下步驟：首先，使用化學氣相沉積法或其他合適的方法，在第一金屬氧化物半導體層121、第二金屬氧化物半導體層122及緩衝層112上形成毯覆的絕緣材料層（未繪示）；接著，利用微影製程，在絕緣材料層上形成圖案化光阻（未繪示）；繼之，利用圖案化光阻作為罩幕，來對絕緣材料層進行濕式或乾式蝕刻製程，以形成第一絕緣層130；之後，移除圖案化光阻。第一絕緣層130可以包括能夠阻擋氧逸散或對金屬氧化物半導體層供氧的材質。舉例而言，在本實施例中，第一絕緣層130可以包括阻氧層或含氧絕緣層，例如氧化矽、氮氧化矽、氧化鉿、氧化鋁或其他合適的材料，但本發明不以此為限。Referring to FIG. 1B , next, a first insulating layer 130 is formed on the second metal oxide semiconductor layer 122 and the buffer layer 112 . The first insulating layer 130 may completely cover the top surface and side surfaces of the second metal oxide semiconductor layer 122 , and the first insulating layer 130 does not contact the first metal oxide semiconductor 121 . For example, the method of forming the first insulating layer 130 may include the following steps: first, using a chemical vapor deposition method or other suitable method, forming the first metal oxide semiconductor layer 121 , the second metal oxide semiconductor layer 122 and A blanket insulating material layer (not shown) is formed on the buffer layer 112; then, a photolithography process is used to form a patterned photoresist (not shown) on the insulating material layer; and then, the patterned photoresist is used as a mask. A wet or dry etching process is performed on the insulating material layer to form the first insulating layer 130; thereafter, the patterned photoresist is removed. The first insulating layer 130 may include a material that can block the escape of oxygen or provide oxygen to the metal oxide semiconductor layer. For example, in this embodiment, the first insulating layer 130 may include an oxygen barrier layer or an oxygen-containing insulating layer, such as silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide or other suitable materials. However, the present invention does not use This is the limit.

請參照圖1C，接著，進行退火處理（Annealing）TA。退火處理TA可以在介於200℃至500℃之間的溫度（例如280℃、350℃或420℃）下進行，且退火處理TA的時間可以介於30分鐘至180分鐘之間，但本發明不以此為限。由於第一絕緣層130包覆第二金屬氧化物半導體層122，在退火處理TA的過程中，第一絕緣層130能夠阻擋第二金屬氧化物半導體層122中的氧逸散，甚至能對第二金屬氧化物半導體層122供氧，因此，第一金屬氧化物半導體層121會比第二金屬氧化物半導體層122容易脫氧。換句話說，退火處理TA能夠使第一金屬氧化物半導體層121脫氧且轉變為第一金屬氧化物半導體層121’，而第一絕緣層130則在退火處理TA中阻擋第二金屬氧化物半導體層122中的氧逸散或對第二金屬氧化物半導體層122供氧，使得第一金屬氧化物半導體層121’的氧空缺（oxygen vacancy）濃度高於第二金屬氧化物半導體層122的氧空缺濃度。如此一來，在退火處理TA之後，第一金屬氧化物半導體層121’的氧濃度將低於第二金屬氧化物半導體層122的氧濃度，使得第一金屬氧化物半導體層121’的載子遷移率（carrier mobility）能夠大於第二金屬氧化物半導體層的122載子遷移率。Please refer to Figure 1C, and then perform annealing TA. The annealing treatment TA can be performed at a temperature between 200°C and 500°C (for example, 280°C, 350°C or 420°C), and the time for the annealing treatment TA can be between 30 minutes and 180 minutes. However, the present invention Not limited to this. Since the first insulating layer 130 covers the second metal oxide semiconductor layer 122, during the annealing process TA, the first insulating layer 130 can block the oxygen in the second metal oxide semiconductor layer 122 from escaping, and can even prevent the second metal oxide semiconductor layer 122 from escaping. The two metal oxide semiconductor layers 122 supply oxygen. Therefore, the first metal oxide semiconductor layer 121 is easier to deoxidize than the second metal oxide semiconductor layer 122 . In other words, the annealing process TA can deoxidize the first metal oxide semiconductor layer 121 and transform it into the first metal oxide semiconductor layer 121', while the first insulating layer 130 blocks the second metal oxide semiconductor layer during the annealing process TA. The oxygen in the layer 122 escapes or supplies oxygen to the second metal oxide semiconductor layer 122 , so that the oxygen vacancy concentration of the first metal oxide semiconductor layer 121 ′ is higher than that of the second metal oxide semiconductor layer 122 Vacancy concentration. In this way, after the annealing process TA, the oxygen concentration of the first metal oxide semiconductor layer 121' will be lower than the oxygen concentration of the second metal oxide semiconductor layer 122, so that the carriers of the first metal oxide semiconductor layer 121' The carrier mobility can be greater than the 122 carrier mobility of the second metal oxide semiconductor layer.

在一些實施例中，脫氧之後的第一金屬氧化物半導體層121’中還能夠局部形成結晶顆粒，使得第一金屬氧化物半導體層121’的結晶度高於第二金屬氧化物半導體層122的結晶度。在某些實施例中，上述的結晶顆粒可具有奈米等級的粒徑，例如小於1 nm的粒徑，換句話說，經歷退火處理TA後的第一金屬氧化物半導體層121’的結晶度實質上可以介於非晶（amorphous）與多晶（polycrystalline）之間。In some embodiments, crystalline particles can be locally formed in the first metal oxide semiconductor layer 121' after deoxidation, so that the crystallinity of the first metal oxide semiconductor layer 121' is higher than that of the second metal oxide semiconductor layer 122. Crystallinity. In some embodiments, the above-mentioned crystalline particles may have a nanometer-level particle size, for example, a particle size less than 1 nm. In other words, the crystallinity of the first metal oxide semiconductor layer 121' after undergoing the annealing treatment TA In essence, it can be between amorphous and polycrystalline.

請參照圖1D，接著，形成第二絕緣層140於基板110之上，且第二絕緣層140覆蓋第一金屬氧化物半導體層121’、第一絕緣層130及緩衝層112。第二絕緣層140可以使用化學氣相沉積法或其他合適的方法形成。第二絕緣層140的材質可以包括氧化矽、氮化矽、氮氧化矽、有機聚合物或上述材料的疊層，但本發明不以此為限。Referring to FIG. 1D, next, a second insulating layer 140 is formed on the substrate 110, and the second insulating layer 140 covers the first metal oxide semiconductor layer 121', the first insulating layer 130 and the buffer layer 112. The second insulating layer 140 may be formed using chemical vapor deposition or other suitable methods. The material of the second insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, organic polymer, or a stack of the above materials, but the invention is not limited thereto.

請參照圖1E，接著，分別形成第一閘極151及第二閘極152於第一金屬氧化物半導體層121’及第二金屬氧化物半導體層122之上。第一閘極151及第二閘極152的形成方法可以包括以下步驟。首先，在第二絕緣層140上形成閘金屬層（未繪示）。繼之，利用微影製程，在閘金屬層上形成圖案化光阻（未繪示）。接著，利用圖案化光阻作為罩幕，來對閘金屬層進行濕式或乾式蝕刻製程，以形成第一閘極151及第二閘極152。之後，移除圖案化光阻。換句話說，第一閘極151及第二閘極152屬於相同膜層，且第一閘極151及第二閘極152同時形成。Please refer to FIG. 1E. Next, a first gate 151 and a second gate 152 are formed on the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122 respectively. The method of forming the first gate 151 and the second gate 152 may include the following steps. First, a gate metal layer (not shown) is formed on the second insulating layer 140 . Then, a photolithography process is used to form a patterned photoresist (not shown) on the gate metal layer. Next, the patterned photoresist is used as a mask to perform a wet or dry etching process on the gate metal layer to form the first gate 151 and the second gate 152 . Afterwards, the patterned photoresist is removed. In other words, the first gate 151 and the second gate 152 belong to the same film layer, and the first gate 151 and the second gate 152 are formed at the same time.

第一閘極151於基板110的正投影重疊第一金屬氧化物半導體層121’於基板110的正投影，第二閘極152於基板110的正投影重疊第一絕緣層130於基板110的正投影。第一閘極151及第二閘極152的材料可包括金屬，例如鉻（Cr）、金（Au）、銀（Ag）、銅（Cu）、錫（Sn）、鉛（Pb）、鉿（Hf）、鎢（W）、鉬（Mo）、釹（Nd）、鈦（Ti）、鉭（Ta）、鋁（Al）、鋅（Zn）、或上述金屬的任意組合之合金、或上述金屬及/或合金之疊層，但不限於此。第一閘極151及第二閘極152也可以使用其他導電材料，例如：金屬的氮化物、金屬的氧化物、金屬的氮氧化物、金屬與其它導電材料的堆疊層、或是其它具有導電性質之材料。The first gate 151 overlaps the orthographic projection of the first metal oxide semiconductor layer 121 ′ on the substrate 110 , and the second gate 152 overlaps the orthographic projection of the first insulating layer 130 on the substrate 110 . projection. The materials of the first gate 151 and the second gate 152 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium ( Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or the above metals and/or alloy laminates, but not limited to this. The first gate 151 and the second gate 152 can also use other conductive materials, such as metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials, or other conductive materials. properties of materials.

請參照圖1F，在一些實施例中，在形成第一閘極151及第二閘極152之後，還可以進行摻雜製程IA。摻雜製程IA可以利用第一閘極151及第二閘極152作為罩幕，來對第一金屬氧化物半導體層121’及第二金屬氧化物半導體層122進行摻雜製程。在摻雜製程IA之後，第一金屬氧化物半導體層121’中重疊第一閘極151的部分可形成通道部分121c，且第一金屬氧化物半導體層121’中未重疊第一閘極151的第一部分121a及第二部分121b可具有較通道部分121c低的電阻。同樣地，第二金屬氧化物半導體層122中重疊第二閘極152的部分可形成通道部分122c，且第二金屬氧化物半導體層122中未重疊第二閘極152的第一部分122a及第二部分122b可具有較通道部分122c低的電阻。摻雜製程IA例如為氫電漿處理，且摻雜製程IA可以將氫元素植入第一金屬氧化物半導體層121’的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b中，使得第一金屬氧化物半導體層121’的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b的載子遷移率上升。在一些實施例中，第一金屬氧化物半導體層121’的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b能夠分別與後續形成的第一源極171、第一汲極172、第二源極173以及第二汲極174之間形成歐姆（ohmic）接觸。Referring to FIG. 1F , in some embodiments, after forming the first gate 151 and the second gate 152 , a doping process IA may also be performed. The doping process IA can use the first gate 151 and the second gate 152 as masks to perform a doping process on the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122. After the doping process IA, the portion of the first metal oxide semiconductor layer 121' that overlaps the first gate 151 may form a channel portion 121c, and the portion of the first metal oxide semiconductor layer 121' that does not overlap the first gate 151 can form a channel portion 121c. The first portion 121a and the second portion 121b may have a lower resistance than the channel portion 121c. Similarly, the portion of the second metal oxide semiconductor layer 122 that overlaps the second gate 152 can form the channel portion 122c, and the first portion 122a and the second portion of the second metal oxide semiconductor layer 122 that do not overlap the second gate 152 can form a channel portion 122c. Portion 122b may have a lower resistance than channel portion 122c. The doping process IA is, for example, hydrogen plasma treatment, and the doping process IA can implant hydrogen elements into the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122. In the first part 122a and the second part 122b, the carriers of the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121' and the first part 122a and the second part 122b of the second metal oxide semiconductor layer 122 are Migration rates increase. In some embodiments, the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the first portion 122a and the second portion 122b of the second metal oxide semiconductor layer 122 can be respectively connected with the subsequently formed first portion. An ohmic contact is formed between the source electrode 171 , the first drain electrode 172 , the second source electrode 173 and the second drain electrode 174 .

請參照圖1G，接著，形成第三絕緣層160於第一閘極151、第二閘極152及第二絕緣層140上。第三絕緣層160的形成方法可以包括以下步驟。首先，利用化學氣相沉積法或物理氣相沉積法，在基板110之上形成毯覆的介電材料層（未繪示）。接著，利用微影製程，在介電材料層上形成圖案化光阻（未繪示）。繼之，利用圖案化光阻作為罩幕，來對於介電材料層進行濕式或乾式蝕刻製程，以形成第三絕緣層160。之後，移除圖案化光阻。第三絕緣層160具有通孔V1、V2、V3、V4，其中通孔V1、V2可以貫穿第三絕緣層160及第二絕緣層140且分別暴露出第一金屬氧化物半導體層121’的第一部分121a及第二部分121b，通孔V3、V4可以貫穿第三絕緣層160、第二絕緣層140及第一絕緣層130且分別暴露出第二金屬氧化物半導體層122的第一部分122a及第二部分122b。第三絕緣層160的材料例如包括氧化矽、氮氧化矽、有機聚合物、或其他合適的材料、或上述材料之堆疊層。Please refer to FIG. 1G. Next, a third insulating layer 160 is formed on the first gate 151, the second gate 152 and the second insulating layer 140. The formation method of the third insulating layer 160 may include the following steps. First, a blanket dielectric material layer (not shown) is formed on the substrate 110 using a chemical vapor deposition method or a physical vapor deposition method. Next, a photolithography process is used to form a patterned photoresist (not shown) on the dielectric material layer. Then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the dielectric material layer to form the third insulating layer 160 . Afterwards, the patterned photoresist is removed. The third insulating layer 160 has through holes V1, V2, V3, and V4, wherein the through holes V1 and V2 can penetrate the third insulating layer 160 and the second insulating layer 140 and expose the third portion of the first metal oxide semiconductor layer 121' respectively. The part 121a and the second part 121b, the through holes V3 and V4 can penetrate the third insulating layer 160, the second insulating layer 140 and the first insulating layer 130 and expose the first part 122a and the second part of the second metal oxide semiconductor layer 122 respectively. Part II 122b. The material of the third insulating layer 160 includes, for example, silicon oxide, silicon oxynitride, organic polymer, or other suitable materials, or stacked layers of the above materials.

在一些實施例中，用以形成第三絕緣層160的反應物中含有氫元素，且在形成第三絕緣層160的過程中或在後續的熱處理製程中，氫元素可以遷移或擴散至第一金屬氧化物半導體層121’以及第二金屬氧化物半導體層122中，藉此調整第一金屬氧化物半導體層121’的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b的含氫量，進而提高其導電性。In some embodiments, the reactant used to form the third insulating layer 160 contains hydrogen, and during the process of forming the third insulating layer 160 or in the subsequent heat treatment process, the hydrogen may migrate or diffuse to the first In the metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122, the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the second portion of the second metal oxide semiconductor layer 122 are thereby adjusted. The hydrogen content in one part 122a and the second part 122b further improves their electrical conductivity.

請參照圖1H，接著，形成第一源極171、第一汲極172、第二源極173及第二汲極174於第三絕緣層160上，且第一源極171及第一汲極172電性連接至第一金屬氧化物半導體層121’，第二源極173及第二汲極174電性連接至第二金屬氧化物半導體層122，即可形成第一電晶體T1以及第二電晶體T2，且第一電晶體T1以及第二電晶體T2皆為頂閘極型（Top gate）薄膜電晶體。Please refer to FIG. 1H. Next, the first source electrode 171, the first drain electrode 172, the second source electrode 173 and the second drain electrode 174 are formed on the third insulating layer 160, and the first source electrode 171 and the first drain electrode are 172 is electrically connected to the first metal oxide semiconductor layer 121', and the second source electrode 173 and the second drain electrode 174 are electrically connected to the second metal oxide semiconductor layer 122, thereby forming the first transistor T1 and the second transistor T1. The transistor T2, the first transistor T1 and the second transistor T2 are all top gate thin film transistors.

舉例而言，第一源極171、第一汲極172、第二源極173及第二汲極174的形成方法可以包括以下步驟。首先，利用化學氣相沉積法或物理氣相沉積法，在基板110之上形成導電層（未繪示）。接著，利用微影製程，在導電層上形成圖案化光阻（未繪示）。繼之，利用圖案化光阻作為罩幕，來對於導電層進行濕式或乾式蝕刻製程，以形成第一源極171、第一汲極172、第二源極173及第二汲極174。之後，移除圖案化光阻。換句話說，第一源極171、第一汲極172、第二源極173及第二汲極174可以屬於相同膜層。第一源極171、第一汲極172、第二源極173及第二汲極174的材質可以包括鉻、金、銀、銅、錫、鉛、鉿、鎢、鉬、釹、鈦、鉭、鋁、鋅、前述金屬的合金、或前述金屬及/或合金之堆疊層、或其他導電材料。For example, a method of forming the first source 171 , the first drain 172 , the second source 173 and the second drain 174 may include the following steps. First, a conductive layer (not shown) is formed on the substrate 110 using a chemical vapor deposition method or a physical vapor deposition method. Next, a photolithography process is used to form a patterned photoresist (not shown) on the conductive layer. Then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the conductive layer to form the first source 171 , the first drain 172 , the second source 173 and the second drain 174 . Afterwards, the patterned photoresist is removed. In other words, the first source electrode 171 , the first drain electrode 172 , the second source electrode 173 and the second drain electrode 174 may belong to the same film layer. The materials of the first source electrode 171 , the first drain electrode 172 , the second source electrode 173 and the second drain electrode 174 may include chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, and tantalum. , aluminum, zinc, alloys of the aforementioned metals, or stacked layers of the aforementioned metals and/or alloys, or other conductive materials.

在本實施例中，第一源極171可以通過通孔V1而電性連接第一金屬氧化物半導體層121’的第一部分121a，第一汲極172可以通過通孔V2而電性連接第一金屬氧化物半導體層121’的第二部分121b，第二源極173可以通過通孔V3而電性連接第二金屬氧化物半導體層122的第一部分122a，第二汲極174可以通過通孔V4而電性連接第二金屬氧化物半導體層122的第二部分122b。In this embodiment, the first source electrode 171 can be electrically connected to the first portion 121a of the first metal oxide semiconductor layer 121' through the through hole V1, and the first drain electrode 172 can be electrically connected to the first drain electrode 172 through the through hole V2. The second portion 121b of the metal oxide semiconductor layer 121' and the second source electrode 173 can be electrically connected to the first portion 122a of the second metal oxide semiconductor layer 122 through the through hole V3, and the second drain electrode 174 can pass through the through hole V4. And electrically connected to the second portion 122b of the second metal oxide semiconductor layer 122.

在一些實施例中，還可以形成鈍化層180於第一源極171、第一汲極172、第二源極173、第二汲極174以及第三絕緣層160上。鈍化層180的形成方式可以是電漿化學氣相沈積法或其他合適的製程，鈍化層180的材料可以使用氮化矽或其他合適的材料。In some embodiments, a passivation layer 180 may also be formed on the first source electrode 171 , the first drain electrode 172 , the second source electrode 173 , the second drain electrode 174 and the third insulating layer 160 . The passivation layer 180 may be formed by plasma chemical vapor deposition or other suitable processes, and the material of the passivation layer 180 may be silicon nitride or other suitable materials.

圖1H是依照本發明一實施例的半導體裝置10的剖面示意圖。在本實施例中，半導體裝置10可以包括：基板110、第一電晶體T1以及第二電晶體T2，且第一電晶體T1及第二電晶體T2皆設置於基板110之上。FIG. 1H is a schematic cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention. In this embodiment, the semiconductor device 10 may include a substrate 110, a first transistor T1 and a second transistor T2, and the first transistor T1 and the second transistor T2 are both disposed on the substrate 110.

在一些實施例中，半導體裝置10還可以包括緩衝層112，且緩衝層112可以位於第一電晶體T1及第二電晶體T2與基板110之間，以避免基板110中的雜質擴散至第一電晶體T1及第二電晶體T2中。In some embodiments, the semiconductor device 10 may further include a buffer layer 112 , and the buffer layer 112 may be located between the first transistor T1 and the second transistor T2 and the substrate 110 to prevent impurities in the substrate 110 from diffusing to the first transistor. in the transistor T1 and the second transistor T2.

第一電晶體T1至少包括第一金屬氧化物半導體層121’。舉例而言，第一電晶體T1可以包括第一金屬氧化物半導體層121’、第一閘極151、第一源極171以及第一汲極172，且第二絕緣層140可位於第一閘極151與第一金屬氧化物半導體層121’之間，第三絕緣層160可位於第一源極171以及第一汲極172與第一閘極151之間。The first transistor T1 includes at least a first metal oxide semiconductor layer 121'. For example, the first transistor T1 may include a first metal oxide semiconductor layer 121', a first gate electrode 151, a first source electrode 171 and a first drain electrode 172, and the second insulating layer 140 may be located on the first gate electrode. Between the electrode 151 and the first metal oxide semiconductor layer 121 ′, the third insulating layer 160 may be located between the first source electrode 171 and the first drain electrode 172 and the first gate electrode 151 .

第一金屬氧化物半導體層121’可以包括第一部分121a、第二部分121b及通道部分121c，通道部分121c重疊第一閘極151，第一源極171電性連接第一部分121a，第一汲極172電性連接第二部分121b，且通道部分121c位於第一部分121a與第二部分121b之間。The first metal oxide semiconductor layer 121' may include a first part 121a, a second part 121b and a channel part 121c. The channel part 121c overlaps the first gate 151. The first source 171 is electrically connected to the first part 121a and the first drain. 172 is electrically connected to the second part 121b, and the channel part 121c is located between the first part 121a and the second part 121b.

第二電晶體T2至少包括第二金屬氧化物半導體層122及第一絕緣層130，其中，第二金屬氧化物半導體層122與第一金屬氧化物半導體層121’可屬於相同膜層。第一絕緣層130包覆第二金屬氧化物半導體層122。第一絕緣層130不接觸第一金屬氧化物半導體層121’，且第一絕緣層130不位於第一金屬氧化物半導體層121’與第一閘極151之間。舉例而言，第二電晶體T2可以包括第二金屬氧化物半導體層122、第一絕緣層130、第二閘極152、第二源極173以及第二汲極174，且第二絕緣層140位於第二閘極152與第一絕緣層130之間，第三絕緣層160位於第二源極173以及第二汲極174與第二閘極152之間。在本實施例中，第一金屬氧化物半導體層121’與第一閘極151之間夾有第一絕緣層130，且第二金屬氧化物半導體層122與第二閘極152之間夾有第一絕緣層130與第二絕緣層140。第一金屬氧化物半導體層121’與第一閘極151之間的距離小於第二金屬氧化物半導體層122與第二閘極152之間的距離。The second transistor T2 at least includes a second metal oxide semiconductor layer 122 and a first insulating layer 130, wherein the second metal oxide semiconductor layer 122 and the first metal oxide semiconductor layer 121' may belong to the same film layer. The first insulating layer 130 covers the second metal oxide semiconductor layer 122 . The first insulating layer 130 does not contact the first metal oxide semiconductor layer 121', and the first insulating layer 130 is not located between the first metal oxide semiconductor layer 121' and the first gate 151. For example, the second transistor T2 may include a second metal oxide semiconductor layer 122, a first insulating layer 130, a second gate 152, a second source 173 and a second drain 174, and the second insulating layer 140 Located between the second gate electrode 152 and the first insulating layer 130 , the third insulating layer 160 is located between the second source electrode 173 and the second drain electrode 174 and the second gate electrode 152 . In this embodiment, the first insulating layer 130 is sandwiched between the first metal oxide semiconductor layer 121' and the first gate 151, and the second metal oxide semiconductor layer 122 is sandwiched between the second gate 152 and the second gate 152. The first insulation layer 130 and the second insulation layer 140 . The distance between the first metal oxide semiconductor layer 121' and the first gate electrode 151 is smaller than the distance between the second metal oxide semiconductor layer 122 and the second gate electrode 152.

第二金屬氧化物半導體層122可以包括第一部分122a、第二部分122b及通道部分122c，通道部分122c重疊第二閘極152，第二源極173電性連接第一部分122a，第二汲極174電性連接第二部分122b，且通道部分122c位於第一部分122a與第二部分122b之間。The second metal oxide semiconductor layer 122 may include a first part 122a, a second part 122b and a channel part 122c. The channel part 122c overlaps the second gate 152, and the second source 173 is electrically connected to the first part 122a and the second drain 174. The second part 122b is electrically connected, and the channel part 122c is located between the first part 122a and the second part 122b.

在一些實施例中，第一金屬氧化物半導體層121’及第二金屬氧化物半導體層122的厚度可以為100Å至500Å，例如200Å、300Å或400Å，但本發明不以此為限。在一些實施例中，第一絕緣層130的厚度可以介於100Å至1000Å之間，例如300Å、500Å或700Å，但本發明不以此為限。在一些實施例中，第二絕緣層140的厚度可以介於300Å至2500Å之間，例如1000Å、1500Å或2000Å，但本發明不以此為限。In some embodiments, the thickness of the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122 may be 100Å to 500Å, such as 200Å, 300Å or 400Å, but the invention is not limited thereto. In some embodiments, the thickness of the first insulating layer 130 may be between 100Å and 1000Å, such as 300Å, 500Å or 700Å, but the invention is not limited thereto. In some embodiments, the thickness of the second insulating layer 140 may be between 300Å and 2500Å, such as 1000Å, 1500Å or 2000Å, but the invention is not limited thereto.

在一些實施例中，第一電晶體T1的第一金屬氧化物半導體層121’的載子遷移率大於50 cm 2/Vs，第二電晶體T2的第二金屬氧化物半導體層122的載子遷移率約介於10至30cm 2/Vs之間，且第二電晶體T2的臨界電壓（threshold voltage）高於第一電晶體T1的臨界電壓。由此可知，在半導體裝置10中，藉由以第一絕緣層130包覆第二金屬氧化物半導體層122來進行退火處理TA，能夠使第一金屬氧化物半導體層121’的氧濃度低於第二金屬氧化物半導體層122的氧濃度，並使第一金屬氧化物半導體層121’的載子遷移率大於第二金屬氧化物半導體層122的載子遷移率。藉此，減少第二電晶體T2的漏電流，同時使第一電晶體T1具有高驅動電流的優點，如此一來，第一電晶體T1可適用於作為驅動元件，且第二電晶體T2具有高可靠度而適用於作為開關元件。 In some embodiments, the carrier mobility of the first metal oxide semiconductor layer 121' of the first transistor T1 is greater than 50 cm 2 /Vs, and the carrier mobility of the second metal oxide semiconductor layer 122 of the second transistor T2 The mobility is approximately between 10 and 30 cm 2 /Vs, and the threshold voltage of the second transistor T2 is higher than the threshold voltage of the first transistor T1. It can be seen from this that in the semiconductor device 10 , by covering the second metal oxide semiconductor layer 122 with the first insulating layer 130 and performing the annealing treatment TA, the oxygen concentration of the first metal oxide semiconductor layer 121 ′ can be made lower than The oxygen concentration of the second metal oxide semiconductor layer 122 causes the carrier mobility of the first metal oxide semiconductor layer 121' to be greater than the carrier mobility of the second metal oxide semiconductor layer 122. Thereby, the leakage current of the second transistor T2 is reduced, while the first transistor T1 has the advantage of high driving current. In this way, the first transistor T1 can be suitable as a driving element, and the second transistor T2 has High reliability and suitable for use as switching components.

圖2A至圖2F是依照本發明另一實施例的半導體裝置20的製作方法的步驟流程的剖面示意圖。在此必須說明的是，圖2A至圖2F的實施例是接續於圖1C的步驟之後進行，且圖2A至圖2F的實施例沿用圖1A至圖1H的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。2A to 2F are schematic cross-sectional views of the steps of a method for manufacturing a semiconductor device 20 according to another embodiment of the present invention. It must be noted here that the embodiment of FIGS. 2A to 2F is performed after the steps of FIG. 1C, and the embodiment of FIGS. 2A to 2F follows the component numbers and part of the content of the embodiment of FIGS. 1A to 1H. The same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

請參照圖2A，在圖1C的退火處理TA之後，可以移除第一絕緣層130，以暴露出第二金屬氧化物半導體層122。移除第一絕緣層130的方式可以採用蝕刻製程或其他適合的方式。舉例而言，上述蝕刻製程可以使用對於第一絕緣層130具有相對較高蝕刻選擇性、但不易蝕刻第一金屬氧化物半導體層121’以及第二金屬氧化物半導體層122的蝕刻劑來進行。Referring to FIG. 2A , after the annealing process TA of FIG. 1C , the first insulating layer 130 may be removed to expose the second metal oxide semiconductor layer 122 . The first insulating layer 130 may be removed by etching or other suitable methods. For example, the above etching process can be performed using an etchant that has a relatively high etching selectivity for the first insulating layer 130 but is not easy to etch the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122.

請參照圖2B，接著，形成第二絕緣層140於基板110之上，且第二絕緣層140覆蓋第一金屬氧化物半導體層121’、第二金屬氧化物半導體層122及緩衝層112。Referring to FIG. 2B, next, a second insulating layer 140 is formed on the substrate 110, and the second insulating layer 140 covers the first metal oxide semiconductor layer 121', the second metal oxide semiconductor layer 122 and the buffer layer 112.

請參照圖2C，接著，分別形成第一閘極151及第二閘極152於第一金屬氧化物半導體層121’及第二金屬氧化物半導體層122之上，且第一閘極151於基板110的正投影重疊第一金屬氧化物半導體層121’於基板110的正投影，第二閘極152於基板110的正投影重疊第一絕緣層130於基板110的正投影。Please refer to FIG. 2C. Next, the first gate 151 and the second gate 152 are respectively formed on the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122, and the first gate 151 is formed on the substrate. The orthographic projection of 110 overlaps the orthographic projection of the first metal oxide semiconductor layer 121 ′ on the substrate 110 , and the orthographic projection of the second gate 152 overlaps the orthographic projection of the first insulating layer 130 on the substrate 110 .

請參照圖2D，在形成第一閘極151及第二閘極152之後，可以進行摻雜製程IA。摻雜製程IA可以利用第一閘極151及第二閘極152作為罩幕，來對第一金屬氧化物半導體層121’中未重疊第一閘極151的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122中未重疊第二閘極152的第一部分122a及第二部分122b植入氫元素，使得第一金屬氧化物半導體層121’的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b的載子遷移率上升。在摻雜製程IA之後，第一金屬氧化物半導體層121’中重疊第一閘極151的部分可形成通道部分121c，第二金屬氧化物半導體層122中重疊第二閘極152的部分可形成通道部分122c。Referring to FIG. 2D , after forming the first gate 151 and the second gate 152 , a doping process IA can be performed. The doping process IA can use the first gate 151 and the second gate 152 as masks to cover the first portion 121 a and the second portion 121 b of the first metal oxide semiconductor layer 121 ′ that do not overlap the first gate 151 and The first portion 122a and the second portion 122b of the second metal oxide semiconductor layer 122 that do not overlap the second gate 152 are implanted with hydrogen elements, so that the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and The carrier mobility of the first portion 122a and the second portion 122b of the second metal oxide semiconductor layer 122 increases. After the doping process IA, the portion of the first metal oxide semiconductor layer 121' overlapping the first gate 151 can form the channel portion 121c, and the portion of the second metal oxide semiconductor layer 122 overlapping the second gate 152 can form Channel portion 122c.

請參照圖2E，接著，形成具有通孔V1、V2、V3、V4的第三絕緣層160於第一閘極151、第二閘極152及第二絕緣層140上，其中，通孔V1、V2可以貫穿第三絕緣層160及第二絕緣層140且分別暴露出第一金屬氧化物半導體層121’的第一部分121a及第二部分121b，通孔V3、V4可以貫穿第三絕緣層160及第二絕緣層140且分別暴露出第二金屬氧化物半導體層122的第一部分122a及第二部分122b。在形成第三絕緣層160的過程中或在後續的熱處理製程中，氫元素可以遷移或擴散至第一金屬氧化物半導體層121’的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b中，藉以調整其含氫量，進而提高其導電性。Please refer to FIG. 2E. Next, a third insulating layer 160 having through holes V1, V2, V3, and V4 is formed on the first gate 151, the second gate 152, and the second insulating layer 140, wherein the through holes V1, V2 can penetrate the third insulating layer 160 and the second insulating layer 140 and expose the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' respectively. The through holes V3 and V4 can penetrate the third insulating layer 160 and the second insulating layer 140, respectively. The second insulating layer 140 exposes the first portion 122a and the second portion 122b of the second metal oxide semiconductor layer 122 respectively. During the formation of the third insulating layer 160 or in the subsequent heat treatment process, the hydrogen element may migrate or diffuse to the first portion 121 a and the second portion 121 b of the first metal oxide semiconductor layer 121 ′ and the second metal oxide semiconductor layer 121 ′. In the first part 122a and the second part 122b of the layer 122, the hydrogen content is adjusted to thereby improve the conductivity.

請參照圖2F，接著，形成第一源極171、第一汲極172、第二源極173及第二汲極174於第三絕緣層160上，且第一源極171及第一汲極172分別通過通孔V1、V2而電性連接至第一金屬氧化物半導體層121’的第一部分121a及第二部分121b，第二源極173及第二汲極174分別通過通孔V3、V4而電性連接至第二金屬氧化物半導體層122的第一部分122a及第二部分122b，即可形成第一電晶體T1以及第二電晶體T2A。在一些實施例中，還可以形成鈍化層180於第一電晶體T1以及第二電晶體T2A上。Please refer to FIG. 2F. Next, the first source electrode 171, the first drain electrode 172, the second source electrode 173 and the second drain electrode 174 are formed on the third insulating layer 160, and the first source electrode 171 and the first drain electrode are 172 is electrically connected to the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121' through the through holes V1 and V2 respectively, and the second source electrode 173 and the second drain electrode 174 pass through the through holes V3 and V4 respectively. The first portion 122a and the second portion 122b of the second metal oxide semiconductor layer 122 are electrically connected to form the first transistor T1 and the second transistor T2A. In some embodiments, a passivation layer 180 may also be formed on the first transistor T1 and the second transistor T2A.

圖2F是依照本發明另一實施例的半導體裝置20的剖面示意圖。在本實施例中，半導體裝置20可以包括：基板110、緩衝層112、第一電晶體T1、第二電晶體T2A以及鈍化層180，且第一電晶體T1及第二電晶體T2A可以設置於緩衝層112與鈍化層180之間。FIG. 2F is a schematic cross-sectional view of a semiconductor device 20 according to another embodiment of the present invention. In this embodiment, the semiconductor device 20 may include: a substrate 110, a buffer layer 112, a first transistor T1, a second transistor T2A, and a passivation layer 180, and the first transistor T1 and the second transistor T2A may be disposed on between the buffer layer 112 and the passivation layer 180 .

圖2F所示的半導體裝置20與圖1H所示的半導體裝置10的主要差異在於：半導體裝置20不包括第一絕緣層，且第二電晶體T2A可以包括第二金屬氧化物半導體層122、第二閘極152、第二源極173以及第二汲極174。第二絕緣層140位於第一閘極151與第一金屬氧化物半導體層121’以及第二閘極152與第二金屬氧化物半導體層122之間。在本實施例中，第一閘極151與第一金屬氧化物半導體層121’之間的距離實質上等於第二閘極152與第二金屬氧化物半導體層122之間的距離。The main difference between the semiconductor device 20 shown in FIG. 2F and the semiconductor device 10 shown in FIG. 1H is that the semiconductor device 20 does not include a first insulating layer, and the second transistor T2A may include a second metal oxide semiconductor layer 122, a third Two gates 152 , a second source 173 and a second drain 174 . The second insulating layer 140 is located between the first gate electrode 151 and the first metal oxide semiconductor layer 121' and between the second gate electrode 152 and the second metal oxide semiconductor layer 122. In this embodiment, the distance between the first gate 151 and the first metal oxide semiconductor layer 121' is substantially equal to the distance between the second gate 152 and the second metal oxide semiconductor layer 122.

在本實施例中，第一金屬氧化物半導體層121’的氧空缺濃度高於第二金屬氧化物半導體層122的氧空缺濃度，換句話說，第一金屬氧化物半導體層121’的氧濃度低於第二金屬氧化物半導體層122的氧濃度，而且，第一金屬氧化物半導體層121’的結晶度高於第二金屬氧化物半導體層122的結晶度，使得第一金屬氧化物半導體層121’的載子遷移率大於第二金屬氧化物半導體層122的載子遷移率。如此一來，第一電晶體T1具有驅動電流大的優點，且可適用於作為驅動元件；而第二電晶體T2A具有漏電流少的優點，且可適用於作為開關元件。In this embodiment, the oxygen vacancy concentration of the first metal oxide semiconductor layer 121' is higher than the oxygen vacancy concentration of the second metal oxide semiconductor layer 122. In other words, the oxygen concentration of the first metal oxide semiconductor layer 121' Lower than the oxygen concentration of the second metal oxide semiconductor layer 122, and the crystallinity of the first metal oxide semiconductor layer 121' is higher than the crystallinity of the second metal oxide semiconductor layer 122, so that the first metal oxide semiconductor layer The carrier mobility of 121' is greater than the carrier mobility of the second metal oxide semiconductor layer 122. In this way, the first transistor T1 has the advantage of large driving current and can be suitable as a driving element; while the second transistor T2A has the advantage of low leakage current and can be suitable as a switching element.

圖3A至圖3C是依照本發明又一實施例的半導體裝置30的製作方法的步驟流程的剖面示意圖。在此必須說明的是，圖3A至圖3C的實施例是在圖1F的步驟之後進行，且圖3A至圖3C的實施例沿用圖1A至圖1H的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。3A to 3C are schematic cross-sectional views of the steps of a method of manufacturing a semiconductor device 30 according to another embodiment of the present invention. It must be noted here that the embodiment of FIGS. 3A to 3C is performed after the steps of FIG. 1F, and the embodiment of FIGS. 3A to 3C follows the component numbers and part of the content of the embodiment of FIGS. 1A to 1H, where The same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

請參照圖3A，在圖1F的摻雜製程IA之後，可以利用第一閘極151及第二閘極152作為罩幕，來對第一絕緣層130以及第二絕緣層140進行圖案化處理。舉例而言，可以採用乾蝕刻製程來移除未被第一閘極151及第二閘極152覆蓋的第一絕緣層130以及第二絕緣層140，以形成第一絕緣層圖案132以及第二絕緣層圖案141、142。Referring to FIG. 3A , after the doping process IA of FIG. 1F , the first gate 151 and the second gate 152 can be used as masks to pattern the first insulating layer 130 and the second insulating layer 140 . For example, a dry etching process may be used to remove the first insulating layer 130 and the second insulating layer 140 that are not covered by the first gate 151 and the second gate 152 to form the first insulating layer pattern 132 and the second insulating layer 140 . Insulating layer patterns 141, 142.

第一絕緣層圖案132以及第二絕緣層圖案141、142暴露出第一金屬氧化物半導體層121’的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b。在上述圖案化處理之後，可以形成第一絕緣層圖案132以及第二絕緣層圖案141、142，其中第二絕緣層圖案141夾於第一閘極151與第一金屬氧化物半導體層121’的通道部分121c之間，且第一絕緣層圖案132及第二絕緣層圖案142夾於第二閘極152與第二金屬氧化物半導體層122的通道部分122c之間，換句話說，第二絕緣層圖案141的寬度W1可以實質上等於或近似於通道部分121c及第一閘極151的寬度，且第二絕緣層圖案142的寬度W2可以實質上等於或近似於通道部分122c、第二閘極152及第一絕緣層圖案132的寬度。The first insulating layer pattern 132 and the second insulating layer pattern 141, 142 expose the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the first portion 122a and the second portion 122a of the second metal oxide semiconductor layer 122. Part II 122b. After the above patterning process, the first insulating layer pattern 132 and the second insulating layer pattern 141, 142 can be formed, wherein the second insulating layer pattern 141 is sandwiched between the first gate 151 and the first metal oxide semiconductor layer 121'. between the channel portion 121c, and the first insulating layer pattern 132 and the second insulating layer pattern 142 are sandwiched between the second gate 152 and the channel portion 122c of the second metal oxide semiconductor layer 122. In other words, the second insulating layer The width W1 of the layer pattern 141 may be substantially equal to or approximately the width of the channel portion 121c and the first gate 151, and the width W2 of the second insulating layer pattern 142 may be substantially equal to or approximately equal to the width of the channel portion 122c and the second gate 151. 152 and the width of the first insulating layer pattern 132 .

請參照圖3B，接著，形成第三絕緣層160於基板110之上，同時調整第一金屬氧化物半導體層121’的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b的含氫量。第三絕緣層160可以覆蓋第一金屬氧化物半導體層121’的第一部分121a及第二部分121b的頂表面及側壁、第二金屬氧化物半導體層122的第一部分122a及第二部分122b的頂表面及側壁、第一絕緣層圖案132的側壁、第二絕緣層圖案141、142的側壁以及第一閘極151及第二閘極152的頂表面及側壁。Please refer to FIG. 3B. Next, a third insulating layer 160 is formed on the substrate 110, and the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the second portion of the second metal oxide semiconductor layer 122 are adjusted at the same time. The hydrogen content of one part 122a and the second part 122b. The third insulating layer 160 may cover the top surface and sidewalls of the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121', and the top surfaces of the first part 122a and the second part 122b of the second metal oxide semiconductor layer 122. The surface and sidewalls, the sidewalls of the first insulating layer pattern 132 , the sidewalls of the second insulating layer patterns 141 and 142 , and the top surface and sidewalls of the first gate 151 and the second gate 152 .

在一些實施例中，用以形成第三絕緣層160的反應物中含有氫元素，且在於第三絕緣層160中形成通孔V1、V2、V3、V4前，利用熱處理使第三絕緣層160中的氫元素遷移或擴散至第一金屬氧化物半導體層121’的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b中，藉此調整的第一部分121a、第二部分121b、第一部分122a及第二部分122b的含氫量，進而提高其導電性。在一些實施例中，利用第三絕緣層160中的氫元素對第一金屬氧化物半導體層121’以及第二金屬氧化物半導體層122進行氫摻雜，因此，可以省略對第一金屬氧化物半導體層121’以及第二金屬氧化物半導體層122進行氫電漿處理的步驟。In some embodiments, the reactant used to form the third insulating layer 160 contains hydrogen, and before forming the through holes V1, V2, V3, and V4 in the third insulating layer 160, the third insulating layer 160 is thermally treated. The hydrogen element in migrates or diffuses into the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121' and the first part 122a and the second part 122b of the second metal oxide semiconductor layer 122, thereby adjusting The hydrogen content of the first part 121a, the second part 121b, the first part 122a and the second part 122b further improves their electrical conductivity. In some embodiments, the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122 are hydrogen-doped using the hydrogen element in the third insulating layer 160. Therefore, the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122 may be omitted. The semiconductor layer 121' and the second metal oxide semiconductor layer 122 undergo a hydrogen plasma treatment step.

第三絕緣層160的通孔V1、V2、V3、V4可以分別暴露出第一金屬氧化物半導體層121’的第一部分121a及第二部分121b的頂表面以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b的頂表面。The through holes V1, V2, V3, and V4 of the third insulating layer 160 may respectively expose the top surfaces of the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122. The top surfaces of the first portion 122a and the second portion 122b.

請參照圖3C，接著，形成第一源極171、第一汲極172、第二源極173以及第二汲極174於第三絕緣層160上，且第一源極171、第一汲極172、第二源極173以及第二汲極174分別通過通孔V1、V2、V3、V4而電性連接至第一金屬氧化物半導體層121’的第一部分121a及第二部分121b以及第二金屬氧化物半導體層122的第一部分122a及第二部分122b，即可形成第一電晶體T1B以及第二電晶體T2B。在一些實施例中，還可以形成鈍化層180於第一電晶體T1B以及第二電晶體T2B上。Please refer to FIG. 3C. Next, the first source electrode 171, the first drain electrode 172, the second source electrode 173 and the second drain electrode 174 are formed on the third insulating layer 160, and the first source electrode 171, the first drain electrode 172. The second source electrode 173 and the second drain electrode 174 are electrically connected to the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121' through the through holes V1, V2, V3, and V4 respectively. The first portion 122a and the second portion 122b of the metal oxide semiconductor layer 122 can form the first transistor T1B and the second transistor T2B. In some embodiments, a passivation layer 180 may also be formed on the first transistor T1B and the second transistor T2B.

圖3C是依照本發明又一實施例的半導體裝置30的剖面示意圖。在本實施例中，半導體裝置30可以包括：基板110、緩衝層112、第一電晶體T1B、第二電晶體T2B以及鈍化層180，且第一電晶體T1B及第二電晶體T2B可以設置於緩衝層112與鈍化層180之間。FIG. 3C is a schematic cross-sectional view of a semiconductor device 30 according to yet another embodiment of the present invention. In this embodiment, the semiconductor device 30 may include: a substrate 110, a buffer layer 112, a first transistor T1B, a second transistor T2B, and a passivation layer 180, and the first transistor T1B and the second transistor T2B may be disposed on between the buffer layer 112 and the passivation layer 180 .

圖3C所示的半導體裝置30與圖1H所示的半導體裝置10的主要差異在於：半導體裝置30的第一電晶體T1B可以包括第一金屬氧化物半導體層121’、第二絕緣層圖案141、第一閘極151、第一源極171以及第一汲極172，且第二絕緣層圖案141夾於第一閘極151與第一金屬氧化物半導體層121’的通道部分121c之間；半導體裝置30的第二電晶體T2B可以包括第二金屬氧化物半導體層122、第一絕緣層圖案132、第二絕緣層圖案142、第二閘極152、第二源極173以及第二汲極174，且第一絕緣層圖案132以及第二絕緣層圖案142夾於第二閘極152與第二金屬氧化物半導體層122的通道部分122c之間；且第三絕緣層160直接接觸緩衝層。The main difference between the semiconductor device 30 shown in FIG. 3C and the semiconductor device 10 shown in FIG. 1H is that the first transistor T1B of the semiconductor device 30 may include a first metal oxide semiconductor layer 121', a second insulating layer pattern 141, The first gate 151, the first source 171 and the first drain 172, and the second insulating layer pattern 141 is sandwiched between the first gate 151 and the channel portion 121c of the first metal oxide semiconductor layer 121'; semiconductor The second transistor T2B of the device 30 may include a second metal oxide semiconductor layer 122, a first insulating layer pattern 132, a second insulating layer pattern 142, a second gate electrode 152, a second source electrode 173, and a second drain electrode 174. , and the first insulating layer pattern 132 and the second insulating layer pattern 142 are sandwiched between the second gate 152 and the channel portion 122c of the second metal oxide semiconductor layer 122; and the third insulating layer 160 directly contacts the buffer layer.

在本實施例中，第一金屬氧化物半導體層121’的氧空缺濃度高於第二金屬氧化物半導體層122的氧空缺濃度，換句話說，第一金屬氧化物半導體層121’的氧濃度低於第二金屬氧化物半導體層122的氧濃度，而且，第一金屬氧化物半導體層121’的結晶度高於第二金屬氧化物半導體層122的結晶度，使得第一金屬氧化物半導體層121’的載子遷移率大於第二金屬氧化物半導體層122的載子遷移率。如此一來，第一電晶體T1B可提供相對較大的驅動電流而適用於作為驅動元件，且第二電晶體T2B的漏電流相對較少而適用於作為開關元件。In this embodiment, the oxygen vacancy concentration of the first metal oxide semiconductor layer 121' is higher than the oxygen vacancy concentration of the second metal oxide semiconductor layer 122. In other words, the oxygen concentration of the first metal oxide semiconductor layer 121' Lower than the oxygen concentration of the second metal oxide semiconductor layer 122, and the crystallinity of the first metal oxide semiconductor layer 121' is higher than the crystallinity of the second metal oxide semiconductor layer 122, so that the first metal oxide semiconductor layer The carrier mobility of 121' is greater than the carrier mobility of the second metal oxide semiconductor layer 122. In this way, the first transistor T1B can provide a relatively large driving current and is suitable as a driving element, and the second transistor T2B has a relatively small leakage current and is suitable as a switching element.

圖4是依照本發明又另一實施例的半導體裝置40的剖面示意圖。在此必須說明的是，圖4的實施例沿用圖1A至圖1H的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 4 is a schematic cross-sectional view of a semiconductor device 40 according to yet another embodiment of the present invention. It must be noted here that the embodiment of FIG. 4 follows the component numbers and part of the content of the embodiment of FIGS. 1A to 1H , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

在本實施例中，半導體裝置40可以包括：基板110、緩衝層112、第一電晶體T1C、第二電晶體T2C以及鈍化層180，第一電晶體T1C及第二電晶體T2C設置於基板110之上，且設置於緩衝層112與鈍化層180之間。In this embodiment, the semiconductor device 40 may include: a substrate 110, a buffer layer 112, a first transistor T1C, a second transistor T2C, and a passivation layer 180. The first transistor T1C and the second transistor T2C are disposed on the substrate 110. on the buffer layer 112 and the passivation layer 180 .

圖4所示的半導體裝置40與如圖1H所示的半導體裝置10的主要差異在於：半導體裝置40的第一電晶體T1C及第二電晶體T2C為底閘極型（Bottom gate）薄膜電晶體。The main difference between the semiconductor device 40 shown in FIG. 4 and the semiconductor device 10 shown in FIG. 1H is that the first transistor T1C and the second transistor T2C of the semiconductor device 40 are bottom gate thin film transistors. .

舉例而言，在本實施例中，第一電晶體T1C可以包括第一金屬氧化物半導體層421、第一閘極451、第一源極471以及第一汲極472，其中第三絕緣層460可位於第一源極471以及第一汲極472與第一金屬氧化物半導體層421之間，第一源極471及第一汲極472分別通過第三絕緣層460中的通孔V1、V2而電性連接第一金屬氧化物半導體層421；第二絕緣層440位於第一金屬氧化物半導體層421與第一閘極451之間，且第一金屬氧化物半導體層421可以位於第一源極471與第一閘極451之間以及第一汲極472與第一閘極451之間。第一閘極451可重疊通孔V1、V2，以在第一金屬氧化物半導體層421未經過額外氫擴散或摻雜製程之下，確保電流可正常地從第一源極471及第一汲極472流出。For example, in this embodiment, the first transistor T1C may include a first metal oxide semiconductor layer 421, a first gate electrode 451, a first source electrode 471 and a first drain electrode 472, wherein the third insulating layer 460 The first source electrode 471 and the first drain electrode 472 can be located between the first source electrode 471 and the first drain electrode 472 and the first metal oxide semiconductor layer 421. The first source electrode 471 and the first drain electrode 472 pass through the through holes V1 and V2 in the third insulating layer 460 respectively. The first metal oxide semiconductor layer 421 is electrically connected; the second insulating layer 440 is located between the first metal oxide semiconductor layer 421 and the first gate 451, and the first metal oxide semiconductor layer 421 can be located on the first source. between the pole 471 and the first gate 451 and between the first drain 472 and the first gate 451 . The first gate 451 can overlap the through holes V1 and V2 to ensure that the current can normally flow from the first source 471 and the first drain without the first metal oxide semiconductor layer 421 undergoing additional hydrogen diffusion or doping processes. Extreme 472 outflow.

第二電晶體T2C可以包括第二金屬氧化物半導體層422、第一絕緣層430、第二閘極452、第二源極473以及第二汲極474，其中第二金屬氧化物半導體層422與第一電晶體T1C的第一金屬氧化物半導體層421可屬於相同膜層；第一絕緣層430包覆第二金屬氧化物半導體層422；第三絕緣層460及第一絕緣層430位於第二源極473以及第二汲極474與第二金屬氧化物半導體層422之間，第二源極473以及第二汲極474分別通過第三絕緣層460及第一絕緣層430中的通孔V3、V4而電性連接第二金屬氧化物半導體層422；第二絕緣層440位於第二金屬氧化物半導體層422與第二閘極452之間；且第二金屬氧化物半導體層422可以位於第二源極473與第二閘極452之間以及第二汲極474與第二閘極452之間。第二閘極452可重疊通孔V3、V4，以在第二金屬氧化物半導體層422未經過額外氫擴散或摻雜製程之下，確保電流可正常地從第二源極473及第二汲極474流出。The second transistor T2C may include a second metal oxide semiconductor layer 422, a first insulating layer 430, a second gate electrode 452, a second source electrode 473, and a second drain electrode 474, wherein the second metal oxide semiconductor layer 422 and The first metal oxide semiconductor layer 421 of the first transistor T1C may belong to the same film layer; the first insulating layer 430 covers the second metal oxide semiconductor layer 422; the third insulating layer 460 and the first insulating layer 430 are located in the second Between the source electrode 473 and the second drain electrode 474 and the second metal oxide semiconductor layer 422, the second source electrode 473 and the second drain electrode 474 pass through the through holes V3 in the third insulating layer 460 and the first insulating layer 430 respectively. , V4 to electrically connect the second metal oxide semiconductor layer 422; the second insulating layer 440 is located between the second metal oxide semiconductor layer 422 and the second gate 452; and the second metal oxide semiconductor layer 422 can be located between the second metal oxide semiconductor layer 422 and the second gate electrode 452. between the two sources 473 and the second gate 452 and between the second drain 474 and the second gate 452 . The second gate 452 can overlap the through holes V3 and V4 to ensure that the current can normally flow from the second source 473 and the second drain without the second metal oxide semiconductor layer 422 undergoing additional hydrogen diffusion or doping processes. Extremely 474 flows out.

在本實施例中，半導體裝置40的第一金屬氧化物半導體層421的氧空缺濃度高於第二金屬氧化物半導體層422的氧空缺濃度，第一金屬氧化物半導體層421的氧濃度低於第二金屬氧化物半導體層422的氧濃度，且第一金屬氧化物半導體層421的結晶度高於第二金屬氧化物半導體層422的結晶度。如此一來，能夠使第一金屬氧化物半導體層421的載子遷移率大於第二金屬氧化物半導體層422的載子遷移率，使得第一電晶體T1C可提供相對較大的驅動電流而適用於作為驅動元件，且第二電晶體T2C的漏電流較少因而適用於作為開關元件。第二電晶體T2C的臨界電壓能夠高於第一電晶體T1C的臨界電壓。In this embodiment, the oxygen vacancy concentration of the first metal oxide semiconductor layer 421 of the semiconductor device 40 is higher than the oxygen vacancy concentration of the second metal oxide semiconductor layer 422 , and the oxygen concentration of the first metal oxide semiconductor layer 421 is lower than that of the second metal oxide semiconductor layer 422 . The oxygen concentration of the second metal oxide semiconductor layer 422 and the crystallinity of the first metal oxide semiconductor layer 421 are higher than the crystallinity of the second metal oxide semiconductor layer 422 . In this way, the carrier mobility of the first metal oxide semiconductor layer 421 can be greater than the carrier mobility of the second metal oxide semiconductor layer 422, so that the first transistor T1C can provide a relatively large driving current and is suitable for It is suitable for use as a driving element, and the leakage current of the second transistor T2C is small, so it is suitable for use as a switching element. The threshold voltage of the second transistor T2C can be higher than the threshold voltage of the first transistor T1C.

綜上所述，本發明的半導體裝置的製作方法藉由直接疊置第一絕緣層於第二金屬氧化物半導體層上再進行退火處理，使得第一金屬氧化物半導體層的氧空缺濃度及結晶度能夠高於第二金屬氧化物半導體層。如此一來，第一金屬氧化物半導體層能夠具有提高的載子遷移率，使得第一電晶體適用於作為驅動元件，同時第二電晶體能夠具有降低的漏電流，使得第二電晶體具有高可靠度而適用於作為開關元件。In summary, the manufacturing method of the semiconductor device of the present invention directly stacks the first insulating layer on the second metal oxide semiconductor layer and then performs an annealing process, so that the oxygen vacancy concentration and crystallization of the first metal oxide semiconductor layer are improved. The degree can be higher than that of the second metal oxide semiconductor layer. In this way, the first metal oxide semiconductor layer can have improved carrier mobility, making the first transistor suitable as a driving element, while the second transistor can have reduced leakage current, so that the second transistor has high Reliability and suitable for use as switching components.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10, 20, 30, 40:半導體裝置 110:基板 112:緩衝層 121, 121’, 421:第一金屬氧化物半導體層 121a:第一部分 121b:第二部分 121c:通道部分 122, 422:第二金屬氧化物半導體層 122a:第一部分 122b:第二部分 122c:通道部分 130, 430:第一絕緣層 132:第一絕緣層圖案 140, 440:第二絕緣層 141, 142:第二絕緣層圖案 151, 451:第一閘極 152, 452:第二閘極 160, 460:第三絕緣層 171, 471:第一源極 172, 472:第一汲極 173, 473:第二源極 174, 474:第二汲極 180:鈍化層 IA:摻雜製程 T1, T1B, T1C:第一電晶體 T2, T2A, T2B, T2C:第二電晶體 TA:退火處理 V1, V2, V3, V4:通孔 W1, W2:寬度 10, 20, 30, 40: Semiconductor devices 110:Substrate 112:Buffer layer 121, 121’, 421: first metal oxide semiconductor layer 121a:Part 1 121b:Part 2 121c: Channel part 122, 422: Second metal oxide semiconductor layer 122a:Part 1 122b:Part 2 122c: Channel part 130, 430: First insulation layer 132: First insulation layer pattern 140, 440: Second insulation layer 141, 142: Second insulation layer pattern 151, 451: first gate 152, 452: Second gate 160, 460:Third insulation layer 171, 471: first source 172, 472: first drain 173, 473: Second source 174, 474: Second drain 180: Passivation layer IA: doping process T1, T1B, T1C: first transistor T2, T2A, T2B, T2C: second transistor TA: Annealing treatment V1, V2, V3, V4: through holes W1, W2: Width

圖1A至圖1H是依照本發明一實施例的半導體裝置的製作方法的步驟流程的剖面示意圖，其中，圖1H是依照本發明一實施例的半導體裝置的剖面示意圖。 圖2A至圖2F是依照本發明另一實施例的半導體裝置的製作方法的步驟流程的剖面示意圖，其中，圖2F是依照本發明另一實施例的半導體裝置的剖面示意圖。 圖3A至圖3C是依照本發明又一實施例的半導體裝置的製作方法的步驟流程的剖面示意圖，其中，圖3C是依照本發明又一實施例的半導體裝置的剖面示意圖。 圖4是依照本發明又另一實施例的半導體裝置的剖面示意圖。 1A to 1H are schematic cross-sectional views of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1H is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A to 2F are schematic cross-sectional views of the steps of a method for manufacturing a semiconductor device according to another embodiment of the present invention, wherein FIG. 2F is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. 3A to 3C are schematic cross-sectional views of the steps of a method for manufacturing a semiconductor device according to another embodiment of the present invention, wherein FIG. 3C is a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present invention.

10:半導體裝置 110:基板 112:緩衝層 121’:第一金屬氧化物半導體層 121a:第一部分 121b:第二部分 121c:通道部分 122:第二金屬氧化物半導體層 122a:第一部分 122b:第二部分 122c:通道部分 130:第一絕緣層 140:第二絕緣層 151:第一閘極 152:第二閘極 160:第三絕緣層 171:第一源極 172:第一汲極 173:第二源極 174:第二汲極 180:鈍化層 T1:第一電晶體 T2:第二電晶體 V1, V2, V3, V4:通孔 10:Semiconductor device 110:Substrate 112:Buffer layer 121’: first metal oxide semiconductor layer 121a:Part 1 121b:Part 2 121c: Channel part 122: Second metal oxide semiconductor layer 122a:Part 1 122b:Part 2 122c: Channel part 130: First insulation layer 140: Second insulation layer 151: first gate 152: Second gate 160:Third insulation layer 171:First source 172: first drain 173:Second Source 174: The second drain 180: Passivation layer T1: the first transistor T2: Second transistor V1, V2, V3, V4: through holes

Claims (16)

一種半導體裝置，包括：一基板；一第一電晶體，設置於該基板之上，且該第一電晶體包括一第一金屬氧化物半導體層以及重疊於該第一金屬氧化物半導體層的一第一閘極；以及一第二電晶體，設置於該基板之上，且該第二電晶體包括：一第二金屬氧化物半導體層，其中該第二金屬氧化物半導體層與該第一金屬氧化物半導體層屬於相同膜層，且該第一金屬氧化物半導體層的氧濃度低於該第二金屬氧化物半導體層的氧濃度；一第二閘極，重疊於該第二金屬氧化物半導體層；以及一第一絕緣層，包覆該第二金屬氧化物半導體層，且不位於該第一金屬氧化物半導體層與該第一閘極之間。 A semiconductor device includes: a substrate; a first transistor disposed on the substrate, and the first transistor includes a first metal oxide semiconductor layer and a first metal oxide semiconductor layer overlapping the first metal oxide semiconductor layer. a first gate; and a second transistor disposed on the substrate, and the second transistor includes: a second metal oxide semiconductor layer, wherein the second metal oxide semiconductor layer and the first metal The oxide semiconductor layers belong to the same film layer, and the oxygen concentration of the first metal oxide semiconductor layer is lower than the oxygen concentration of the second metal oxide semiconductor layer; a second gate overlaps the second metal oxide semiconductor layer layer; and a first insulating layer covering the second metal oxide semiconductor layer and not located between the first metal oxide semiconductor layer and the first gate. 如請求項1所述的半導體裝置，其中該第一金屬氧化物半導體層的氧空缺濃度高於該第二金屬氧化物半導體層的氧空缺濃度，且該第一金屬氧化物半導體層的結晶度高於該第二金屬氧化物半導體層的結晶度。 The semiconductor device of claim 1, wherein the oxygen vacancy concentration of the first metal oxide semiconductor layer is higher than the oxygen vacancy concentration of the second metal oxide semiconductor layer, and the crystallinity of the first metal oxide semiconductor layer Higher than the crystallinity of the second metal oxide semiconductor layer. 如請求項1所述的半導體裝置，更包括一第二絕緣層，其中該第二絕緣層覆蓋該第一金屬氧化物半導體層以及該第一絕緣層，且其中該第一金屬氧化物半導體層與該第一閘極之間 之間夾有該第二絕緣層，該第二金屬氧化物半導體層與該第二閘極之間夾有該第一絕緣層以及該第二絕緣層。 The semiconductor device of claim 1, further comprising a second insulating layer, wherein the second insulating layer covers the first metal oxide semiconductor layer and the first insulating layer, and wherein the first metal oxide semiconductor layer and the first gate The second insulating layer is sandwiched between the second metal oxide semiconductor layer and the second gate. The first insulating layer and the second insulating layer are sandwiched between the second metal oxide semiconductor layer and the second gate. 如請求項1所述的半導體裝置，其中該第一金屬氧化物半導體層的載子遷移率大於該第二金屬氧化物半導體層的載子遷移率。 The semiconductor device of claim 1, wherein the carrier mobility of the first metal oxide semiconductor layer is greater than the carrier mobility of the second metal oxide semiconductor layer. 如請求項1所述的半導體裝置，其中該第一金屬氧化物半導體層及該第二金屬氧化物半導體層包含相同的金屬元素。 The semiconductor device of claim 1, wherein the first metal oxide semiconductor layer and the second metal oxide semiconductor layer contain the same metal element. 如請求項1所述的半導體裝置，其中該第一金屬氧化物半導體層及該第二金屬氧化物半導體層包括銦鋅氧化物、銦鎢氧化物、銦鎢鋅氧化物、銦鋅錫氧化物、銦鎵錫氧化物或銦鎵鋅錫氧化物。 The semiconductor device of claim 1, wherein the first metal oxide semiconductor layer and the second metal oxide semiconductor layer include indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, and indium zinc tin oxide. , indium gallium tin oxide or indium gallium zinc tin oxide. 如請求項1所述的半導體裝置，其中該第一金屬氧化物半導體層及該第二金屬氧化物半導體層的厚度為100Å至500Å。 The semiconductor device according to claim 1, wherein the thickness of the first metal oxide semiconductor layer and the second metal oxide semiconductor layer is 100Å to 500Å. 如請求項1所述的半導體裝置，其中該第一絕緣層包括含氧絕緣層或阻氧層。 The semiconductor device of claim 1, wherein the first insulating layer includes an oxygen-containing insulating layer or an oxygen barrier layer. 如請求項1所述的半導體裝置，其中該第二電晶體的臨界電壓高於該第一電晶體的臨界電壓。 The semiconductor device of claim 1, wherein the threshold voltage of the second transistor is higher than the threshold voltage of the first transistor. 一種半導體裝置的製作方法，包括： 形成一第一金屬氧化物半導體層及一第二金屬氧化物半導體層於一基板之上，且該第一金屬氧化物半導體層與該第二金屬氧化物半導體層屬於相同膜層；形成一第一絕緣層以包覆該第二金屬氧化物半導體層，且該第一絕緣層不接觸該第一金屬氧化物半導體層；進行一退火處理，以使該第一金屬氧化物半導體層的氧濃度低於該第二金屬氧化物半導體層的氧濃度；以及形成一第一閘極及一第二閘極於該基板之上，且該第一閘極及該第二閘極分別重疊該第一金屬氧化物半導體層及該第二金屬氧化物半導體層。 A method of manufacturing a semiconductor device, including: Forming a first metal oxide semiconductor layer and a second metal oxide semiconductor layer on a substrate, and the first metal oxide semiconductor layer and the second metal oxide semiconductor layer belong to the same film layer; forming a first metal oxide semiconductor layer An insulating layer is used to cover the second metal oxide semiconductor layer, and the first insulating layer does not contact the first metal oxide semiconductor layer; an annealing process is performed to increase the oxygen concentration of the first metal oxide semiconductor layer. The oxygen concentration is lower than the second metal oxide semiconductor layer; and forming a first gate and a second gate on the substrate, and the first gate and the second gate respectively overlap the first A metal oxide semiconductor layer and the second metal oxide semiconductor layer. 如請求項10所述的半導體裝置的製作方法，其中該退火處理包括在200℃至500℃之間維持30分鐘至180分鐘。 The method of manufacturing a semiconductor device as claimed in claim 10, wherein the annealing process includes maintaining between 200°C and 500°C for 30 minutes to 180 minutes. 如請求項10所述的半導體裝置的製作方法，其中同時形成該第一閘極及該第二閘極。 The method of manufacturing a semiconductor device according to claim 10, wherein the first gate and the second gate are formed simultaneously. 如請求項10所述的半導體裝置的製作方法，還包括在形成該第一閘極及該第二閘極之前形成一第二絕緣層於該基板之上，且該第二絕緣層位於該第一閘極與該第一金屬氧化物半導體層之間以及該第二閘極與該第一絕緣層之間。 The method of manufacturing a semiconductor device according to claim 10, further comprising forming a second insulating layer on the substrate before forming the first gate and the second gate, and the second insulating layer is located on the first gate. between a gate and the first metal oxide semiconductor layer and between the second gate and the first insulating layer. 如請求項10所述的半導體裝置的製作方法，還包括在形成該第一閘極及該第二閘極之後，以該第一閘極及該第二閘極為罩幕對該第一金屬氧化物半導體層以及該第二金屬氧化物半導體層進行一摻雜製程。 The method of manufacturing a semiconductor device according to claim 10, further comprising: after forming the first gate and the second gate, oxidizing the first metal with the first gate and the second gate as a mask The material semiconductor layer and the second metal oxide semiconductor layer undergo a doping process. 如請求項14所述的半導體裝置的製作方法，還包括在該摻雜製程之後形成一第三絕緣層於該第一閘極以及該第二閘極上。 The method of manufacturing a semiconductor device according to claim 14, further comprising forming a third insulating layer on the first gate and the second gate after the doping process. 如請求項15所述的半導體裝置的製作方法，還包括形成一第一源極、一第一汲極、一第二源極及一第二汲極於該第三絕緣層上，且該第一源極及該第一汲極電性連接至該第一金屬氧化物半導體層，該第二源極及該第二汲極電性連接至該第二金屬氧化物半導體層。The method of manufacturing a semiconductor device according to claim 15, further comprising forming a first source, a first drain, a second source and a second drain on the third insulating layer, and the third A source electrode and the first drain electrode are electrically connected to the first metal oxide semiconductor layer, and the second source electrode and the second drain electrode are electrically connected to the second metal oxide semiconductor layer.
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