TWI813217B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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TWI813217B
TWI813217B TW111110923A TW111110923A TWI813217B TW I813217 B TWI813217 B TW I813217B TW 111110923 A TW111110923 A TW 111110923A TW 111110923 A TW111110923 A TW 111110923A TW I813217 B TWI813217 B TW I813217B
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metal oxide
oxide layer
doped region
layer
thin film
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TW202324716A (en
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范揚順
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友達光電股份有限公司
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Priority to US17/881,612 priority patent/US20230187454A1/en
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Abstract

A semiconductor device includes a substrate, a first thin film transistor and a second thin film transistor. The first and second thin film transistors are disposed on the substrate. The first thin film transistor includes stacked first and second metal oxide layers. The oxygen concentration of the first metal oxide layer is smaller than the oxygen concentration of the second metal oxide layer, and the thickness of the second metal oxide layer is smaller than the thickness of the first metal oxide layer. A two-dimensional electron gas is located at an interface between the first and second metal oxide layers. The second thin film transistor is electrically connected to the first thin film transistor. The second thin film transistor includes a third metal oxide layer. The second and third metal oxide layers belong to a same patterned layer.

Description

半導體裝置及其製造方法Semiconductor device and manufacturing method thereof

本發明是有關於一種半導體裝置，且特別是有關於一種包括金屬氧化物層的半導體裝置及其製造方法。 The present invention relates to a semiconductor device, and in particular, to a semiconductor device including a metal oxide layer and a manufacturing method thereof.

目前，常見的薄膜電晶體通常以非晶矽半導體作為通道，其中非晶矽半導體由於製程簡單且成本低廉，因此以廣泛的應用於各種薄膜電晶體中。 At present, common thin film transistors usually use amorphous silicon semiconductors as channels. Amorphous silicon semiconductors are widely used in various thin film transistors due to their simple manufacturing process and low cost.

隨著顯示技術的進步，顯示面板的解析度逐年提升。為了使畫素電路中的薄膜電晶體縮小，許多廠商致力於研發新的半導體材料，例如金屬氧化物半導體材料。在金屬氧化物半導體材料中，氧化銦鎵鋅(indium gallium zinc oxide，IGZO)同時具有面積小以及電子遷移率高的優點，因此被視為一種重要的新型半導體材料。 With the advancement of display technology, the resolution of display panels is increasing year by year. In order to shrink thin film transistors in pixel circuits, many manufacturers are committed to developing new semiconductor materials, such as metal oxide semiconductor materials. Among metal oxide semiconductor materials, indium gallium zinc oxide (IGZO) has the advantages of small area and high electron mobility, so it is regarded as an important new semiconductor material.

本發明提供一種半導體裝置，具有效率高以及製造成本 低的優點。 The present invention provides a semiconductor device with high efficiency and low manufacturing cost. Low advantages.

本發明提供一種半導體裝置的製造方法，具有製造成本低的優點，且所製造的半導體裝置具有效率高的優點。 The present invention provides a method for manufacturing a semiconductor device, which has the advantage of low manufacturing cost, and the manufactured semiconductor device has the advantage of high efficiency.

本發明的至少一實施例提供一種半導體裝置。半導體裝置包括基板、第一薄膜電晶體以及第二薄膜電晶體。第一薄膜電晶體以及第二薄膜電晶體設置於基板之上。第一薄膜電晶體包括堆疊的第一金屬氧化物層以及第二金屬氧化物層。第一金屬氧化物層的氧濃度小於第二金屬氧化物層的氧濃度，第二金屬氧化物層的厚度小於第一金屬氧化物層的厚度。二維電子氣位於第一金屬氧化物層以及第二金屬氧化物層之間的界面。第二薄膜電晶體與第一薄膜電晶體電性連接。第二薄膜電晶體包括第三金屬氧化物層。第二金屬氧化物層與第三金屬氧化物層屬於同一圖案化層。 At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor and the second thin film transistor are disposed on the substrate. The first thin film transistor includes a stacked first metal oxide layer and a second metal oxide layer. The oxygen concentration of the first metal oxide layer is less than the oxygen concentration of the second metal oxide layer, and the thickness of the second metal oxide layer is less than the thickness of the first metal oxide layer. The two-dimensional electron gas is located at the interface between the first metal oxide layer and the second metal oxide layer. The second thin film transistor is electrically connected to the first thin film transistor. The second thin film transistor includes a third metal oxide layer. The second metal oxide layer and the third metal oxide layer belong to the same patterned layer.

本發明的至少一實施例提供一種半導體裝置的製造方法，包括：形成第一薄膜電晶體於基板之上，第一薄膜電晶體包括堆疊的第一金屬氧化物層以及第二金屬氧化物層，其中第一金屬氧化物層的氧濃度小於第二金屬氧化物層的氧濃度，第二金屬氧化物層的厚度小於第一金屬氧化物層的厚度，其中二維電子氣位於第一金屬氧化物層以及第二金屬氧化物層之間的界面；形成第二薄膜電晶體於基板之上，其中第二薄膜電晶體與第一薄膜電晶體電性連接，第二薄膜電晶體包括第三金屬氧化物層，且第二金屬氧化物層與第三金屬氧化物層同時形成。 At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a first thin film transistor on a substrate, the first thin film transistor including a stacked first metal oxide layer and a second metal oxide layer, The oxygen concentration of the first metal oxide layer is less than the oxygen concentration of the second metal oxide layer, the thickness of the second metal oxide layer is less than the thickness of the first metal oxide layer, and the two-dimensional electron gas is located in the first metal oxide layer. The interface between the layer and the second metal oxide layer; forming a second thin film transistor on the substrate, wherein the second thin film transistor is electrically connected to the first thin film transistor, and the second thin film transistor includes a third metal oxide layer material layer, and the second metal oxide layer and the third metal oxide layer are formed simultaneously.

10,20,30,40,50,60:半導體裝置 10,20,30,40,50,60:Semiconductor device

100:基板 100:Substrate

102:緩衝層 102:Buffer layer

110:閘介電層 110: Gate dielectric layer

112:開口 112:Open your mouth

120:層間介電層 120: Interlayer dielectric layer

122:第一接觸孔 122: First contact hole

124:第二接觸孔 124: Second contact hole

126:第三接觸孔 126: Third contact hole

128:第四接觸孔 128:Fourth contact hole

200:第一薄膜電晶體 200:The first thin film transistor

210:第一金屬氧化物層 210: First metal oxide layer

212:第五摻雜區 212: The fifth doped region

214:第六摻雜區 214: The sixth doping region

220,220a:第二金屬氧化物層 220,220a: second metal oxide layer

222:第一摻雜區 222: First doped region

224:第二摻雜區 224: Second doping region

226:第一通道區 226:First channel area

230:第一閘極 230: first gate

242:第一源極 242:First Source

244:第一汲極 244: first drain

300:第二薄膜電晶體 300: Second thin film transistor

320,320a:第三金屬氧化物層 320,320a: The third metal oxide layer

322:第三摻雜區 322: The third doped region

324:第二通道區 324: Second channel area

326:第四摻雜區 326: The fourth doped region

330,330A:第二閘極 330,330A: Second gate

342:第二源極 342:Second Source

344:第二汲極 344: The second drain

2DEG:二維電子氣 2DEG: two-dimensional electron gas

C:電容 C: capacitor

LED:發光二極體 LED: light emitting diode

ND:法線方向 ND: normal direction

OS1:第一金屬氧化物圖案 OS1: The first metal oxide pattern

OS2:第二金屬氧化物圖案 OS2: Second metal oxide pattern

T1,T2,T3:厚度 T1, T2, T3: Thickness

圖1是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖2A至圖2E是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 2A to 2E are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention.

圖3是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖4是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖5是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖6是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖7是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

圖8是依照本發明的一實施例的一種半導體裝置的電路示意圖。 FIG. 8 is a schematic circuit diagram of a semiconductor device according to an embodiment of the present invention.

圖1是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

請參考圖1，半導體裝置10包括基板100、第一薄膜電晶體200以及第二薄膜電晶體300。 Referring to FIG. 1 , the semiconductor device 10 includes a substrate 100 , a first thin film transistor 200 and a second thin film transistor 300 .

基板100的材料例如包括玻璃、石英、有機聚合物或不透光/反射材料(例如：導電材料、金屬、晶圓、陶瓷或其他可適用的材料)或是其他可適用的材料。 The material of the substrate 100 includes, for example, glass, quartz, organic polymers, opaque/reflective materials (such as conductive materials, metals, wafers, ceramics or other applicable materials) or other applicable materials.

緩衝層102形成於基板100的表面。緩衝層102的材料例如包括氧化矽、氮化矽、氮氧化矽或其他絕緣材料。在一些實施例中，緩衝層102為單層結構或多層結構。 The buffer layer 102 is formed on the surface of the substrate 100 . The material of the buffer layer 102 includes, for example, silicon oxide, silicon nitride, silicon oxynitride or other insulating materials. In some embodiments, the buffer layer 102 is a single-layer structure or a multi-layer structure.

第一薄膜電晶體200設置於基板100之上。在本實施例中，第一薄膜電晶體200形成於緩衝層102上。第一薄膜電晶體包括第一金屬氧化物層210、第二金屬氧化物層220、第一閘極230、第一源極242與第一汲極244。 The first thin film transistor 200 is disposed on the substrate 100 . In this embodiment, the first thin film transistor 200 is formed on the buffer layer 102 . The first thin film transistor includes a first metal oxide layer 210, a second metal oxide layer 220, a first gate electrode 230, a first source electrode 242 and a first drain electrode 244.

第一金屬氧化物層210以及第二金屬氧化物層220位於基板100之上且彼此互相堆疊。在本實施例中，第一金屬氧化物層210以及第二金屬氧化物層220依序形成於緩衝層102上。第一金屬氧化物層210的氧濃度小於第二金屬氧化物層220的氧濃度。在一些實施例中，第一金屬氧化物層210的氧濃度為10at%至50at%，且第二金屬氧化物層220的氧濃度為30at%至70at%。在一些實施例中，藉由調整氧濃度，使第一金屬氧化物層210的能隙(Band Gap)小於第二金屬氧化物層220的能隙，藉此於第一金屬氧化物層210以及第二金屬氧化物層220之間的界面形成二維電子氣2DEG。第二金屬氧化物層220的厚度T2小於第一金 屬氧化物層210的厚度T1，藉此使二維電子氣2DEG更容易的形成於前述界面。在一些實施例中，第一金屬氧化物層210的厚度T1為10奈米至60奈米，第二金屬氧化物層220的厚度T2為5奈米至30奈米。在一些實施例中，第一金屬氧化物層210以及第二金屬氧化物層220的材料包括銦鎵鋅氧化物、銦錫鋅氧化物、鋁鋅錫氧化物、銦鎢鋅氧化物等四元化合物或包含前述四元化合物中的其中兩種金屬元素以及氧元素的三元化合物。 The first metal oxide layer 210 and the second metal oxide layer 220 are located on the substrate 100 and stacked on each other. In this embodiment, the first metal oxide layer 210 and the second metal oxide layer 220 are sequentially formed on the buffer layer 102 . The oxygen concentration of the first metal oxide layer 210 is smaller than the oxygen concentration of the second metal oxide layer 220 . In some embodiments, the oxygen concentration of the first metal oxide layer 210 is 10at% to 50at%, and the oxygen concentration of the second metal oxide layer 220 is 30at% to 70at%. In some embodiments, by adjusting the oxygen concentration, the energy gap (Band Gap) of the first metal oxide layer 210 is smaller than the energy gap of the second metal oxide layer 220 , whereby the first metal oxide layer 210 and The interface between the second metal oxide layers 220 forms a two-dimensional electron gas 2DEG. The thickness T2 of the second metal oxide layer 220 is smaller than the thickness T2 of the first metal oxide layer 220 . The thickness T1 of the oxide layer 210 makes it easier for the two-dimensional electron gas 2DEG to be formed at the aforementioned interface. In some embodiments, the thickness T1 of the first metal oxide layer 210 ranges from 10 nanometers to 60 nanometers, and the thickness T2 of the second metal oxide layer 220 ranges from 5 nanometers to 30 nanometers. In some embodiments, the materials of the first metal oxide layer 210 and the second metal oxide layer 220 include quaternary elements such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, and indium tungsten zinc oxide. compound or a ternary compound containing two of the metal elements and oxygen in the aforementioned quaternary compound.

第二金屬氧化物層220包括第一摻雜區222、第二摻雜區226以及位於第一摻雜區222與第二摻雜區226之間的第一通道區224。在一些實施例中，通過氫電漿處理形成第一摻雜區222與第二摻雜區226，其中第一摻雜區222與第二摻雜區226的氧空缺濃度低於第一通道區224的氧空缺濃度，第一摻雜區222與第二摻雜區226的導電率高於第一通道區224的導電率。 The second metal oxide layer 220 includes a first doped region 222, a second doped region 226, and a first channel region 224 located between the first doped region 222 and the second doped region 226. In some embodiments, the first doped region 222 and the second doped region 226 are formed by hydrogen plasma treatment, wherein the oxygen vacancy concentration of the first doped region 222 and the second doped region 226 is lower than that of the first channel region. With an oxygen vacancy concentration of 224, the conductivity of the first doped region 222 and the second doped region 226 is higher than the conductivity of the first channel region 224 .

閘介電層110位於第二金屬氧化物層220上。在一些實施例中，閘介電層110的材料包括氧化矽、氮化矽、氮氧化矽、氧化鉿、氧化鋁或其他絕緣材料。在一些實施例中，閘介電層110的厚度為50奈米至300奈米。 The gate dielectric layer 110 is located on the second metal oxide layer 220 . In some embodiments, the material of the gate dielectric layer 110 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide or other insulating materials. In some embodiments, the gate dielectric layer 110 has a thickness of 50 nanometers to 300 nanometers.

第一閘極230位於閘介電層110上。第一閘極230在基板100的頂面的法線方向ND上重疊於第一金屬氧化物層210以及第二金屬氧化物層220的第一通道區224。閘介電層110位於第一閘極230與第二金屬氧化物層220之間。第一閘極230通過閘介電層的開口而接觸第二金屬氧化物層220的第一通道區224。在 本實施例中，前述閘介電層的開口的寬度小於第一通道區224的寬度。在一些實施例中，第一閘極230的材料包括鎢、鉬、鉑、金或其他高功函數金屬或上述材料的組合。第一閘極230與第二金屬氧化物層220之間具有肖特基接觸(Schottky contact)。 The first gate 230 is located on the gate dielectric layer 110 . The first gate 230 overlaps the first channel region 224 of the first metal oxide layer 210 and the second metal oxide layer 220 in the normal direction ND of the top surface of the substrate 100 . The gate dielectric layer 110 is located between the first gate electrode 230 and the second metal oxide layer 220 . The first gate 230 contacts the first channel region 224 of the second metal oxide layer 220 through the opening of the gate dielectric layer. exist In this embodiment, the width of the opening of the gate dielectric layer is smaller than the width of the first channel region 224 . In some embodiments, the material of the first gate 230 includes tungsten, molybdenum, platinum, gold or other high work function metals or a combination of the above materials. There is a Schottky contact between the first gate 230 and the second metal oxide layer 220 .

層間介電層120設置於閘介電層110上。層間介電層120覆蓋第一閘極230。在一些實施例中，層間介電層120的材料包括氧化矽、氮化矽、氮氧化矽、氧化鉿、氧化鋁或其他絕緣材料。在一些實施例中，層間介電層120的厚度為100奈米至600奈米。 The interlayer dielectric layer 120 is disposed on the gate dielectric layer 110 . The interlayer dielectric layer 120 covers the first gate 230 . In some embodiments, the material of the interlayer dielectric layer 120 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide or other insulating materials. In some embodiments, the interlayer dielectric layer 120 has a thickness of 100 nanometers to 600 nanometers.

第一源極242與第一汲極244設置於層間介電層120上，且透過層間介電層120中接觸孔而分別連接至第二金屬氧化物層220的第一摻雜區222與第二摻雜區226。在一些實施例中，第一源極242與第一汲極244的材料包括鋁、鈦、鉬、銅或上述金屬的合金或上述材料的組合。在一些實施例中，第一源極242與第二金屬氧化物層220之間以及第一汲極244與第二金屬氧化物層220之間具有肖特基接觸或歐姆接觸(Ohmic contact)。 The first source electrode 242 and the first drain electrode 244 are disposed on the interlayer dielectric layer 120 and are respectively connected to the first doped region 222 and the second doped region 222 of the second metal oxide layer 220 through the contact holes in the interlayer dielectric layer 120 . Two doped regions 226. In some embodiments, the materials of the first source electrode 242 and the first drain electrode 244 include aluminum, titanium, molybdenum, copper or alloys of the above metals or combinations of the above materials. In some embodiments, there is Schottky contact or Ohmic contact between the first source electrode 242 and the second metal oxide layer 220 and between the first drain electrode 244 and the second metal oxide layer 220 .

在本實施例中，第一薄膜電晶體200為金屬-半導體場效電晶體(Metal Semiconductor Field Effect Transistor，MESFET)，且第一薄膜電晶體200為常開型(normally-on)的電晶體。由於第一薄膜電晶體200包括二維電子氣2DEG，第一薄膜電晶體200適用於高電流的驅動電晶體。此外，由於第一薄膜電晶體200的第一閘極230接觸第二金屬氧化物層220，可以減少第一閘極230與第二金屬氧化物層220之間的絕緣層出現的電荷捕獲效應 (charge trapping effect)，藉此提升第一薄膜電晶體200的效率。 In this embodiment, the first thin film transistor 200 is a Metal Semiconductor Field Effect Transistor (MESFET), and the first thin film transistor 200 is a normally-on transistor. Since the first thin film transistor 200 includes two-dimensional electron gas 2DEG, the first thin film transistor 200 is suitable for a high current driving transistor. In addition, since the first gate electrode 230 of the first thin film transistor 200 contacts the second metal oxide layer 220, the charge trapping effect in the insulating layer between the first gate electrode 230 and the second metal oxide layer 220 can be reduced. (charge trapping effect), thereby improving the efficiency of the first thin film transistor 200.

第二薄膜電晶體300設置於基板100之上。在本實施例中，第二薄膜電晶體300形成於緩衝層102上。第二薄膜電晶體包括第三金屬氧化物層320、第二閘極330、第二源極342與第二汲極344。第二薄膜電晶體300與第一薄膜電晶體200電性連接。舉例來說，第二薄膜電晶體300的第二汲極344透過圖1中未繪出的導線而電性連接第一薄膜電晶體200的第一閘極230。 The second thin film transistor 300 is disposed on the substrate 100 . In this embodiment, the second thin film transistor 300 is formed on the buffer layer 102 . The second thin film transistor includes a third metal oxide layer 320, a second gate electrode 330, a second source electrode 342 and a second drain electrode 344. The second thin film transistor 300 is electrically connected to the first thin film transistor 200 . For example, the second drain electrode 344 of the second thin film transistor 300 is electrically connected to the first gate electrode 230 of the first thin film transistor 200 through a wire not shown in FIG. 1 .

第三金屬氧化物層320位於基板100之上。在本實施例中，第三金屬氧化物層320形成於緩衝層102上。在一些實施例中，第三金屬氧化物層320的厚度T3為5奈米至30奈米。在一些實施例中，第三金屬氧化物層320的材料包括銦鎵鋅氧化物、銦錫鋅氧化物、鋁鋅錫氧化物、銦鎢鋅氧化物等四元化合物或包含前述四元化合物中的其中兩種金屬元素以及氧元素的三元化合物。第一金屬氧化物層210的氧濃度小於第三金屬氧化物層320的氧濃度。在一些實施例中，第二金屬氧化物層220與第三金屬氧化物層230屬於同一圖案化層，也可以說第二金屬氧化物層220與第三金屬氧化物層230的形狀是於同一次的圖案化製程中定義出來。第二金屬氧化物層220與第三金屬氧化物層230包括相同的材料。 The third metal oxide layer 320 is located on the substrate 100 . In this embodiment, the third metal oxide layer 320 is formed on the buffer layer 102 . In some embodiments, the thickness T3 of the third metal oxide layer 320 is 5 nm to 30 nm. In some embodiments, the material of the third metal oxide layer 320 includes quaternary compounds such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, or other quaternary compounds. A ternary compound of two metal elements and oxygen. The oxygen concentration of the first metal oxide layer 210 is smaller than the oxygen concentration of the third metal oxide layer 320 . In some embodiments, the second metal oxide layer 220 and the third metal oxide layer 230 belong to the same patterned layer. It can also be said that the shapes of the second metal oxide layer 220 and the third metal oxide layer 230 are the same. defined in the patterning process. The second metal oxide layer 220 and the third metal oxide layer 230 include the same material.

第三金屬氧化物層320包括第三摻雜區322、第四摻雜區326以及位於第三摻雜區322與第四摻雜區326之間的第二通道區324。在一些實施例中，通過氫電漿處理形成第三摻雜區322與第 四摻雜區326，其中第三摻雜區322與第四摻雜區326的氧空缺濃度高於第二通道區324的氧空缺濃度，第三摻雜區322與第四摻雜區326的導電率高於第二通道區324的導電率。在一些實施例中，於同一次的氫電漿處理形成第二金屬氧化物層220的第一摻雜區222與第二摻雜區226以及第三金屬氧化物層320的第三摻雜區322以及第四摻雜區326。 The third metal oxide layer 320 includes a third doped region 322 , a fourth doped region 326 , and a second channel region 324 located between the third doped region 322 and the fourth doped region 326 . In some embodiments, the third doped region 322 and the third doped region are formed by hydrogen plasma treatment. Four doped regions 326, in which the oxygen vacancy concentration of the third doped region 322 and the fourth doped region 326 is higher than the oxygen vacancy concentration of the second channel region 324. The third doped region 322 and the fourth doped region 326 have The conductivity is higher than the conductivity of the second channel region 324 . In some embodiments, the first doped region 222 and the second doped region 226 of the second metal oxide layer 220 and the third doped region of the third metal oxide layer 320 are formed in the same hydrogen plasma treatment. 322 and the fourth doped region 326.

第二閘極330位於閘介電層110上。第二閘極330在基板100的頂面的法線方向ND上重疊於第三金屬氧化物層320的第二通道區324。閘介電層110位於第二閘極330與第三金屬氧化物層320之間。第二閘極330不接觸第三金屬氧化物層320。在一些實施例中，第一閘極230與第二閘極330屬於同一圖案化層，也可以說第一閘極230與第二閘極330的形狀是於同一次的圖案化製程中定義出來。第一閘極230與第二閘極330包括相同的材料。 The second gate 330 is located on the gate dielectric layer 110 . The second gate 330 overlaps the second channel region 324 of the third metal oxide layer 320 in the normal direction ND of the top surface of the substrate 100 . The gate dielectric layer 110 is located between the second gate electrode 330 and the third metal oxide layer 320 . The second gate 330 does not contact the third metal oxide layer 320 . In some embodiments, the first gate 230 and the second gate 330 belong to the same patterned layer. It can also be said that the shapes of the first gate 230 and the second gate 330 are defined in the same patterning process. . The first gate 230 and the second gate 330 include the same material.

第二源極322與第二汲極326設置於層間介電層120上，且透過層間介電層120中接觸孔而分別連接至第三金屬氧化物層320的第三摻雜區322以及第四摻雜區326。在一些實施例中，第二源極322與第二汲極326的材料包括鋁、鈦、鉬、銅或上述材料的組合。在一些實施例中，第二源極322與第三金屬氧化物層320之間以及第二汲極326與第三金屬氧化物層320之間具有肖特基接觸或歐姆接觸(Ohmic contact)。在一些實施例中，第一源極222、第一汲極226、第二源極322與第二汲極326屬於同一圖案 化層，也可以說第一源極222、第一汲極226、第二源極322與第二汲極326的形狀是於同一次的圖案化製程中定義出來。第一源極222、第一汲極226、第二源極322與第二汲極326包括相同的材料。 The second source electrode 322 and the second drain electrode 326 are disposed on the interlayer dielectric layer 120 and are respectively connected to the third doped region 322 and the third metal oxide layer 320 through the contact holes in the interlayer dielectric layer 120 . Four doped regions 326. In some embodiments, the materials of the second source electrode 322 and the second drain electrode 326 include aluminum, titanium, molybdenum, copper, or a combination of the above materials. In some embodiments, there is Schottky contact or Ohmic contact between the second source electrode 322 and the third metal oxide layer 320 and between the second drain electrode 326 and the third metal oxide layer 320 . In some embodiments, the first source electrode 222, the first drain electrode 226, the second source electrode 322 and the second drain electrode 326 belong to the same pattern. layer, it can also be said that the shapes of the first source electrode 222, the first drain electrode 226, the second source electrode 322 and the second drain electrode 326 are defined in the same patterning process. The first source electrode 222 , the first drain electrode 226 , the second source electrode 322 and the second drain electrode 326 include the same material.

在本實施例中，第二薄膜電晶體300為金屬-氧化物-半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)，且第二薄膜電晶體300為常閉型(normally-off)的電晶體。 In this embodiment, the second thin film transistor 300 is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the second thin film transistor 300 is normally-off. of transistors.

圖2A至圖2E是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 2A to 2E are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention.

請參考圖2A，形成第一金屬氧化物圖案OS1於基板100之上。第一金屬氧化物圖案OS1包括第一金屬氧化物層210。 Referring to FIG. 2A , a first metal oxide pattern OS1 is formed on the substrate 100 . The first metal oxide pattern OS1 includes a first metal oxide layer 210 .

請參考圖2B，形成第二金屬氧化物圖案OS2於第一金屬氧化物圖案OS1以及基板100之上。第二金屬氧化物圖案OS2包括第二金屬氧化物層220a以及第三金屬氧化物層320a。 Referring to FIG. 2B , a second metal oxide pattern OS2 is formed on the first metal oxide pattern OS1 and the substrate 100 . The second metal oxide pattern OS2 includes a second metal oxide layer 220a and a third metal oxide layer 320a.

請參考圖2C，形成閘介電層110於第二金屬氧化物圖案OS2上。閘介電層110具有重疊並暴露出第二金屬氧化物層220a的開口112。 Referring to FIG. 2C, a gate dielectric layer 110 is formed on the second metal oxide pattern OS2. The gate dielectric layer 110 has an opening 112 overlapping and exposing the second metal oxide layer 220a.

請參考圖2C與2D，形成第一閘極230以及第二閘極330於閘介電層110上。第二金屬氧化物層220a重疊於第一閘極230，且第三金屬氧化物層320a重疊於第二閘極330。第一閘極230通過開口112接觸第二金屬氧化物層220a。 Referring to FIGS. 2C and 2D , the first gate 230 and the second gate 330 are formed on the gate dielectric layer 110 . The second metal oxide layer 220a overlaps the first gate 230, and the third metal oxide layer 320a overlaps the second gate 330. The first gate 230 contacts the second metal oxide layer 220a through the opening 112.

以第一閘極230與第二閘極330為罩幕對第二金屬氧化物層220a以及第三金屬氧化物層320a執行摻雜製程，以形成包括第一摻雜區222、第二摻雜區226以及第一通道區224的第二金屬氧化物層220以及包括第三摻雜區322、第四摻雜區326以及第二通道區324的第三金屬氧化物層320。第一通道區224位於第一摻雜區222與第二摻雜區226之間，且第二通道區324位於第三摻雜區322與第四摻雜區326之間。在本實施例中，在基板100的頂面的法線方向ND上，第一通道區224以及第二通道區324分別重疊於第一閘極230以及第二閘極330。 Using the first gate 230 and the second gate 330 as masks, a doping process is performed on the second metal oxide layer 220a and the third metal oxide layer 320a to form a first doped region 222, a second doped region region 226 and the second metal oxide layer 220 of the first channel region 224 and the third metal oxide layer 320 including the third doped region 322 , the fourth doped region 326 and the second channel region 324 . The first channel region 224 is located between the first doped region 222 and the second doped region 226 , and the second channel region 324 is located between the third doped region 322 and the fourth doped region 326 . In this embodiment, in the normal direction ND of the top surface of the substrate 100, the first channel region 224 and the second channel region 324 overlap the first gate 230 and the second gate 330 respectively.

在一些實施例中，摻雜製程例如為氫電漿摻雜製程或其他合適的製程，透過摻雜製程減少第一摻雜區222、第二摻雜區226、第三摻雜區322以及第四摻雜區326中的氧空缺，以提升第一摻雜區222、第二摻雜區226、第三摻雜區322以及第四摻雜區326的導電率。 In some embodiments, the doping process is, for example, a hydrogen plasma doping process or other suitable processes. Through the doping process, the first doped region 222 , the second doped region 226 , the third doped region 322 and the third doped region are reduced. The oxygen vacancies in the fourth doped region 326 increase the conductivity of the first doped region 222 , the second doped region 226 , the third doped region 322 and the fourth doped region 326 .

請參考圖2E，形成層間介電層120於閘介電層110上。執行一次或多次蝕刻製程以形成穿過層間介電層120以及閘介電層110的第一接觸孔122、第二接觸孔124、第三接觸孔126以及第四接觸孔128。第一接觸孔122以及第二接觸孔124重疊並暴露出第二金屬氧化物層220的第一摻雜區222以及第二摻雜區226，且第三接觸孔126以及第四接觸孔128重疊並暴露出第三金屬氧化物層320的第三摻雜區322以及第四摻雜區326。 Referring to FIG. 2E, an interlayer dielectric layer 120 is formed on the gate dielectric layer 110. One or more etching processes are performed to form the first, second, third and fourth contact holes 122 , 124 , 126 and 128 through the interlayer dielectric layer 120 and the gate dielectric layer 110 . The first contact hole 122 and the second contact hole 124 overlap and expose the first doped region 222 and the second doped region 226 of the second metal oxide layer 220, and the third contact hole 126 and the fourth contact hole 128 overlap. And the third doped region 322 and the fourth doped region 326 of the third metal oxide layer 320 are exposed.

最後請參考圖2E與圖1，形成第一源極242、第一汲極 244、第二源極342與第二汲極344於層間介電層120上，且形成第一源極242、第一汲極244、第二源極342與第二汲極344於第一接觸孔122、第二接觸孔124、第三接觸孔126以及第四接觸孔128中。第一源極242與第一汲極244分別連接至第二金屬氧化物層220的第一摻雜區222以及第二摻雜區226，且第二源極342與第二汲極344分別連接至第三金屬氧化物層320的第三摻雜區322以及第四摻雜區326。 Finally, please refer to Figure 2E and Figure 1 to form the first source 242 and the first drain 244. The second source electrode 342 and the second drain electrode 344 are formed on the interlayer dielectric layer 120, and the first source electrode 242, the first drain electrode 244, the second source electrode 342 and the second drain electrode 344 are formed on the first contact hole 122 , the second contact hole 124 , the third contact hole 126 and the fourth contact hole 128 . The first source electrode 242 and the first drain electrode 244 are respectively connected to the first doped region 222 and the second doped region 226 of the second metal oxide layer 220, and the second source electrode 342 and the second drain electrode 344 are respectively connected. to the third doped region 322 and the fourth doped region 326 of the third metal oxide layer 320 .

圖3是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖3的實施例沿用圖1至圖2E的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of Figure 3 follows the component numbers and part of the content of the embodiment of Figures 1 to 2E, where the same or similar numbers are used to represent the same or similar elements, and references to the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

圖3的半導體裝置20與圖1的半導體裝置10的主要差異在於：半導體裝置20的第一閘極230包括多層結構。 The main difference between the semiconductor device 20 of FIG. 3 and the semiconductor device 10 of FIG. 1 is that the first gate 230 of the semiconductor device 20 includes a multi-layer structure.

請參考圖3，第一閘極230包括金屬層234與P型半導體層232的堆疊，其中P型半導體層232接觸第二金屬氧化物層220。在本實施例中，第一薄膜電晶體200為常閉型(normally-off)的電晶體。 Referring to FIG. 3 , the first gate 230 includes a stack of a metal layer 234 and a P-type semiconductor layer 232 , where the P-type semiconductor layer 232 contacts the second metal oxide layer 220 . In this embodiment, the first thin film transistor 200 is a normally-off transistor.

圖4是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖4的實施例沿用圖1至圖2E的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略 部分的說明可參考前述實施例，在此不贅述。 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of Figure 4 follows the component numbers and part of the content of the embodiment of Figures 1 to 2E, where the same or similar numbers are used to represent the same or similar elements, and references to the same technical content are omitted. instruction. About omission Part of the description may refer to the foregoing embodiments and will not be described again here.

圖4的半導體裝置30與圖1的半導體裝置10的主要差異在於：半導體裝置30的第一源極242與第一汲極244延伸穿過第二金屬氧化物層220。 The main difference between the semiconductor device 30 of FIG. 4 and the semiconductor device 10 of FIG. 1 is that the first source electrode 242 and the first drain electrode 244 of the semiconductor device 30 extend through the second metal oxide layer 220 .

請參考圖4，第一源極242與第一汲極244延伸穿過第二金屬氧化物層220，並接觸第一金屬氧化物層210以及第二金屬氧化物層220的界面。換句話說，第一源極242與第一汲極244直接接觸二維電子氣2DEG，藉此提升第一薄膜電晶體200的輸出電流大小。 Referring to FIG. 4 , the first source electrode 242 and the first drain electrode 244 extend through the second metal oxide layer 220 and contact the interface of the first metal oxide layer 210 and the second metal oxide layer 220 . In other words, the first source 242 and the first drain 244 directly contact the two-dimensional electron gas 2DEG, thereby increasing the output current of the first thin film transistor 200 .

在本實施例中，第二源極342與第二汲極344亦延伸穿過第三金屬氧化物層320，但本發明不以此為限。在其他實施例中，第二源極342與第二汲極344未穿過第三金屬氧化物層320。 In this embodiment, the second source electrode 342 and the second drain electrode 344 also extend through the third metal oxide layer 320, but the invention is not limited thereto. In other embodiments, the second source electrode 342 and the second drain electrode 344 do not pass through the third metal oxide layer 320 .

圖5是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖5的實施例沿用圖1至圖2E的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 5 follows the component numbers and part of the content of the embodiment of FIGS. 1 to 2E , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

圖5的半導體裝置40與圖1的半導體裝置10的主要差異在於：半導體裝置40的第一金屬氧化物層210包括第五摻雜區212以及第六摻雜區214。 The main difference between the semiconductor device 40 of FIG. 5 and the semiconductor device 10 of FIG. 1 is that the first metal oxide layer 210 of the semiconductor device 40 includes a fifth doped region 212 and a sixth doped region 214 .

在本實施例中，執行摻雜製程以於第二金屬氧化物層220中形成第一摻雜區222以及第二摻雜區226，且摻雜製程於第一金 屬氧化物層210中形成第五摻雜區212以及第六摻雜區214。換句話說，摻雜製程中的摻子(例如氫原子)穿過第二金屬氧化物層220後抵達第一金屬氧化物層210，並於第一金屬氧化物層210中形成第五摻雜區212以及第六摻雜區214。第五摻雜區212以及第六摻雜區214分別接觸第一摻雜區222的底部以及第二摻雜區226的底部。 In this embodiment, a doping process is performed to form the first doping region 222 and the second doping region 226 in the second metal oxide layer 220, and the doping process is performed on the first metal oxide layer 220. A fifth doped region 212 and a sixth doped region 214 are formed in the metal oxide layer 210 . In other words, the dopants (such as hydrogen atoms) in the doping process pass through the second metal oxide layer 220 and then reach the first metal oxide layer 210, and form the fifth dopant in the first metal oxide layer 210. region 212 and the sixth doped region 214. The fifth doped region 212 and the sixth doped region 214 respectively contact the bottom of the first doped region 222 and the bottom of the second doped region 226 .

在一些實施例中，第五摻雜區212的厚度以及第六摻雜區214的厚度小於第一金屬氧化物層210的厚度。 In some embodiments, the thickness of the fifth doped region 212 and the thickness of the sixth doped region 214 are less than the thickness of the first metal oxide layer 210 .

在一些實施例中，第一摻雜區222、第二摻雜區226、第三摻雜區322、第四摻雜區326、第五摻雜區212以及第六摻雜區214的寬度隨著靠近基板100而逐漸縮小。第一摻雜區222以及第二摻雜區226朝向第一通道區224的面為弧面，且第三摻雜區322以及第四摻雜區326朝向第二通道區324的面為弧面。 In some embodiments, the widths of the first doped region 222 , the second doped region 226 , the third doped region 322 , the fourth doped region 326 , the fifth doped region 212 and the sixth doped region 214 vary with It gradually shrinks as it gets closer to the substrate 100 . The surfaces of the first doped region 222 and the second doped region 226 facing the first channel region 224 are curved surfaces, and the surfaces of the third doped region 322 and the fourth doped region 326 facing the second channel region 324 are curved surfaces. .

圖6是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖6的實施例沿用圖1至圖2E的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of Figure 6 follows the component numbers and part of the content of the embodiment of Figures 1 to 2E, where the same or similar numbers are used to represent the same or similar elements, and references to the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

圖6的半導體裝置50與圖1的半導體裝置10的主要差異在於：半導體裝置50的第二薄膜電晶體300為底部閘極型薄膜電晶體。 The main difference between the semiconductor device 50 of FIG. 6 and the semiconductor device 10 of FIG. 1 is that the second thin film transistor 300 of the semiconductor device 50 is a bottom gate type thin film transistor.

請參考圖6，第二薄膜電晶體300的第二閘極330A位於 第三金屬氧化物層320與基板100之間。第一閘極230與第二閘極330A屬於不同圖案化層，也可以說第一閘極230與第二閘極330A的形狀是於不同次的圖案化製程中定義出來。 Please refer to FIG. 6 , the second gate 330A of the second thin film transistor 300 is located at between the third metal oxide layer 320 and the substrate 100 . The first gate 230 and the second gate 330A belong to different patterned layers. It can also be said that the shapes of the first gate 230 and the second gate 330A are defined in different patterning processes.

圖7是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖7的實施例沿用圖1至圖2E的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of Figure 7 follows the component numbers and part of the content of the embodiment of Figures 1 to 2E, where the same or similar numbers are used to represent the same or similar elements, and references to the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

圖7的半導體裝置60與圖1的半導體裝置10的主要差異在於：半導體裝置60的第二薄膜電晶體300為雙閘極型薄膜電晶體。 The main difference between the semiconductor device 60 of FIG. 7 and the semiconductor device 10 of FIG. 1 is that the second thin film transistor 300 of the semiconductor device 60 is a dual-gate thin film transistor.

請參考圖6，第二薄膜電晶體300包括兩個閘極，即第二閘極330以及第二閘極330A，其中第三金屬氧化物層320位於第二閘極330以及第二閘極330A之間。 Please refer to FIG. 6 , the second thin film transistor 300 includes two gates, namely a second gate 330 and a second gate 330A, in which the third metal oxide layer 320 is located on the second gate 330 and the second gate 330A. between.

圖8是依照本發明的一實施例的一種半導體裝置的電路示意圖。圖8可以為前述任一實施例的半導體裝置的電路示意圖。 FIG. 8 is a schematic circuit diagram of a semiconductor device according to an embodiment of the present invention. FIG. 8 may be a schematic circuit diagram of a semiconductor device according to any of the foregoing embodiments.

請參考圖8，第一薄膜電晶體200的第一閘極電性連接至第二薄膜電晶體300的第二汲極。在本實施例中，第一薄膜電晶體200的第一汲極與第二薄膜電晶體300的第二汲極之間包括電容C，且第一薄膜電晶體200的第一汲極電性連接至發光二極體LED。 Referring to FIG. 8 , the first gate electrode of the first thin film transistor 200 is electrically connected to the second drain electrode of the second thin film transistor 300 . In this embodiment, a capacitor C is included between the first drain electrode of the first thin film transistor 200 and the second drain electrode of the second thin film transistor 300 , and the first drain electrode of the first thin film transistor 200 is electrically connected. to the light emitting diode LED.

綜上所述，本發明的第一薄膜電晶體包括第一金屬氧化 物層以及第二金屬氧化物層，其中第一金屬氧化物層以及第二金屬氧化物層之間的界面具有二維電子氣，因此，可以提升第一薄膜電晶體200的輸出電流大小。 To sum up, the first thin film transistor of the present invention includes a first metal oxide The interface between the first metal oxide layer and the second metal oxide layer has a two-dimensional electron gas. Therefore, the output current of the first thin film transistor 200 can be increased.

10:半導體裝置 10:Semiconductor device

100:基板 100:Substrate

102:緩衝層 102:Buffer layer

110:閘介電層 110: Gate dielectric layer

120:層間介電層 120: Interlayer dielectric layer

200:第一薄膜電晶體 200:The first thin film transistor

210:第一金屬氧化物層 210: First metal oxide layer

220:第二金屬氧化物層 220: Second metal oxide layer

222:第一摻雜區 222: First doped region

224:第二摻雜區 224: Second doping region

226:第一通道區 226:First channel area

230:第一閘極 230: first gate

242:第一源極 242:First Source

244:第一汲極 244: first drain

300:第二薄膜電晶體 300: Second thin film transistor

320:第三金屬氧化物層 320: Third metal oxide layer

322:第三摻雜區 322: The third doped region

324:第二通道區 324: Second channel area

326:第四摻雜區 326: The fourth doped region

330:第二閘極 330: Second gate

342:第二源極 342:Second Source

344:第二汲極 344: The second drain

2DEG:二維電子氣 2DEG: two-dimensional electron gas

ND:法線方向 ND: normal direction

T1,T2,T3:厚度 T1, T2, T3: Thickness

Claims (17)

一種半導體裝置，包括：一基板；一第一薄膜電晶體，設置於該基板之上，該第一薄膜電晶體包括：堆疊的一第一金屬氧化物層以及一第二金屬氧化物層，其中該第一金屬氧化物層的氧濃度小於該第二金屬氧化物層的氧濃度，該第二金屬氧化物層的厚度小於該第一金屬氧化物層的厚度，其中一二維電子氣位於該第一金屬氧化物層以及該第二金屬氧化物層之間的界面；一第一閘極，在該基板的頂面的一法線方向上重疊於該第一金屬氧化物層以及該第二金屬氧化物層，其中一閘介電層位於該第一閘極與該第二金屬氧化物層之間，該第一閘極通過該閘介電層的一開口而接觸該第二金屬氧化物層，且一層間介電層設置於該閘介電層上；以及一第一源極與一第一汲極，設置於該層間介電層上，且分別連接至該第二金屬氧化物層；以及一第二薄膜電晶體，設置於該基板之上，並與該第一薄膜電晶體電性連接，其中該第二薄膜電晶體包括一第三金屬氧化物層，且該第二金屬氧化物層與該第三金屬氧化物層屬於同一圖案化層。 A semiconductor device includes: a substrate; a first thin film transistor disposed on the substrate; the first thin film transistor includes: a stacked first metal oxide layer and a second metal oxide layer, wherein The oxygen concentration of the first metal oxide layer is less than the oxygen concentration of the second metal oxide layer, the thickness of the second metal oxide layer is less than the thickness of the first metal oxide layer, wherein a two-dimensional electron gas is located in the The interface between the first metal oxide layer and the second metal oxide layer; a first gate overlapping the first metal oxide layer and the second metal oxide layer in a normal direction of the top surface of the substrate Metal oxide layer, wherein a gate dielectric layer is located between the first gate electrode and the second metal oxide layer, the first gate electrode contacts the second metal oxide through an opening of the gate dielectric layer layer, and an interlayer dielectric layer is disposed on the gate dielectric layer; and a first source electrode and a first drain electrode are disposed on the interlayer dielectric layer and are respectively connected to the second metal oxide layer ; and a second thin film transistor, disposed on the substrate and electrically connected to the first thin film transistor, wherein the second thin film transistor includes a third metal oxide layer, and the second metal oxide layer The physical layer and the third metal oxide layer belong to the same patterned layer. 如請求項1所述的半導體裝置，其中該第二金屬氧化物層包括一第一摻雜區、一第二摻雜區以及位於該第一摻雜區與該第二摻雜區之間的一第一通道區，該層間介電層包括重疊於該第一摻雜區的一第一接觸孔以及重疊於該第二摻雜區的一第二接觸孔，該第一源極透過該第一接觸孔連接至該第一摻雜區，且該第一汲極透過該第二接觸孔連接至該第二摻雜區。 The semiconductor device of claim 1, wherein the second metal oxide layer includes a first doped region, a second doped region, and a region between the first doped region and the second doped region. A first channel region, the interlayer dielectric layer includes a first contact hole overlapping the first doping region and a second contact hole overlapping the second doping region, the first source passes through the A contact hole is connected to the first doped region, and the first drain is connected to the second doped region through the second contact hole. 如請求項1所述的半導體裝置，其中該第一源極與該第一汲極延伸穿過該第二金屬氧化物層，並接觸該第一金屬氧化物層以及該第二金屬氧化物層的該界面。 The semiconductor device of claim 1, wherein the first source electrode and the first drain electrode extend through the second metal oxide layer and contact the first metal oxide layer and the second metal oxide layer of this interface. 如請求項1所述的半導體裝置，其中該第一閘極包括金屬層與P型半導體層的堆疊。 The semiconductor device of claim 1, wherein the first gate includes a stack of a metal layer and a P-type semiconductor layer. 如請求項1所述的半導體裝置，其中該第二薄膜電晶體更包括：一第二閘極，在該基板的該頂面的該法線方向上重疊於該第三金屬氧化物層，其中該閘介電層位於該第二閘極與該第三金屬氧化物層之間；以及一第二源極與一第二汲極，設置於該層間介電層上，且分別連接至該第三金屬氧化物層。 The semiconductor device of claim 1, wherein the second thin film transistor further includes: a second gate overlapping the third metal oxide layer in the normal direction of the top surface of the substrate, wherein The gate dielectric layer is located between the second gate electrode and the third metal oxide layer; and a second source electrode and a second drain electrode are disposed on the interlayer dielectric layer and are respectively connected to the third metal oxide layer. Three metal oxide layers. 如請求項5所述的半導體裝置，其中該第三金屬氧化物層包括一第三摻雜區、一第四摻雜區以及位於該第三摻雜區與該第四摻雜區之間的一第二通道區，該層間介電層包括重疊於該第三摻雜區的第三接觸孔以及重疊於該第四摻雜區的第四接觸 孔，該第二源極透過該第三接觸孔連接至該第三摻雜區，該第二汲極透過該第四接觸孔連接至該第四摻雜區。 The semiconductor device of claim 5, wherein the third metal oxide layer includes a third doped region, a fourth doped region, and a third doped region between the third doped region and the fourth doped region. a second channel region, the interlayer dielectric layer includes a third contact hole overlapping the third doped region and a fourth contact overlapping the fourth doped region hole, the second source is connected to the third doping region through the third contact hole, and the second drain is connected to the fourth doping region through the fourth contact hole. 如請求項5所述的半導體裝置，其中該第一閘極與該第二閘極的材料包括鎢、鉬、鉑、金或其組合。 The semiconductor device of claim 5, wherein the materials of the first gate and the second gate include tungsten, molybdenum, platinum, gold or a combination thereof. 如請求項2所述的半導體裝置，其中該第一金屬氧化物層包括一第五摻雜區以及一第六摻雜區，其中該第五摻雜區以及該第六摻雜區分別接觸該第一摻雜區的底部以及該第二摻雜區的底部。 The semiconductor device of claim 2, wherein the first metal oxide layer includes a fifth doped region and a sixth doped region, wherein the fifth doped region and the sixth doped region respectively contact the The bottom of the first doped region and the bottom of the second doped region. 如請求項8所述的半導體裝置，其中該第五摻雜區的厚度以及該第六摻雜區的厚度小於該第一金屬氧化物層的厚度。 The semiconductor device of claim 8, wherein the thickness of the fifth doped region and the thickness of the sixth doped region are smaller than the thickness of the first metal oxide layer. 如請求項1所述的半導體裝置，其中該第一金屬氧化物層、該第二金屬氧化物層以及該第三金屬氧化物層的材料包括銦鎵鋅氧化物、銦錫鋅氧化物、鋁鋅錫氧化物或銦鎢鋅氧化物。 The semiconductor device according to claim 1, wherein the materials of the first metal oxide layer, the second metal oxide layer and the third metal oxide layer include indium gallium zinc oxide, indium tin zinc oxide, aluminum Zinc tin oxide or indium tungsten zinc oxide. 如請求項1所述的半導體裝置，其中該第一金屬氧化物層的氧濃度小於該第三金屬氧化物層的氧濃度。 The semiconductor device of claim 1, wherein the oxygen concentration of the first metal oxide layer is less than the oxygen concentration of the third metal oxide layer. 一種半導體裝置的製造方法，包括：形成一第一薄膜電晶體於一基板之上，該第一薄膜電晶體包括堆疊的一第一金屬氧化物層以及一第二金屬氧化物層，其中該第一金屬氧化物層的氧濃度小於該第二金屬氧化物層的氧濃度，該第二金屬氧化物層的厚度小於該第一金屬氧化物層的厚度，其 中一二維電子氣位於該第一金屬氧化物層以及該第二金屬氧化物層之間的界面；以及形成一第二薄膜電晶體於該基板之上，其中該第二薄膜電晶體與該第一薄膜電晶體電性連接，該第二薄膜電晶體包括一第三金屬氧化物層，且該第二金屬氧化物層與該第三金屬氧化物層同時形成，其中形成該第一薄膜電晶體於該基板上以及形成該第二薄膜電晶體於該基板上的方法包括：形成一第一金屬氧化物圖案於該基板之上，其中該第一金屬氧化物圖案包括該第一金屬氧化物層；形成一第二金屬氧化物圖案於該第一金屬氧化物圖案以及該基板之上，其中該第二金屬氧化物圖案包括該第二金屬氧化物層以及該第三金屬氧化物層；形成一閘介電層於該第二金屬氧化物圖案上，且該閘介電層具有暴露出該第二金屬氧化物層的一開口；形成一第一閘極於該閘介電層上，其中該第一閘極通過該開口接觸該第二金屬氧化物層；形成一第二閘極，其中該第三金屬氧化物層重疊於該第二閘極；對該第二金屬氧化物層以及該第三金屬氧化物層執行一摻雜製程；形成一層間介電層於該閘介電層上；形成一第一源極、一第一汲極、一第二源極與一第二汲極於 該層間介電層上，其中該第一源極與該第一汲極分別連接至該第二金屬氧化物層，且該第二源極與該第二汲極分別連接至該第三金屬氧化物層。 A method of manufacturing a semiconductor device, including: forming a first thin film transistor on a substrate, the first thin film transistor including a stacked first metal oxide layer and a second metal oxide layer, wherein the first thin film transistor The oxygen concentration of a metal oxide layer is less than the oxygen concentration of the second metal oxide layer, and the thickness of the second metal oxide layer is less than the thickness of the first metal oxide layer. A two-dimensional electron gas is located at the interface between the first metal oxide layer and the second metal oxide layer; and forming a second thin film transistor on the substrate, wherein the second thin film transistor and the second thin film transistor are The first thin film transistor is electrically connected, the second thin film transistor includes a third metal oxide layer, and the second metal oxide layer and the third metal oxide layer are formed simultaneously, wherein the first thin film transistor is formed. A method of forming crystals on the substrate and forming the second thin film transistor on the substrate includes: forming a first metal oxide pattern on the substrate, wherein the first metal oxide pattern includes the first metal oxide layer; forming a second metal oxide pattern on the first metal oxide pattern and the substrate, wherein the second metal oxide pattern includes the second metal oxide layer and the third metal oxide layer; forming A gate dielectric layer is on the second metal oxide pattern, and the gate dielectric layer has an opening exposing the second metal oxide layer; a first gate is formed on the gate dielectric layer, wherein The first gate contacts the second metal oxide layer through the opening; a second gate is formed, wherein the third metal oxide layer overlaps the second gate; the second metal oxide layer and the A doping process is performed on the third metal oxide layer; an interlayer dielectric layer is formed on the gate dielectric layer; a first source electrode, a first drain electrode, a second source electrode and a second drain electrode are formed. at On the interlayer dielectric layer, the first source electrode and the first drain electrode are respectively connected to the second metal oxide layer, and the second source electrode and the second drain electrode are respectively connected to the third metal oxide layer. object layer. 如請求項12所述的半導體裝置的製造方法，其中執行該摻雜製程以於該第二金屬氧化物層中形成一第一摻雜區、一第二摻雜區以及位於該第一摻雜區與該第二摻雜區之間的一第一通道區，且於該第三金屬氧化物層中形成一第三摻雜區、一第四摻雜區以及位於該第三摻雜區與該第四摻雜區之間的一第二通道區。 The manufacturing method of a semiconductor device as claimed in claim 12, wherein the doping process is performed to form a first doped region, a second doped region and a second doped region located in the first doped layer in the second metal oxide layer. A first channel region between the third metal oxide layer and the second doped region, and a third doped region, a fourth doped region and a third doped region between the third doped region and the second doped region are formed in the third metal oxide layer. a second channel region between the fourth doping regions. 如請求項13所述的半導體裝置的製造方法，其中執行該摻雜製程以於該第一金屬氧化物層中形成一第五摻雜區以及一第六摻雜區。 The method of manufacturing a semiconductor device as claimed in claim 13, wherein the doping process is performed to form a fifth doped region and a sixth doped region in the first metal oxide layer. 如請求項12所述的半導體裝置的製造方法，其中以該第一閘極與該第二閘極為罩幕執行該摻雜製程。 The method of manufacturing a semiconductor device according to claim 12, wherein the doping process is performed using the first gate and the second gate as a mask. 如請求項12所述的半導體裝置的製造方法，更包括：執行一次或多次蝕刻製程以形成穿過該層間介電層以及該閘介電層的一第一接觸孔、一第二接觸孔、一第三接觸孔以及一第四接觸孔，其中該第一接觸孔以及該第二接觸孔重疊於該第二金屬氧化物層，且該第三接觸孔以及該第四接觸孔重疊於該第三金屬氧化物層；以及形成該第一源極、該第一汲極、該第二源極與該第二汲極於 該第一接觸孔、該第二接觸孔、該第三接觸孔以及該第四接觸孔中。 The method of manufacturing a semiconductor device according to claim 12, further comprising: performing one or more etching processes to form a first contact hole and a second contact hole through the interlayer dielectric layer and the gate dielectric layer. , a third contact hole and a fourth contact hole, wherein the first contact hole and the second contact hole overlap the second metal oxide layer, and the third contact hole and the fourth contact hole overlap the a third metal oxide layer; and forming the first source electrode, the first drain electrode, the second source electrode and the second drain electrode on in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole. 如請求項12所述的半導體裝置的製造方法，其中該第一源極以及該第一汲極延伸穿過該第二金屬氧化物層，且該第二源極以及該第二汲極延伸穿過該第三金屬氧化物層。The method of manufacturing a semiconductor device according to claim 12, wherein the first source electrode and the first drain electrode extend through the second metal oxide layer, and the second source electrode and the second drain electrode extend through through the third metal oxide layer.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100032668A1 (en) * 2008-08-08 2010-02-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20130033655A1 (en) * 2010-04-16 2013-02-07 Sharp Kabushiki Kaisha Thin film transistor substrate, method for producing same, and display device
TW201810439A (en) * 2009-06-30 2018-03-16 半導體能源研究所股份有限公司 Method for manufacturing semiconductor device
TW201809818A (en) * 2016-04-08 2018-03-16 群創光電股份有限公司 Display device
TW201843795A (en) * 2008-09-12 2018-12-16 日商半導體能源研究所股份有限公司 Semiconductor device and method for manufacturing the same

Family Cites Families (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371026A (en) * 1992-11-30 1994-12-06 Motorola Inc. Method for fabricating paired MOS transistors having a current-gain differential
JP2002076352A (en) * 2000-08-31 2002-03-15 Semiconductor Energy Lab Co Ltd Display device and its manufacturing method
JP4802364B2 (en) * 2000-12-07 2011-10-26 ソニー株式会社 Semiconductor layer doping method, thin film semiconductor device manufacturing method, and semiconductor layer resistance control method
US6724012B2 (en) * 2000-12-14 2004-04-20 Semiconductor Energy Laboratory Co., Ltd. Display matrix with pixels having sensor and light emitting portions
TW595005B (en) * 2003-08-04 2004-06-21 Au Optronics Corp Thin film transistor and pixel structure with the same
KR100719366B1 (en) * 2005-06-15 2007-05-17 삼성전자주식회사 Method of forming a semiconductor device having a trench device isolation layer
JP4220509B2 (en) * 2005-09-06 2009-02-04 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
JP5337380B2 (en) * 2007-01-26 2013-11-06 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
JP5294651B2 (en) * 2007-05-18 2013-09-18 キヤノン株式会社 Inverter manufacturing method and inverter
US8202773B2 (en) * 2008-08-29 2012-06-19 Texas Instruments Incorporated Engineered oxygen profile in metal gate electrode and nitrided high-k gate dielectrics structure for high performance PMOS devices
KR101529575B1 (en) * 2008-09-10 2015-06-29 삼성전자주식회사 Transistor, inverter comprising the same and methods of manufacturing transistor and inverter
EP2172977A1 (en) * 2008-10-03 2010-04-07 Semiconductor Energy Laboratory Co., Ltd. Display device
KR101016266B1 (en) * 2008-11-13 2011-02-25 한국과학기술원 Transparent memory for transparent electronics
US8367486B2 (en) * 2009-02-05 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Transistor and method for manufacturing the transistor
WO2011010543A1 (en) * 2009-07-18 2011-01-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
KR101772639B1 (en) * 2009-10-16 2017-08-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
JP5727204B2 (en) * 2009-12-11 2015-06-03 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
TWI434409B (en) * 2010-08-04 2014-04-11 Au Optronics Corp Organic electroluminescent display unit and method for fabricating the same
SG10201505586UA (en) * 2011-06-17 2015-08-28 Semiconductor Energy Lab Semiconductor device and method for manufacturing the same
US8952377B2 (en) * 2011-07-08 2015-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8952379B2 (en) * 2011-09-16 2015-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR20130053053A (en) * 2011-11-14 2013-05-23 삼성디스플레이 주식회사 Organic light emitting display apparatus and method of manufacturing organic light emitting display apparatus
KR101881895B1 (en) * 2011-11-30 2018-07-26 삼성디스플레이 주식회사 Thin-film transistor array substrate, organic light emitting display device comprising the same and method for manufacturing of the thin-film transistor array substrate
TWI478353B (en) * 2011-12-14 2015-03-21 E Ink Holdings Inc Thin film transistor and method for manufacturing the same
TWI613824B (en) * 2011-12-23 2018-02-01 半導體能源研究所股份有限公司 Semiconductor device
KR101884738B1 (en) * 2011-12-23 2018-08-31 삼성디스플레이 주식회사 Organic light emitting display apparatus and method of manufacturing organic light emitting display apparatus
US9006733B2 (en) * 2012-01-26 2015-04-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing thereof
TWI498220B (en) * 2012-10-31 2015-09-01 Au Optronics Corp Display panel and method for manufacturing the same
GB2511541B (en) * 2013-03-06 2015-01-28 Toshiba Res Europ Ltd Field effect transistor device
TWI802017B (en) * 2013-05-16 2023-05-11 日商半導體能源研究所股份有限公司 Semiconductor device
JP6374221B2 (en) * 2013-06-05 2018-08-15 株式会社半導体エネルギー研究所 Semiconductor device
KR102281300B1 (en) * 2013-09-11 2021-07-26 삼성디스플레이 주식회사 Thin film transistor, method of manufacturing the same, and display device including the same
CN104576381B (en) * 2013-10-14 2018-01-09 中国科学院微电子研究所 A kind of asymmetric ultra-thin SOI mos transistor structure and its manufacture method
TWI535034B (en) * 2014-01-29 2016-05-21 友達光電股份有限公司 Pixel structure and method of fabricating the same
US9929279B2 (en) * 2014-02-05 2018-03-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20170317217A1 (en) * 2014-11-11 2017-11-02 Sharp Kabushiki Kaisha Semiconductor device and method for manufacturing same
US9859391B2 (en) * 2015-10-27 2018-01-02 Nlt Technologies, Ltd. Thin film transistor, display device, and method for manufacturing thin film transistor
TWI579974B (en) * 2015-12-25 2017-04-21 國立交通大學 A resistive memory, resistive memory unit and thin-film transistor having composition of amorphous metal oxide
KR102640383B1 (en) * 2016-03-22 2024-02-27 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and display device including the same
US10468434B2 (en) * 2016-04-08 2019-11-05 Innolux Corporation Hybrid thin film transistor structure, display device, and method of making the same
CN106098784A (en) * 2016-06-13 2016-11-09 武汉华星光电技术有限公司 Coplanar type double grid electrode oxide thin film transistor and preparation method thereof
US20180122833A1 (en) * 2016-10-31 2018-05-03 LG Display Co. , Ltd. Thin film transistor substrate having bi-layer oxide semiconductor
WO2018211724A1 (en) * 2017-05-16 2018-11-22 住友電気工業株式会社 Oxide sintered body and production method therefor, sputtering target, oxide semiconductor film, and method for producing semiconductor device
KR102439133B1 (en) * 2017-09-05 2022-09-02 삼성디스플레이 주식회사 Thin film transistor substrate, method of manufacturing the same, and method of manufacturing a display device including the same
KR20190062695A (en) * 2017-11-29 2019-06-07 엘지디스플레이 주식회사 Thin film trnasistor, method for manufacturing the same and display device comprising the same
KR102482856B1 (en) * 2017-12-15 2022-12-28 엘지디스플레이 주식회사 Thin film trnasistor, method for manufacturing the same and display device comprising the same
CN108538789A (en) * 2018-03-30 2018-09-14 武汉华星光电技术有限公司 The preparation method of CMOS transistor, the preparation method of array substrate
TWI703735B (en) * 2018-06-26 2020-09-01 鴻海精密工業股份有限公司 Semiconductor substrate, array substrate, inverter circuit, and switch circuit
TWI666767B (en) * 2018-08-31 2019-07-21 友達光電股份有限公司 Active device substrate
JP6799123B2 (en) * 2018-09-19 2020-12-09 シャープ株式会社 Active matrix substrate and its manufacturing method
TWI685696B (en) * 2018-10-01 2020-02-21 友達光電股份有限公司 Active device substrate and manufacturing method thereof
KR102546780B1 (en) * 2018-12-28 2023-06-21 엘지디스플레이 주식회사 Thin film transistor comprising active layer having thickness difference and display apparatus comprising the same
KR20200093718A (en) * 2019-01-28 2020-08-06 삼성디스플레이 주식회사 Organic light emitting diode display device and method of manufacturing organic light emitting diode display device
CN109997230A (en) * 2019-01-29 2019-07-09 京东方科技集团股份有限公司 Pixel unit and its manufacturing method and double-sided OLED display device
US11342392B2 (en) * 2019-03-18 2022-05-24 Chengdu Boe Optoelectronics Technology Co., Ltd. Display panel and manufacturing method thereof
KR20210000605A (en) * 2019-06-25 2021-01-05 엘지디스플레이 주식회사 Display device including sensor
US11594533B2 (en) * 2019-06-27 2023-02-28 Intel Corporation Stacked trigate transistors with dielectric isolation between first and second semiconductor fins
TWI726348B (en) * 2019-07-03 2021-05-01 友達光電股份有限公司 Semiconductor substrate
TWI712844B (en) * 2019-07-03 2020-12-11 友達光電股份有限公司 Device substrate and manufacturing method thereof
TWI715344B (en) * 2019-12-10 2021-01-01 友達光電股份有限公司 Active device substrate and manufacturing method thereof
US11631671B2 (en) * 2019-12-31 2023-04-18 Tokyo Electron Limited 3D complementary metal oxide semiconductor (CMOS) device and method of forming the same
KR20210085942A (en) * 2019-12-31 2021-07-08 엘지디스플레이 주식회사 Thin film transistor and display apparatus comprising the same
US11663455B2 (en) * 2020-02-12 2023-05-30 Ememory Technology Inc. Resistive random-access memory cell and associated cell array structure
US11410999B2 (en) * 2020-02-21 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Boundary design for high-voltage integration on HKMG technology
KR20210117389A (en) * 2020-03-18 2021-09-29 삼성디스플레이 주식회사 Display device and method of fabricating for display device
KR20210142046A (en) * 2020-05-15 2021-11-24 삼성디스플레이 주식회사 Display device and method of fabricating the same
CN111710289A (en) * 2020-06-24 2020-09-25 天津中科新显科技有限公司 Pixel driving circuit and driving method of active light-emitting device
CN113257841B (en) * 2021-07-19 2021-11-16 深圳市柔宇科技股份有限公司 TFT substrate and preparation method thereof, display and electronic equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100032668A1 (en) * 2008-08-08 2010-02-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
TW201843795A (en) * 2008-09-12 2018-12-16 日商半導體能源研究所股份有限公司 Semiconductor device and method for manufacturing the same
TW201810439A (en) * 2009-06-30 2018-03-16 半導體能源研究所股份有限公司 Method for manufacturing semiconductor device
US20130033655A1 (en) * 2010-04-16 2013-02-07 Sharp Kabushiki Kaisha Thin film transistor substrate, method for producing same, and display device
TW201809818A (en) * 2016-04-08 2018-03-16 群創光電股份有限公司 Display device

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