TWI793027B - Inverter - Google Patents

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TWI793027B
TWI793027B TW111120041A TW111120041A TWI793027B TW I793027 B TWI793027 B TW I793027B TW 111120041 A TW111120041 A TW 111120041A TW 111120041 A TW111120041 A TW 111120041A TW I793027 B TWI793027 B TW I793027B
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metal oxide
region
source
drain
oxide layer
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TW202324674A (en
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江家維
范揚順
黃震鑠
陳衍豪
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友達光電股份有限公司
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Abstract

An inverter includes a substrate, a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first semiconductor structure, a first source and a first drain. The first semiconductor structure includes a first source region, a first drain region, and a first channel region. The thickness of the first source region is greater than that of the first channel region and the first drain region. The second thin film transistor includes a second gate, a second semiconductor structure, a second source and a second drain. The second semiconductor structure includes a second source region, a second drain region, and a second channel region. The thickness of the second channel region is greater than that of the second source region and the second drain region. The second drain is electrically connected to the first source.

Description

逆變器inverter

本發明是有關於一種逆變器。The invention relates to an inverter.

逆變器是一種能夠把直流電轉變為交流電的裝置。常見的逆變器包括N型逆變器以及P型逆變器，其中N型逆變器包括N型電晶體，而P型逆變器則包括P型電晶體。An inverter is a device that converts direct current into alternating current. Common inverters include N-type inverters and P-type inverters, wherein the N-type inverters include N-type transistors, and the P-type inverters include P-type transistors.

目前，矽半導體材料常被用於製作電源裝置中使用的電晶體。在逆變器的一些應用中，通常會包括一個或多個NMOS電晶體或PMOS電晶體。金屬氧化物半導體材料（例如銦鎵鋅氧化物）具有容易大面積製造與製程溫度低的優點，因此，近幾年許多廠商致力於以金屬氧化物半導體材料取代矽半導體材料作為電晶體的通道。然而，要如何將金屬氧化物半導體材料應用於逆變器中仍然是許多廠商致力於發展的課題。At present, silicon semiconductor material is often used to make transistors used in power supply devices. In some inverter applications, one or more NMOS transistors or PMOS transistors are usually included. Metal oxide semiconductor materials (such as indium gallium zinc oxide) have the advantages of easy large-scale manufacturing and low process temperature. Therefore, in recent years, many manufacturers have devoted themselves to replacing silicon semiconductor materials with metal oxide semiconductor materials as transistor channels. However, how to apply metal oxide semiconductor materials to inverters is still a topic that many manufacturers are working on.

本發明提供一種逆變器，具有面積小的優點。The invention provides an inverter with the advantage of small area.

本發明的至少一實施例提供一種逆變器。逆變器包括基板、第一薄膜電晶體以及第二薄膜電晶體。第一薄膜電晶體以及第二薄膜電晶體位於基板之上。第一薄膜電晶體包括第一閘極、第一半導體結構、第一源極以及第一汲極。第一半導體結構包括第一源極區、第一汲極區以及位於第一源極區與第一汲極區之間的第一通道區。第一閘極重疊於第一通道區。第一源極區的厚度大於第一通道區的厚度以及第一汲極區的厚度。第一源極電性連接第一源極區。第一汲極電性連接第一汲極區以及第一閘極。第二薄膜電晶體包括第二閘極、第二半導體結構、第二源極以及第二汲極。第二半導體結構包括第二源極區、第二汲極區以及位於第二源極區與第二汲極區之間的第二通道區。第二閘極重疊於第二通道區。第二通道區的厚度大於第二源極區的厚度以及第二汲極區的厚度。第二源極電性連接第二源極區。第二汲極電性連接第二汲極區以及第一源極。At least one embodiment of the present invention provides an inverter. The inverter includes a substrate, a first thin film transistor and a second thin film transistor. The first thin film transistor and the second thin film transistor are located on the substrate. The first TFT includes a first gate, a first semiconductor structure, a first source and a first drain. The first semiconductor structure includes a first source region, a first drain region, and a first channel region between the first source region and the first drain region. The first gate overlaps the first channel region. The thickness of the first source region is greater than the thickness of the first channel region and the thickness of the first drain region. The first source is electrically connected to the first source region. The first drain is electrically connected to the first drain region and the first gate. The second thin film transistor includes a second gate, a second semiconductor structure, a second source and a second drain. The second semiconductor structure includes a second source region, a second drain region, and a second channel region between the second source region and the second drain region. The second gate overlaps the second channel region. The thickness of the second channel region is greater than the thickness of the second source region and the thickness of the second drain region. The second source is electrically connected to the second source region. The second drain is electrically connected to the second drain region and the first source.

本發明的至少一實施例提供一種逆變器。逆變器包括基板、第一薄膜電晶體以及第二薄膜電晶體。第一薄膜電晶體以及第二薄膜電晶體位於基板之上。第一薄膜電晶體包括第一閘極、第一半導體結構、第一源極以及第一汲極。第一半導體結構包括第一源極區、第一汲極區以及位於第一源極區與第一汲極區之間的第一通道區。第一閘極重疊於第一通道區。第一通道區的厚度大於第一源極區的厚度以及第一汲極區的厚度。第一源極電性連接第一源極區以及第一閘極。第一汲極電性連接第一汲極區。第二薄膜電晶體包括第二閘極、第二半導體結構、第二源極以及第二汲極。第二半導體結構包括第二源極區、第二汲極區以及位於第二源極區與第二汲極區之間的第二通道區。第二閘極重疊於第二通道區，且第二源極區的厚度大於第二通道區的厚度以及第二汲極區的厚度。第二源極電性連接第二源極區。第二汲極電性連接第二汲極區以及第一源極。At least one embodiment of the present invention provides an inverter. The inverter includes a substrate, a first thin film transistor and a second thin film transistor. The first thin film transistor and the second thin film transistor are located on the substrate. The first TFT includes a first gate, a first semiconductor structure, a first source and a first drain. The first semiconductor structure includes a first source region, a first drain region, and a first channel region between the first source region and the first drain region. The first gate overlaps the first channel region. The thickness of the first channel region is greater than the thickness of the first source region and the thickness of the first drain region. The first source is electrically connected to the first source region and the first gate. The first drain is electrically connected to the first drain region. The second thin film transistor includes a second gate, a second semiconductor structure, a second source and a second drain. The second semiconductor structure includes a second source region, a second drain region, and a second channel region between the second source region and the second drain region. The second gate overlaps the second channel region, and the thickness of the second source region is greater than the thickness of the second channel region and the thickness of the second drain region. The second source is electrically connected to the second source region. The second drain is electrically connected to the second drain region and the first source.

圖1是依照本發明的一實施例的一種逆變器的剖面示意圖。FIG. 1 is a schematic cross-sectional view of an inverter according to an embodiment of the present invention.

請參考圖1，逆變器10A包括基板100、第一薄膜電晶體TL及第二薄膜電晶體TS。Please refer to FIG. 1 , the inverter 10A includes a substrate 100 , a first thin film transistor TL and a second thin film transistor TS.

基板100之材質可為玻璃、石英、有機聚合物或是不透光/反射材料（例如：導電材料、金屬、晶圓、陶瓷或其他可適用的材料）或是其他可適用的材料。若使用導電材料或金屬時，則在基板100上覆蓋一層絕緣層（未繪示），以避免短路問題。在一些實施例中，基板100為軟性基板，且基板100的材料例如為聚乙烯對苯二甲酸酯（polyethylene terephthalate, PET）、聚二甲酸乙二醇酯（polyethylene naphthalate, PEN）、聚酯（polyester, PES）、聚甲基丙烯酸甲酯（polymethylmethacrylate, PMMA）、聚碳酸酯（polycarbonate, PC）、聚醯亞胺(polyimide, PI）或金屬軟板（Metal Foil）或其他可撓性材質。The material of the substrate 100 can be glass, quartz, organic polymer or opaque/reflective material (eg conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene glycol ester (polyethylene naphthalate, PEN), polyester (polyester, PES), polymethylmethacrylate (polymethylmethacrylate, PMMA), polycarbonate (polycarbonate, PC), polyimide (polyimide, PI) or metal soft board (Metal Foil) or other flexible materials .

緩衝層110位於基板100上，緩衝層110為單層或多層結構，且緩衝層110的材料可以包括氧化矽、氮氧化矽或其他合適的材料或上述材料的堆疊層。The buffer layer 110 is located on the substrate 100. The buffer layer 110 has a single-layer or multi-layer structure, and the material of the buffer layer 110 may include silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials.

第一薄膜電晶體TL以及第二薄膜電晶體TS位於基板100之上。在本實施例中，第一薄膜電晶體TL以及第二薄膜電晶體TS位於緩衝層110上。The first thin film transistor TL and the second thin film transistor TS are located on the substrate 100 . In this embodiment, the first thin film transistor TL and the second thin film transistor TS are located on the buffer layer 110 .

第一薄膜電晶體TL包括第一閘極G1、第一半導體結構SM1、第一源極S1以及第一汲極D1。第二薄膜電晶體TS包括第二閘極G2、第二半導體結構SM2、第二源極S2以及第二汲極D2。The first thin film transistor TL includes a first gate G1 , a first semiconductor structure SM1 , a first source S1 and a first drain D1 . The second thin film transistor TS includes a second gate G2 , a second semiconductor structure SM2 , a second source S2 and a second drain D2 .

第一半導體結構SM1位於緩衝層110上。第一半導體結構SM1包括第一源極區sr1、第一汲極區dr1以及位於第一源極區sr1與第一汲極區dr1之間的第一通道區ch1。第一源極區sr1的厚度（例如為厚度t2加上厚度t1）大於第一通道區ch1的厚度（例如為厚度t1）以及第一汲極區dr1的厚度（例如為厚度t1）。The first semiconductor structure SM1 is located on the buffer layer 110 . The first semiconductor structure SM1 includes a first source region sr1 , a first drain region dr1 and a first channel region ch1 between the first source region sr1 and the first drain region dr1 . The thickness of the first source region sr1 (for example, the thickness t2 plus the thickness t1 ) is greater than the thickness of the first channel region ch1 (for example, the thickness t1 ) and the thickness of the first drain region dr1 (for example, the thickness t1 ).

第一半導體結構SM1包括第一金屬氧化物層OS1A以及第一金屬氧化物圖案OS2A的堆疊。第一金屬氧化物層OS1A設置於第一源極區sr1、第一汲極區dr1以及第一通道區ch1中。第一金屬氧化物圖案OS2A設置於第一源極區sr1中。第一金屬氧化物圖案OS2A未延伸至第一汲極區dr1以及第一通道區ch1。在本實施例中，第一金屬氧化物層OS1A包覆第一金屬氧化物圖案OS2A的側壁與頂面，且第一金屬氧化物圖案OS2A位於第一金屬氧化物層OS1A與基板100之間。The first semiconductor structure SM1 includes a first metal oxide layer OS1A and a stack of first metal oxide patterns OS2A. The first metal oxide layer OS1A is disposed in the first source region sr1 , the first drain region dr1 and the first channel region ch1 . The first metal oxide pattern OS2A is disposed in the first source region sr1. The first metal oxide pattern OS2A does not extend to the first drain region dr1 and the first channel region ch1 . In this embodiment, the first metal oxide layer OS1A covers sidewalls and top surfaces of the first metal oxide pattern OS2A, and the first metal oxide pattern OS2A is located between the first metal oxide layer OS1A and the substrate 100 .

第二半導體結構SM2包括第二源極區sr2、第二汲極區dr2以及位於第二源極區sr2與第二汲極區dr2之間的第二通道區ch2。第二通道區ch2的厚度（例如為厚度t2加上厚度t1）大於第二源極區sr2的厚度（例如為厚度t1）以及第二汲極區dr2的厚度（例如為厚度t1）。The second semiconductor structure SM2 includes a second source region sr2, a second drain region dr2, and a second channel region ch2 between the second source region sr2 and the second drain region dr2. The thickness of the second channel region ch2 (for example, the thickness t2 plus the thickness t1 ) is greater than the thickness of the second source region sr2 (for example, the thickness t1 ) and the thickness of the second drain region dr2 (for example, the thickness t1 ).

第二半導體結構SM2包括第二金屬氧化物層OS1B以及第二金屬氧化物圖案OS2B的堆疊。第二金屬氧化物層OS1B設置於第二源極區sr2、第二汲極區dr2以及第二通道區ch2中。第二金屬氧化物圖案OS2B設置於第二通道區ch2中。第二金屬氧化物圖案OS2B未延伸至第二源極區sr2以及第二汲極區dr2。在本實施例中，第二金屬氧化物層OS1B包覆第二金屬氧化物圖案OS2B的側壁與頂面，且第二金屬氧化物圖案OS2B位於第二金屬氧化物層OS1B與基板100之間。The second semiconductor structure SM2 includes a stack of a second metal oxide layer OS1B and a second metal oxide pattern OS2B. The second metal oxide layer OS1B is disposed in the second source region sr2 , the second drain region dr2 and the second channel region ch2 . The second metal oxide pattern OS2B is disposed in the second channel region ch2. The second metal oxide pattern OS2B does not extend to the second source region sr2 and the second drain region dr2. In this embodiment, the second metal oxide layer OS1B covers sidewalls and top surfaces of the second metal oxide pattern OS2B, and the second metal oxide pattern OS2B is located between the second metal oxide layer OS1B and the substrate 100 .

在一些實施例中，第一金屬氧化物圖案OS2A與第二金屬氧化物圖案OS2B屬於相同膜層。換句話說，第一金屬氧化物圖案OS2A與第二金屬氧化物圖案OS2B是於同一次圖案化製程中所定義出來的。第一金屬氧化物圖案OS2A與第二金屬氧化物圖案OS2B包括相同的厚度與相同的材料。在一些實施例中，第一金屬氧化物圖案OS2A與第二金屬氧化物圖案OS2B的厚度t2為5奈米至25奈米。在一些實施例中，第一金屬氧化物圖案OS2A與第二金屬氧化物圖案OS2B的材料包括銦鎢鋅氧化物、銦鎵鋅氧化物或其他金屬氧化物。在一些實施例中，第一金屬氧化物圖案OS2A經摻雜而具有低於第二金屬氧化物圖案OS2B的電阻率。In some embodiments, the first metal oxide pattern OS2A and the second metal oxide pattern OS2B belong to the same film layer. In other words, the first metal oxide pattern OS2A and the second metal oxide pattern OS2B are defined in the same patterning process. The first metal oxide pattern OS2A and the second metal oxide pattern OS2B include the same thickness and the same material. In some embodiments, the thickness t2 of the first metal oxide pattern OS2A and the second metal oxide pattern OS2B is 5 nm to 25 nm. In some embodiments, the material of the first metal oxide pattern OS2A and the second metal oxide pattern OS2B includes indium tungsten zinc oxide, indium gallium zinc oxide or other metal oxides. In some embodiments, the first metal oxide pattern OS2A is doped to have a lower resistivity than the second metal oxide pattern OS2B.

在一些實施例中，第一金屬氧化物層OS1A與第二金屬氧化物層OS1B屬於相同膜層。換句話說，第一金屬氧化物層OS1A與第二金屬氧化物層OS1B是於同一次圖案化製程中所定義出來的。第一金屬氧化物層OS1A與第二金屬氧化物層OS1B包括相同的厚度與相同的材料。在一些實施例中，第一金屬氧化物層OS1A與第二金屬氧化物層OS1B的厚度t1為15奈米至25奈米。在一些實施例中，第一金屬氧化物層OS1A與第二金屬氧化物層OS1B的材料包括銦鎵鋅氧化物或其他金屬氧化物。在一些實施例中，在第一金屬氧化物層OS1A中，第一汲極區dr1以及第一源極區dr1經摻雜而具有低於第一通道區ch1的電阻率。類似地，在第二金屬氧化物層OS1B中，第二汲極區dr2以及第二源極區dr2經摻雜而具有低於第二通道區ch2的電阻率。另外，在第二通道區ch2中，第二金屬氧化物圖案OS2B的載子遷移率大於或等於第二金屬氧化物層OS1B的載子遷移率。In some embodiments, the first metal oxide layer OS1A and the second metal oxide layer OS1B belong to the same film layer. In other words, the first metal oxide layer OS1A and the second metal oxide layer OS1B are defined in the same patterning process. The first metal oxide layer OS1A and the second metal oxide layer OS1B include the same thickness and the same material. In some embodiments, the thickness t1 of the first metal oxide layer OS1A and the second metal oxide layer OS1B is 15 nm to 25 nm. In some embodiments, materials of the first metal oxide layer OS1A and the second metal oxide layer OS1B include InGaZnO or other metal oxides. In some embodiments, in the first metal oxide layer OS1A, the first drain region dr1 and the first source region dr1 are doped to have a lower resistivity than the first channel region ch1 . Similarly, in the second metal oxide layer OS1B, the second drain region dr2 and the second source region dr2 are doped to have a lower resistivity than the second channel region ch2 . In addition, in the second channel region ch2, the carrier mobility of the second metal oxide pattern OS2B is greater than or equal to the carrier mobility of the second metal oxide layer OS1B.

基於上述，藉由於第二通道區ch2中設置第二金屬氧化物圖案OS2B，可以降低第二薄膜電晶體TS的等效阻值R S，因此，不需要增加第一薄膜電晶體TL的第一通道區ch1的長度就可以提升第一薄膜電晶體TL的等效阻值R L與第二薄膜電晶體TS的等效阻值R S的比值（R L/R S），使逆變器10A具有面積小的優點。 Based on the above, by disposing the second metal oxide pattern OS2B in the second channel region ch2, the equivalent resistance value R S of the second thin film transistor TS can be reduced. Therefore, there is no need to increase the first resistance of the first thin film transistor TL. The length of the channel region ch1 can increase the ratio (R L / RS ) of the equivalent resistance value R L of the first thin film transistor TL to the equivalent resistance value R S of the second thin film transistor TS, so that the inverter 10A It has the advantage of small area.

閘介電層120位於第一半導體結構SM1與第二半導體結構SM2之上。在本實施例中，閘介電層120直接形成於第一半導體結構SM1與第二半導體結構SM2上。在一些實施例中，閘介電層120的材料包括氧化矽、氮氧化矽、氧化鉿或其他合適的材料或上述材料的堆疊層。The gate dielectric layer 120 is located on the first semiconductor structure SM1 and the second semiconductor structure SM2. In this embodiment, the gate dielectric layer 120 is directly formed on the first semiconductor structure SM1 and the second semiconductor structure SM2. In some embodiments, the material of the gate dielectric layer 120 includes silicon oxide, silicon oxynitride, hafnium oxide or other suitable materials or stacked layers of the above materials.

第一閘極G1與第二閘極G2位於閘介電層120之上。在本實施例中，第一閘極G1與第二閘極G2直接形成於閘介電層120上。第一閘極G1在基板100的上表面的法線方向ND上重疊於第一通道區ch1。第二閘極G2在基板100的上表面的法線方向ND上重疊於第二通道區ch2。在一些實施例中，第一金屬氧化物圖案OS2A的側壁與第一閘極G1的側壁之間的水平距離HD1小於300奈米，且第二金屬氧化物圖案OS2B的側壁與第二閘極G2的側壁之間的水平距離HD2小於300奈米。The first gate G1 and the second gate G2 are located on the gate dielectric layer 120 . In this embodiment, the first gate G1 and the second gate G2 are directly formed on the gate dielectric layer 120 . The first gate G1 overlaps the first channel region ch1 in the normal direction ND of the upper surface of the substrate 100 . The second gate G2 overlaps the second channel region ch2 in the normal direction ND of the upper surface of the substrate 100 . In some embodiments, the horizontal distance HD1 between the sidewall of the first metal oxide pattern OS2A and the sidewall of the first gate G1 is less than 300 nm, and the sidewall of the second metal oxide pattern OS2B is closer to the second gate G2. The horizontal distance HD2 between the sidewalls is less than 300 nm.

在一些實施例中，第一閘極G1與第二閘極G2的材料可包括金屬，例如鉻（Cr）、金（Au）、銀（Ag）、銅（Cu）、錫（Sn）、鉛（Pb）、鉿（Hf）、鎢（W）、鉬（Mo）、釹（Nd）、鈦（Ti）、鉭（Ta）、鋁（Al）、鋅（Zn）或上述金屬的任意組合之合金或上述金屬及/或合金之疊層，但本發明不以此為限。第一閘極G1與第二閘極G2也可以使用其他導電材料，例如：金屬的氮化物、金屬的氧化物、金屬的氮氧化物、金屬與其它導電材料的堆疊層或是其他具有導電性質之材料。In some embodiments, the materials of the first gate G1 and the second gate G2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn) or any combination of the above metals Alloys or stacks of the above metals and/or alloys, but the present invention is not limited thereto. The first gate G1 and the second gate G2 can also use other conductive materials, such as: metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials, or other conductive materials. The material.

層間介電層130位於第一閘極G1、第二閘極G2以及閘介電層120之上。在一些實施例中，層間介電層130的材料包括氮化矽、氧化矽、氮氧化矽、氧化鉿或其他合適的材料或上述材料的堆疊層。The interlayer dielectric layer 130 is located on the first gate G1 , the second gate G2 and the gate dielectric layer 120 . In some embodiments, the material of the interlayer dielectric layer 130 includes silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide or other suitable materials or stacked layers of the above materials.

層間介電層130具有第一接觸孔V1、第二接觸孔V2、第三接觸孔V3、第四接觸孔V4、第五接觸孔V5以及第六接觸孔V6。在本實施例中，第一接觸孔V1、第三接觸孔V3、第四接觸孔V4以及第六接觸孔V6貫穿層間介電層130以及閘介電層120，而第二接觸孔V2以及第五接觸孔V5貫穿層間介電層130。The interlayer dielectric layer 130 has a first contact hole V1 , a second contact hole V2 , a third contact hole V3 , a fourth contact hole V4 , a fifth contact hole V5 and a sixth contact hole V6 . In this embodiment, the first contact hole V1, the third contact hole V3, the fourth contact hole V4 and the sixth contact hole V6 penetrate the interlayer dielectric layer 130 and the gate dielectric layer 120, while the second contact hole V2 and the Five contact holes V5 penetrate through the interlayer dielectric layer 130 .

第一源極S1、第一汲極D1、第二源極S2、第二汲極D2以及訊號線L位於層間介電層130上。第一汲極D1填入第一接觸孔V1以電性連接第一汲極區dr1，且第一汲極D1填入第二接觸孔V2以電性連接該第一閘極G1。第一源極S1填入第三接觸孔V3以電性連接第一源極區sr1。第二汲極D2填入第四接觸孔V4以電性連接第二汲極區dr2，且第二汲極D2電性連接第一源極S1。訊號線L填入第五接觸孔V5以電性連接第二閘極G2。第二源極S2填入第六接觸孔V6以電性連接第二源極區sr2。The first source S1 , the first drain D1 , the second source S2 , the second drain D2 and the signal line L are located on the interlayer dielectric layer 130 . The first drain D1 fills in the first contact hole V1 to electrically connect to the first drain region dr1 , and the first drain D1 fills in the second contact hole V2 to electrically connect to the first gate G1 . The first source S1 fills the third contact hole V3 to be electrically connected to the first source region sr1 . The second drain D2 fills the fourth contact hole V4 to be electrically connected to the second drain region dr2, and the second drain D2 is electrically connected to the first source S1. The signal line L is filled into the fifth contact hole V5 to be electrically connected to the second gate G2. The second source S2 fills into the sixth contact hole V6 to be electrically connected to the second source region sr2.

在本實施例中，由於第一金屬氧化物圖案OS2A的設置，第一源極區sr1具有較低的電阻率，藉此減少第一源極S1與第一源極區sr1之間的阻抗。另外，藉由於第一源極區sr1中設置第一金屬氧化物圖案OS2A，第一源極區sr1的厚度大於第一通道區ch1的厚度，可以分散第一通道區ch1與第一源極S1之間的電場，藉此降低第一源極S1與第一金屬氧化物圖案OS2A之接觸阻抗。此外，藉由於第二通道區ch2中設置第二金屬氧化物圖案OS2B，第二通道區ch1的厚度大於第二汲極區dr2的厚度，可以分散第二汲極D2與第二通道區ch2之間的電場，藉此減少熱載子效應。In this embodiment, due to the arrangement of the first metal oxide pattern OS2A, the first source region sr1 has a lower resistivity, thereby reducing the resistance between the first source S1 and the first source region sr1 . In addition, by disposing the first metal oxide pattern OS2A in the first source region sr1, the thickness of the first source region sr1 is greater than the thickness of the first channel region ch1, and the first channel region ch1 and the first source S1 can be dispersed. The electric field between the first source electrode S1 and the first metal oxide pattern OS2A is thereby reduced. In addition, by disposing the second metal oxide pattern OS2B in the second channel region ch2, the thickness of the second channel region ch1 is greater than the thickness of the second drain region dr2, and the difference between the second drain electrode D2 and the second channel region ch2 can be dispersed. The electric field between them, thereby reducing the hot carrier effect.

圖2A至圖2D是圖1的逆變器的製造方法的剖面示意圖。2A to 2D are schematic cross-sectional views of the manufacturing method of the inverter shown in FIG. 1 .

請參考圖2A，形成第一金屬氧化物圖案OS2A’與第二金屬氧化物圖案OS2B於基板100之上。在一些實施例中，形成第一金屬氧化物圖案OS2A’與第二金屬氧化物圖案OS2B的方法包括微影蝕刻製程。第一金屬氧化物圖案OS2A’與第二金屬氧化物圖案OS2B屬於相同膜層，且第一金屬氧化物圖案OS2A’與第二金屬氧化物圖案OS2B包括相同的材料與相同的厚度。Referring to FIG. 2A , a first metal oxide pattern OS2A' and a second metal oxide pattern OS2B are formed on a substrate 100 . In some embodiments, the method of forming the first metal oxide pattern OS2A' and the second metal oxide pattern OS2B includes a lithographic etching process. The first metal oxide pattern OS2A' and the second metal oxide pattern OS2B belong to the same film layer, and the first metal oxide pattern OS2A' and the second metal oxide pattern OS2B include the same material and the same thickness.

請參考圖2B，形成第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’於第一金屬氧化物圖案OS2A’、第二金屬氧化物圖案OS2B以及基板100之上，其中第一金屬氧化物層OS1A’覆蓋第一金屬氧化物圖案OS2A’，且第二金屬氧化物層OS1B’覆蓋第二金屬氧化物圖案OS2B。在一些實施例中，形成第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’的方法包括微影蝕刻製程。2B, a first metal oxide layer OS1A' and a second metal oxide layer OS1B' are formed on the first metal oxide pattern OS2A', the second metal oxide pattern OS2B and the substrate 100, wherein the first metal The oxide layer OS1A' covers the first metal oxide pattern OS2A', and the second metal oxide layer OS1B' covers the second metal oxide pattern OS2B. In some embodiments, the method of forming the first metal oxide layer OS1A' and the second metal oxide layer OS1B' includes a lithographic etching process.

舉例來說，形成毯覆於第一金屬氧化物圖案OS2A’、第二金屬氧化物圖案OS2B以及緩衝層110上的金屬氧化物材料層（未繪出）；於金屬氧化物材料層表面形成圖案化的光阻（未繪出）；以圖案化的光阻為遮罩蝕刻金屬氧化物材料層，以形成第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’；移除圖案化的光阻。第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’屬於相同膜層，且第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’包括相同的材料與相同的厚度。For example, forming a metal oxide material layer (not shown) covering the first metal oxide pattern OS2A', the second metal oxide pattern OS2B and the buffer layer 110; forming a pattern on the surface of the metal oxide material layer patterned photoresist (not shown); etch the metal oxide material layer using the patterned photoresist as a mask to form the first metal oxide layer OS1A' and the second metal oxide layer OS1B'; remove the patterned photoresist. The first metal oxide layer OS1A' and the second metal oxide layer OS1B' belong to the same film layer, and the first metal oxide layer OS1A' and the second metal oxide layer OS1B' include the same material and the same thickness.

在本實施例中，由於第一金屬氧化物層OS1A’覆蓋第一金屬氧化物圖案OS2A’，且第二金屬氧化物層OS1B’覆蓋第二金屬氧化物圖案OS2B，蝕刻金屬氧化物材料層時所用之蝕刻液不會對第一金屬氧化物圖案OS2A’以及第二金屬氧化物圖案OS2B的表面造成損傷，藉此提升半導體結構的良率。In this embodiment, since the first metal oxide layer OS1A' covers the first metal oxide pattern OS2A', and the second metal oxide layer OS1B' covers the second metal oxide pattern OS2B, when etching the metal oxide material layer The used etchant will not damage the surfaces of the first metal oxide pattern OS2A′ and the second metal oxide pattern OS2B, thereby improving the yield of the semiconductor structure.

請參考圖2B與2C，形成閘介電層120於第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’上。形成第一閘極G1與第二閘極G2於閘介電層120上。以第一閘極G1與第二閘極G2為罩幕，執行摻雜製程P，以形成包括第一源極區sr1、第一汲極區dr1以及第一通道區ch1的第一半導體結構SM1以及包括第二源極區sr2、第二汲極區dr2以及第二通道區ch2的第二半導體結構SM2。在本實施例中，由於第一金屬氧化物圖案OS2A未被閘極遮蔽，第一金屬氧化物圖案OS2A經摻雜而具有低於第二金屬氧化物圖案OS2B的電阻率。在一些實施例中，摻雜製程P例如為氫電漿摻雜或其他合適的製程。2B and 2C, a gate dielectric layer 120 is formed on the first metal oxide layer OS1A' and the second metal oxide layer OS1B'. A first gate G1 and a second gate G2 are formed on the gate dielectric layer 120 . Using the first gate G1 and the second gate G2 as a mask, perform a doping process P to form a first semiconductor structure SM1 including a first source region sr1, a first drain region dr1, and a first channel region ch1 And the second semiconductor structure SM2 including the second source region sr2 , the second drain region dr2 and the second channel region ch2 . In this embodiment, since the first metal oxide pattern OS2A is not shielded by the gate, the first metal oxide pattern OS2A is doped to have a lower resistivity than the second metal oxide pattern OS2B. In some embodiments, the doping process P is, for example, hydrogen plasma doping or other suitable processes.

請參考圖2D，形成層間介電層130於第一閘極G1、第二閘極G2以及閘介電層120之上。於層間介電層130中形成第一接觸孔V1至第六接觸孔V6。Referring to FIG. 2D , an interlayer dielectric layer 130 is formed on the first gate G1 , the second gate G2 and the gate dielectric layer 120 . A first contact hole V1 to a sixth contact hole V6 are formed in the interlayer dielectric layer 130 .

最後請回到圖1，形成第一源極S1、第一汲極D1、第二源極S2、第二汲極D2以及訊號線L位於層間介電層130上。在本實施例中，第一源極S1以及第一汲極D1連接至第一金屬氧化物層OS1A，而第二源極S2以及第二汲極D2連接至第二金屬氧化物層OS1B。至此，逆變器10A大致完成。Finally, please return to FIG. 1 , the first source S1 , the first drain D1 , the second source S2 , the second drain D2 and the signal line L are formed on the interlayer dielectric layer 130 . In this embodiment, the first source S1 and the first drain D1 are connected to the first metal oxide layer OS1A, and the second source S2 and the second drain D2 are connected to the second metal oxide layer OS1B. So far, the inverter 10A is almost completed.

圖3是依照本發明的一實施例的一種逆變器的剖面示意圖。在此必須說明的是，圖3的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 3 is a schematic cross-sectional view of an inverter according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 3 uses the component numbers and parts of the content in the embodiment in FIG. 1 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

圖3的逆變器10B與圖1的半導體裝置10A的主要差異在於：逆變器10B的第一金屬氧化物層OS1A位於第一金屬氧化物圖案OS2A與基板100之間，且第二金屬氧化物層OS1B位於第二金屬氧化物圖案OS2B與基板100之間。The main difference between the inverter 10B of FIG. 3 and the semiconductor device 10A of FIG. 1 is that the first metal oxide layer OS1A of the inverter 10B is located between the first metal oxide pattern OS2A and the substrate 100, and the second metal oxide layer OS2A The substance layer OS1B is located between the second metal oxide pattern OS2B and the substrate 100 .

圖4A至圖4D是圖3的逆變器的製造方法的剖面示意圖。4A to 4D are schematic cross-sectional views of the manufacturing method of the inverter shown in FIG. 3 .

請參考圖4A，形成第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’於基板100之上。在一些實施例中，形成第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’的方法包括微影蝕刻製程。第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’屬於相同膜層，且第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’包括相同的材料與相同的厚度。Referring to FIG. 4A , a first metal oxide layer OS1A' and a second metal oxide layer OS1B' are formed on the substrate 100. Referring to FIG. In some embodiments, the method of forming the first metal oxide layer OS1A' and the second metal oxide layer OS1B' includes a lithographic etching process. The first metal oxide layer OS1A' and the second metal oxide layer OS1B' belong to the same film layer, and the first metal oxide layer OS1A' and the second metal oxide layer OS1B' include the same material and the same thickness.

請參考圖2B，形成第一金屬氧化物圖案OS2A’與第二金屬氧化物圖案OS2B於第一金屬氧化物層OS1A’與第二金屬氧化物層OS1B’之上，其中第一金屬氧化物圖案OS2A’暴露出第一金屬氧化物層OS1A’的部分上表面，且第二金屬氧化物圖案OS2B暴露出第二金屬氧化物層OS1B’的部分上表面。在一些實施例中，形成第一金屬氧化物圖案OS2A’與第二金屬氧化物圖案OS2B的方法包括微影蝕刻製程。2B, a first metal oxide pattern OS2A' and a second metal oxide pattern OS2B are formed on the first metal oxide layer OS1A' and the second metal oxide layer OS1B', wherein the first metal oxide pattern OS2A' exposes a portion of the upper surface of the first metal oxide layer OS1A', and the second metal oxide pattern OS2B exposes a portion of the upper surface of the second metal oxide layer OS1B'. In some embodiments, the method of forming the first metal oxide pattern OS2A' and the second metal oxide pattern OS2B includes a lithographic etching process.

舉例來說，形成毯覆於第一金屬氧化物層OS1A’、第二金屬氧化物層OS1B’以及緩衝層110上的金屬氧化物材料層（未繪出）；於金屬氧化物材料層表面形成圖案化的光阻（未繪出）；以圖案化的光阻為遮罩蝕刻金屬氧化物材料層，以形成第一金屬氧化物圖案OS2A’與第二金屬氧化物圖案OS2B；移除圖案化的光阻。第一金屬氧化物圖案OS2A’與第二金屬氧化物圖案OS2B屬於相同膜層，且第一金屬氧化物圖案OS2A’與第二金屬氧化物圖案OS2B包括相同的材料與相同的厚度。For example, a metal oxide material layer (not shown) is formed blanketing the first metal oxide layer OS1A', the second metal oxide layer OS1B' and the buffer layer 110; patterned photoresist (not shown); etching the metal oxide material layer using the patterned photoresist as a mask to form a first metal oxide pattern OS2A' and a second metal oxide pattern OS2B; remove the patterning photoresist. The first metal oxide pattern OS2A' and the second metal oxide pattern OS2B belong to the same film layer, and the first metal oxide pattern OS2A' and the second metal oxide pattern OS2B include the same material and the same thickness.

請參考圖4B與4C，形成閘介電層120於第一金屬氧化物層OS1A’、第二金屬氧化物層OS1B’、第一金屬氧化物圖案OS2A’與第二金屬氧化物圖案OS2B上。形成第一閘極G1與第二閘極G2於閘介電層120上。以第一閘極G1與第二閘極G2為罩幕，執行摻雜製程P，以形成包括第一源極區sr1、第一汲極區dr1以及第一通道區ch1的第一半導體結構SM1以及包括第二源極區sr2、第二汲極區dr2以及第二通道區ch2的第二半導體結構SM2。在本實施例中，由於第一金屬氧化物圖案OS2A未被閘極遮蔽，第一金屬氧化物圖案OS2A經摻雜而具有低於第二金屬氧化物圖案OS2B的電阻率。在一些實施例中，摻雜製程P例如為氫電漿摻雜或其他合適的製程。4B and 4C, the gate dielectric layer 120 is formed on the first metal oxide layer OS1A', the second metal oxide layer OS1B', the first metal oxide pattern OS2A' and the second metal oxide pattern OS2B. A first gate G1 and a second gate G2 are formed on the gate dielectric layer 120 . Using the first gate G1 and the second gate G2 as a mask, perform a doping process P to form a first semiconductor structure SM1 including a first source region sr1, a first drain region dr1, and a first channel region ch1 And the second semiconductor structure SM2 including the second source region sr2 , the second drain region dr2 and the second channel region ch2 . In this embodiment, since the first metal oxide pattern OS2A is not shielded by the gate, the first metal oxide pattern OS2A is doped to have a lower resistivity than the second metal oxide pattern OS2B. In some embodiments, the doping process P is, for example, hydrogen plasma doping or other suitable processes.

請參考圖4D，形成層間介電層130於第一閘極G1、第二閘極G2以及閘介電層120之上。於層間介電層130中形成第一接觸孔V1至第六接觸孔V6。Referring to FIG. 4D , an interlayer dielectric layer 130 is formed on the first gate G1 , the second gate G2 and the gate dielectric layer 120 . A first contact hole V1 to a sixth contact hole V6 are formed in the interlayer dielectric layer 130 .

最後請回到圖3，形成第一源極S1、第一汲極D1、第二源極S2、第二汲極D2以及訊號線L位於層間介電層130上。在本實施例中，第一源極S1連接至第一金屬氧化物圖案OS2A，第一汲極D1連接至第一金屬氧化物層OS1A，且第二源極S2以及第二汲極D2連接至第二金屬氧化物層OS1B。至此，逆變器10B大致完成。Finally, please return to FIG. 3 , the first source S1 , the first drain D1 , the second source S2 , the second drain D2 and the signal line L are formed on the interlayer dielectric layer 130 . In this embodiment, the first source S1 is connected to the first metal oxide pattern OS2A, the first drain D1 is connected to the first metal oxide layer OS1A, and the second source S2 and the second drain D2 are connected to The second metal oxide layer OS1B. So far, the inverter 10B is substantially completed.

圖5是依照本發明的一實施例的一種逆變器的剖面示意圖。在此必須說明的是，圖5的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 5 is a schematic cross-sectional view of an inverter according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 5 follows the component numbers and part of the content of the embodiment in FIG. 1 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

圖5的逆變器10C與圖1的半導體裝置10A的主要差異在於：在逆變器10C中，第一通道區ch1的厚度（例如為厚度t2加上厚度t1）大於第一源極區sr1的厚度（例如為厚度t1）以及第一汲極區dr1的厚度（例如為厚度t1），第二源極區sr2的厚度（例如為厚度t2加上厚度t1）大於第二通道區ch2的厚度（例如為厚度t1）以及第二汲極區dr2的厚度（例如為厚度t1），且第一源極S1電性連接第一閘極G1。The main difference between the inverter 10C in FIG. 5 and the semiconductor device 10A in FIG. 1 is that in the inverter 10C, the thickness of the first channel region ch1 (for example, the thickness t2 plus the thickness t1 ) is greater than that of the first source region sr1 The thickness (for example, thickness t1) and the thickness of the first drain region dr1 (for example, thickness t1), the thickness of the second source region sr2 (for example, thickness t2 plus thickness t1) is greater than the thickness of the second channel region ch2 (eg, thickness t1 ) and the thickness of the second drain region dr2 (eg, thickness t1 ), and the first source S1 is electrically connected to the first gate G1 .

請參考圖5，第一半導體結構SM1包括第一金屬氧化物層OS1A以及第一金屬氧化物圖案OS2A的堆疊。第一金屬氧化物層OS1A設置於第一源極區sr1、第一汲極區dr1以及第一通道區ch1中。第一金屬氧化物圖案OS2A設置於第一通道區ch1中。第一金屬氧化物圖案OS2A未延伸至第一汲極區dr1以及第一源極區sr1。在本實施例中，第一金屬氧化物層OS1A包覆第一金屬氧化物圖案OS2A的側壁與頂面，且第一金屬氧化物圖案OS2A位於第一金屬氧化物層OS1A與基板100之間。Referring to FIG. 5 , the first semiconductor structure SM1 includes a stack of a first metal oxide layer OS1A and a first metal oxide pattern OS2A. The first metal oxide layer OS1A is disposed in the first source region sr1 , the first drain region dr1 and the first channel region ch1 . The first metal oxide pattern OS2A is disposed in the first channel region ch1. The first metal oxide pattern OS2A does not extend to the first drain region dr1 and the first source region sr1 . In this embodiment, the first metal oxide layer OS1A covers sidewalls and top surfaces of the first metal oxide pattern OS2A, and the first metal oxide pattern OS2A is located between the first metal oxide layer OS1A and the substrate 100 .

第二半導體結構SM2包括第二金屬氧化物層OS1B以及第二金屬氧化物圖案OS2B的堆疊。第二金屬氧化物層OS1B設置於第二源極區sr2、第二汲極區dr2以及第二通道區ch2中。第二金屬氧化物圖案OS2B設置於第二源極區sr2中。第二金屬氧化物圖案OS2B未延伸至第二汲極區dr2以及第二通道區ch2。在本實施例中，第二金屬氧化物層OS1B包覆第二金屬氧化物圖案OS2B的側壁與頂面，且第二金屬氧化物圖案OS2B位於第二金屬氧化物層OS1B與基板100之間。The second semiconductor structure SM2 includes a stack of a second metal oxide layer OS1B and a second metal oxide pattern OS2B. The second metal oxide layer OS1B is disposed in the second source region sr2 , the second drain region dr2 and the second channel region ch2 . The second metal oxide pattern OS2B is disposed in the second source region sr2. The second metal oxide pattern OS2B does not extend to the second drain region dr2 and the second channel region ch2 . In this embodiment, the second metal oxide layer OS1B covers sidewalls and top surfaces of the second metal oxide pattern OS2B, and the second metal oxide pattern OS2B is located between the second metal oxide layer OS1B and the substrate 100 .

在一些實施例中，第一金屬氧化物圖案OS2A與第二金屬氧化物圖案OS2B屬於相同膜層。換句話說，第一金屬氧化物圖案OS2A與第二金屬氧化物圖案OS2B是於同一次圖案化製程中所定義出來的。第一金屬氧化物圖案OS2A與第二金屬氧化物圖案OS2B包括相同的厚度與相同的材料。在一些實施例中，第一金屬氧化物圖案OS2A與第二金屬氧化物圖案OS2B的厚度t2為5奈米至25奈米。在一些實施例中，第一金屬氧化物圖案OS2A與第二金屬氧化物圖案OS2B的材料包括銦鎢鋅氧化物、銦鎵鋅氧化物或其他金屬氧化物。在一些實施例中，第二金屬氧化物圖案OS2B經摻雜而具有低於第一金屬氧化物圖案OS2A的電阻率。In some embodiments, the first metal oxide pattern OS2A and the second metal oxide pattern OS2B belong to the same film layer. In other words, the first metal oxide pattern OS2A and the second metal oxide pattern OS2B are defined in the same patterning process. The first metal oxide pattern OS2A and the second metal oxide pattern OS2B include the same thickness and the same material. In some embodiments, the thickness t2 of the first metal oxide pattern OS2A and the second metal oxide pattern OS2B is 5 nm to 25 nm. In some embodiments, the material of the first metal oxide pattern OS2A and the second metal oxide pattern OS2B includes indium tungsten zinc oxide, indium gallium zinc oxide or other metal oxides. In some embodiments, the second metal oxide pattern OS2B is doped to have a lower resistivity than the first metal oxide pattern OS2A.

在一些實施例中，第一金屬氧化物層OS1A與第二金屬氧化物層OS1B屬於相同膜層。換句話說，第一金屬氧化物層OS1A與第二金屬氧化物層OS1B是於同一次圖案化製程中所定義出來的。第一金屬氧化物層OS1A與第二金屬氧化物層OS1B包括相同的厚度與相同的材料。在一些實施例中，第一金屬氧化物層OS1A與第二金屬氧化物層OS1B的厚度t1為15奈米至25奈米。在一些實施例中，第一金屬氧化物層OS1A與第二金屬氧化物層OS1B的材料包括銦鎵鋅氧化物或其他金屬氧化物。在一些實施例中，在第一金屬氧化物層OS1A中，第一汲極區dr1以及第一源極區dr1經摻雜而具有低於第一通道區ch1的電阻率。類似地，在第二金屬氧化物層OS1B中，第二汲極區dr2以及第二源極區dr2經摻雜而具有低於第二通道區ch2的電阻率。另外，在第一通道區ch1中，第一金屬氧化物圖案OS2A的載子遷移率大於或等於第一金屬氧化物層OS1A的載子遷移率。In some embodiments, the first metal oxide layer OS1A and the second metal oxide layer OS1B belong to the same film layer. In other words, the first metal oxide layer OS1A and the second metal oxide layer OS1B are defined in the same patterning process. The first metal oxide layer OS1A and the second metal oxide layer OS1B include the same thickness and the same material. In some embodiments, the thickness t1 of the first metal oxide layer OS1A and the second metal oxide layer OS1B is 15 nm to 25 nm. In some embodiments, materials of the first metal oxide layer OS1A and the second metal oxide layer OS1B include InGaZnO or other metal oxides. In some embodiments, in the first metal oxide layer OS1A, the first drain region dr1 and the first source region dr1 are doped to have a lower resistivity than the first channel region ch1 . Similarly, in the second metal oxide layer OS1B, the second drain region dr2 and the second source region dr2 are doped to have a lower resistivity than the second channel region ch2 . In addition, in the first channel region ch1 , the carrier mobility of the first metal oxide pattern OS2A is greater than or equal to the carrier mobility of the first metal oxide layer OS1A.

在一些實施例中，第一金屬氧化物圖案OS2A的側壁與第一閘極G1的側壁之間的水平距離HD1小於300奈米，且第二金屬氧化物圖案OS2B的側壁與第二閘極G2的一側壁之間的水平距離HD2小於300奈米。In some embodiments, the horizontal distance HD1 between the sidewall of the first metal oxide pattern OS2A and the sidewall of the first gate G1 is less than 300 nm, and the sidewall of the second metal oxide pattern OS2B is closer to the second gate G2. The horizontal distance HD2 between the side walls is less than 300 nm.

基於上述，藉由於第一通道區ch1中設置第一金屬氧化物圖案OS2A，可以降低第一薄膜電晶體TL的等效阻值R L，因此，不需要增加第二薄膜電晶體TS的第二通道區ch2的長度就可以減少第一薄膜電晶體TL的等效阻值R L與第二薄膜電晶體TS的等效阻值R S的比值（R L/R S），使逆變器10C具有面積小的優點。 Based on the above, by disposing the first metal oxide pattern OS2A in the first channel region ch1, the equivalent resistance value RL of the first thin film transistor TL can be reduced. Therefore, there is no need to increase the second resistance of the second thin film transistor TS. The length of the channel region ch2 can reduce the ratio (R L / RS ) of the equivalent resistance value R L of the first thin film transistor TL to the equivalent resistance value R S of the second thin film transistor TS, so that the inverter 10C It has the advantage of small area.

此外，由於第二金屬氧化物圖案OS2B的設置，第二源極區sr2具有較低的電阻率，藉此減少第二源極S2與第二源極區sr2之間的阻抗。另外，藉由於第二源極區sr2中設置第二金屬氧化物圖案OS2B，第二源極區sr2的厚度大於第二通道區ch2的厚度，可以分散第二通道區ch2與第二源極S2之間的電場，藉此降低第二源極S2與第二金屬氧化物圖案OS2B之接觸阻抗。此外，藉由於第一通道區ch1中設置第一金屬氧化物圖案OS2A，第一通道區ch1的厚度大於第一汲極區dr1的厚度，可以分散第一汲極D1與第一通道區ch1之間的電場，藉此減少熱載子效應。In addition, due to the arrangement of the second metal oxide pattern OS2B, the second source region sr2 has a lower resistivity, thereby reducing the resistance between the second source S2 and the second source region sr2. In addition, by disposing the second metal oxide pattern OS2B in the second source region sr2, the thickness of the second source region sr2 is greater than the thickness of the second channel region ch2, and the second channel region ch2 and the second source S2 can be dispersed. The electric field between the second source electrode S2 and the second metal oxide pattern OS2B is thereby reduced. In addition, by disposing the first metal oxide pattern OS2A in the first channel region ch1, the thickness of the first channel region ch1 is greater than the thickness of the first drain region dr1, and the difference between the first drain D1 and the first channel region ch1 can be dispersed. The electric field between them, thereby reducing the hot carrier effect.

圖6是依照本發明的一實施例的一種逆變器的剖面示意圖。在此必須說明的是，圖6的實施例沿用圖5的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 6 is a schematic cross-sectional view of an inverter according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 6 follows the component numbers and part of the content of the embodiment in FIG. 5 , wherein the same or similar numbers are used to indicate the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

圖6的逆變器10D與圖5的半導體裝置10C的主要差異在於：逆變器10D的第一金屬氧化物層OS1A位於第一金屬氧化物圖案OS2A與基板100之間，且第二金屬氧化物層OS1B位於第二金屬氧化物圖案OS2B與基板100之間。The main difference between the inverter 10D in FIG. 6 and the semiconductor device 10C in FIG. 5 is that the first metal oxide layer OS1A of the inverter 10D is located between the first metal oxide pattern OS2A and the substrate 100, and the second metal oxide layer The substance layer OS1B is located between the second metal oxide pattern OS2B and the substrate 100 .

圖7A是依照本發明的一實施例的一種逆變器的電路示意圖。圖7B是圖7A的逆變器的輸出電壓與輸入電壓的示意圖。FIG. 7A is a schematic circuit diagram of an inverter according to an embodiment of the present invention. FIG. 7B is a schematic diagram of the output voltage and the input voltage of the inverter of FIG. 7A .

圖7A的逆變器的具體結構可以參考圖1的逆變器10A以及圖3的逆變器10B，於此不再贅述。For the specific structure of the inverter in FIG. 7A , reference may be made to the inverter 10A in FIG. 1 and the inverter 10B in FIG. 3 , which will not be repeated here.

第一薄膜電晶體TL2的第一汲極D1電性連接至電壓V DD。第一薄膜電晶體TL2的第一閘極G1與第一源極S1電性連接至第二薄膜電晶體TS的第二汲極D2，且第一源極S1、第一閘極G1以及第二汲極D2連接至輸出電壓V out。輸入電壓V in透過訊號線L連接至第二薄膜電晶體TS的第二閘極G2。第二薄膜電晶體TS的第二源極S2連接至接地電壓GND。 The first drain D1 of the first TFT TL2 is electrically connected to the voltage V DD . The first gate G1 and the first source S1 of the first thin film transistor TL2 are electrically connected to the second drain D2 of the second thin film transistor TS, and the first source S1, the first gate G1 and the second The drain D2 is connected to the output voltage V out . The input voltage V in is connected to the second gate G2 of the second thin film transistor TS through the signal line L. The second source S2 of the second TFT TS is connected to the ground voltage GND.

在本實施例中，第一薄膜電晶體TL與第二薄膜電晶體TS皆為增強型電晶體。第一薄膜電晶體TL的等效阻值R L不同於第二薄膜電晶體TS的等效阻值R S，等效阻值R L與等效阻值R S的比值（R L/R S）會影響逆變器的特性。當R L/R S高時，逆變器適用於處理數位訊號（Digital signal）；當R L/R S低時，逆變器適用於處理類比訊號（Analog signal）。 In this embodiment, both the first thin film transistor TL and the second thin film transistor TS are enhancement transistors. The equivalent resistance value R L of the first thin film transistor TL is different from the equivalent resistance value R S of the second thin film transistor TS, and the ratio of the equivalent resistance value R L to the equivalent resistance value R S (R L /R S ) will affect the characteristics of the inverter. When R L / R S is high, the inverter is suitable for processing digital signals (Digital signal); when R L / R S is low, the inverter is suitable for processing analog signals (Analog signal).

在本實施例中，藉由於第二通道區ch2中設置第二金屬氧化物圖案OS2B（請參考圖1與圖3），可以降低第二薄膜電晶體TS的等效阻值R S，進而改變R L/R S。換句話說，不需要調整第一通道區ch1的長度與寬度或第二通道區ch2的長度與寬度，就可以改變的R L/R S，藉此調整逆變器的特性。 In this embodiment, by setting the second metal oxide pattern OS2B in the second channel region ch2 (please refer to FIG. 1 and FIG. 3 ), the equivalent resistance value R S of the second thin film transistor TS can be reduced, thereby changing R L /R S . In other words, without adjusting the length and width of the first channel region ch1 or the length and width of the second channel region ch2, R L /R S can be changed, thereby adjusting the characteristics of the inverter.

圖8A是依照本發明的一實施例的一種逆變器的電路示意圖。圖8B是圖8A的逆變器的輸出電壓與輸入電壓的示意圖。FIG. 8A is a schematic circuit diagram of an inverter according to an embodiment of the present invention. FIG. 8B is a schematic diagram of the output voltage and the input voltage of the inverter of FIG. 8A .

圖8A的逆變器的具體結構可以參考圖5的逆變器10C以及圖6的逆變器10D，於此不再贅述。For the specific structure of the inverter in FIG. 8A , reference may be made to the inverter 10C in FIG. 5 and the inverter 10D in FIG. 6 , which will not be repeated here.

第一薄膜電晶體TL2的第一汲極D1電性連接至電壓V DD。第一薄膜電晶體TL2的第一閘極G1與第一源極S1電性連接至第二薄膜電晶體TS的第二汲極D2，且第一源極S1、第一閘極G1以及第二汲極D2連接至輸出電壓V out。輸入電壓V in透過訊號線L連接至第二薄膜電晶體TS的第二閘極G2。第二薄膜電晶體TS的第二源極S2連接至接地電壓GND。 The first drain D1 of the first TFT TL2 is electrically connected to the voltage V DD . The first gate G1 and the first source S1 of the first thin film transistor TL2 are electrically connected to the second drain D2 of the second thin film transistor TS, and the first source S1, the first gate G1 and the second The drain D2 is connected to the output voltage V out . The input voltage V in is connected to the second gate G2 of the second thin film transistor TS through the signal line L. The second source S2 of the second TFT TS is connected to the ground voltage GND.

在本實施例中，第一薄膜電晶體TL為耗盡型電晶體，而第二薄膜電晶體TS為增強型電晶體。第一薄膜電晶體TL的等效阻值R L不同於第二薄膜電晶體TS的等效阻值R S，等效阻值R L與等效阻值R S的比值（R L/R S）會影響逆變器的特性。當R L/R S高時，逆變器適用於處理數位訊號，當R L/R S低時，逆變器適用於處理類比訊號。 In this embodiment, the first thin film transistor TL is a depletion type transistor, and the second thin film transistor TS is an enhancement type transistor. The equivalent resistance value R L of the first thin film transistor TL is different from the equivalent resistance value R S of the second thin film transistor TS, and the ratio of the equivalent resistance value R L to the equivalent resistance value R S (R L /R S ) will affect the characteristics of the inverter. When R L / RS is high, the inverter is suitable for processing digital signals, and when R L / RS is low, the inverter is suitable for processing analog signals.

在本實施例中，藉由於第一通道區ch1中設置第一金屬氧化物圖案OS2A（請參考圖5與圖6），可以降低第一薄膜電晶體TL的等效阻值R L，進而改變R L/R S。換句話說，不需要調整第一通道區ch1的長度與寬度或第二通道區ch2的長度與寬度，就可以改變R L/R S，藉此調整逆變器的特性。 In this embodiment, by setting the first metal oxide pattern OS2A in the first channel region ch1 (please refer to FIG. 5 and FIG. 6 ), the equivalent resistance value RL of the first thin film transistor TL can be reduced, thereby changing the R L /R S . In other words, without adjusting the length and width of the first channel region ch1 or the length and width of the second channel region ch2, R L /R S can be changed, thereby adjusting the characteristics of the inverter.

10A,10B,10C,10D:逆變器 100:基板 110:緩衝層 120:閘介電層 130:層間介電層 TL:第一薄膜電晶體 TS:第二薄膜電晶體 ch1:第一通道區 ch2:第二通道區 D1第一汲極 D2第二汲極 dr1:第一汲極區 dr2:第二汲極區 G1:第一閘極 G2:第二閘極 HD1,HD2:水平距離 L:訊號線 ND:法線方向 OS1A,OS1A’:第一金屬氧化物層 OS1B,OS1B’:第二金屬氧化物層 OS2A,OS2A’:第一金屬氧化物圖案 OS2B:第二金屬氧化物圖案 R L,R S:等效阻值 S1:第一源極 S2:第二源極 SM1:第一半導體結構 SM2:第二半導體結構 sr1:第一源極區 sr2:第二源極區 t1,t2:厚度 V1:第一接觸孔 V2:第二接觸孔 V3:第三接觸孔 V4:第四接觸孔 V5:第五接觸孔 V6:第六接觸孔 V DD:電壓 V in:輸入電壓 V out:輸出電壓 GND:接地電壓10A, 10B, 10C, 10D: inverter 100: substrate 110: buffer layer 120: gate dielectric layer 130: interlayer dielectric layer TL: first thin film transistor TS: second thin film transistor ch1: first channel region ch2: second channel area D1 first drain D2 second drain dr1: first drain area dr2: second drain area G1: first gate G2: second gate HD1, HD2: horizontal distance L: Signal line ND: normal direction OS1A, OS1A': first metal oxide layer OS1B, OS1B': second metal oxide layer OS2A, OS2A': first metal oxide pattern OS2B: second metal oxide pattern R L , R S : equivalent resistance S1: first source S2: second source SM1: first semiconductor structure SM2: second semiconductor structure sr1: first source region sr2: second source region t1, t2: Thickness V1: first contact hole V2: second contact hole V3: third contact hole V4: fourth contact hole V5: fifth contact hole V6: sixth contact hole V DD : voltage V in : input voltage V out : output Voltage GND: ground voltage

圖1是依照本發明的一實施例的一種逆變器的剖面示意圖。 圖2A至圖2D是圖1的逆變器的製造方法的剖面示意圖。 圖3是依照本發明的一實施例的一種逆變器的剖面示意圖。 圖4A至圖4D是圖3的逆變器的製造方法的剖面示意圖。 圖5是依照本發明的一實施例的一種逆變器的剖面示意圖。 圖6是依照本發明的一實施例的一種逆變器的剖面示意圖。 圖7A是依照本發明的一實施例的一種逆變器的電路示意圖。 圖7B是圖7A的逆變器的輸出電壓與輸入電壓的示意圖。 圖8A是依照本發明的一實施例的一種逆變器的電路示意圖。 圖8B是圖8A的逆變器的輸出電壓與輸入電壓的示意圖。 FIG. 1 is a schematic cross-sectional view of an inverter according to an embodiment of the present invention. 2A to 2D are schematic cross-sectional views of the manufacturing method of the inverter shown in FIG. 1 . FIG. 3 is a schematic cross-sectional view of an inverter according to an embodiment of the present invention. 4A to 4D are schematic cross-sectional views of the manufacturing method of the inverter shown in FIG. 3 . FIG. 5 is a schematic cross-sectional view of an inverter according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of an inverter according to an embodiment of the present invention. FIG. 7A is a schematic circuit diagram of an inverter according to an embodiment of the present invention. FIG. 7B is a schematic diagram of the output voltage and the input voltage of the inverter of FIG. 7A . FIG. 8A is a schematic circuit diagram of an inverter according to an embodiment of the present invention. FIG. 8B is a schematic diagram of the output voltage and the input voltage of the inverter of FIG. 8A .

10A:逆變器 10A: Inverter

100:基板 100: Substrate

110:緩衝層 110: buffer layer

120:閘介電層 120: gate dielectric layer

130:層間介電層 130: interlayer dielectric layer

TL:第一薄膜電晶體 TL: The first thin film transistor

TS:第二薄膜電晶體 TS: second thin film transistor

ch1:第一通道區 ch1: the first channel area

ch2:第二通道區 ch2: the second channel area

D1:第一汲極 D1: the first drain

D2:第二汲極 D2: the second drain

dr1:第一汲極區 dr1: the first drain area

dr2:第二汲極區 dr2: the second drain area

G1:第一閘極 G1: the first gate

G2:第二閘極 G2: the second gate

HD1,HD2:水平距離 HD1, HD2: horizontal distance

L:訊號線 L: signal line

ND:法線方向 ND: normal direction

OS1A:第一金屬氧化物層 OS1A: first metal oxide layer

OS1B:第二金屬氧化物層 OS1B: second metal oxide layer

OS2A:第一金屬氧化物圖案 OS2A: First Metal Oxide Pattern

OS2B:第二金屬氧化物圖案 OS2B: Second Metal Oxide Pattern

S1:第一源極 S1: first source

S2:第二源極 S2: second source

SM1:第一半導體結構 SM1: First Semiconductor Structure

SM2:第二半導體結構 SM2: Second semiconductor structure

sr1:第一源極區 sr1: the first source region

sr2:第二源極區 sr2: second source region

t1,t2:厚度 t1, t2: thickness

V1:第一接觸孔 V1: first contact hole

V2:第二接觸孔 V2: Second contact hole

V3:第三接觸孔 V3: The third contact hole

V4:第四接觸孔 V4: Fourth contact hole

V5:第五接觸孔 V5: fifth contact hole

V6:第六接觸孔 V6: sixth contact hole

Claims (16)

一種逆變器，包括： 一基板； 一第一薄膜電晶體，位於該基板之上，且包括： 一第一閘極； 一第一半導體結構，包括一第一源極區、一第一汲極區以及位於該第一源極區與該第一汲極區之間的一第一通道區，其中該第一閘極重疊於該第一通道區，且該第一源極區的厚度大於該第一通道區的厚度以及該第一汲極區的厚度； 一第一源極，電性連接該第一源極區；以及 一第一汲極，電性連接該第一汲極區以及該第一閘極；以及 一第二薄膜電晶體，位於該基板之上，且包括： 一第二閘極； 一第二半導體結構，包括一第二源極區、一第二汲極區以及位於該第二源極區與該第二汲極區之間的一第二通道區，其中該第二閘極重疊於該第二通道區，且該第二通道區的厚度大於該第二源極區的厚度以及該第二汲極區的厚度； 一第二源極，電性連接該第二源極區；以及 一第二汲極，電性連接該第二汲極區以及該第一源極。 An inverter comprising: a substrate; A first thin film transistor is located on the substrate and includes: a first gate; A first semiconductor structure, including a first source region, a first drain region, and a first channel region between the first source region and the first drain region, wherein the first gate overlapping the first channel region, and the thickness of the first source region is greater than the thickness of the first channel region and the thickness of the first drain region; a first source electrically connected to the first source region; and a first drain electrically connected to the first drain region and the first gate; and A second thin film transistor is located on the substrate and includes: a second gate; A second semiconductor structure, including a second source region, a second drain region, and a second channel region between the second source region and the second drain region, wherein the second gate overlapping with the second channel region, and the thickness of the second channel region is greater than the thickness of the second source region and the thickness of the second drain region; a second source electrically connected to the second source region; and A second drain is electrically connected to the second drain region and the first source. 如請求項1所述的逆變器，其中該第一半導體結構包括一第一金屬氧化物層以及一第一金屬氧化物圖案的堆疊，其中該第一金屬氧化物層設置於該第一源極區、該第一汲極區以及該第一通道區中，且該第一金屬氧化物圖案設置於該第一源極區中。The inverter according to claim 1, wherein the first semiconductor structure comprises a stack of a first metal oxide layer and a first metal oxide pattern, wherein the first metal oxide layer is disposed on the first source electrode region, the first drain region and the first channel region, and the first metal oxide pattern is disposed in the first source region. 如請求項2所述的逆變器，其中該第二半導體結構包括一第二金屬氧化物層以及一第二金屬氧化物圖案的堆疊，其中該第二金屬氧化物層設置於該第二源極區、該第二汲極區以及該第二通道區中，且該第二金屬氧化物圖案設置於該第二通道區中。The inverter according to claim 2, wherein the second semiconductor structure comprises a stack of a second metal oxide layer and a second metal oxide pattern, wherein the second metal oxide layer is disposed on the second source electrode region, the second drain region and the second channel region, and the second metal oxide pattern is disposed in the second channel region. 如請求項3所述的逆變器，其中在該第二通道區中，該第二金屬氧化物圖案的載子遷移率大於或等於該第二金屬氧化物層的載子遷移率。The inverter as claimed in claim 3, wherein in the second channel region, the carrier mobility of the second metal oxide pattern is greater than or equal to the carrier mobility of the second metal oxide layer. 如請求項3所述的逆變器，其中該第一金屬氧化物層以及該第二金屬氧化物層的厚度為15奈米至25奈米，且該第一金屬氧化物圖案與該第二金屬氧化物圖案的厚度為5奈米至25奈米。The inverter according to claim 3, wherein the thickness of the first metal oxide layer and the second metal oxide layer is 15 nm to 25 nm, and the first metal oxide pattern and the second The metal oxide pattern has a thickness of 5 nm to 25 nm. 如請求項3所述的逆變器，其中該第一金屬氧化物圖案的一側壁與該第一閘極的一側壁之間的水平距離小於300奈米，且該第二金屬氧化物圖案的一側壁與該第二閘極的一側壁之間的水平距離小於300奈米。The inverter according to claim 3, wherein the horizontal distance between the sidewall of the first metal oxide pattern and the sidewall of the first gate is less than 300 nm, and the second metal oxide pattern A horizontal distance between a sidewall and a sidewall of the second gate is less than 300 nanometers. 如請求項3所述的逆變器，其中該第一金屬氧化物層包覆該第一金屬氧化物圖案的側壁與頂面，且該第二金屬氧化物層包覆該第二金屬氧化物圖案的側壁與頂面。The inverter according to claim 3, wherein the first metal oxide layer coats the sidewall and top surface of the first metal oxide pattern, and the second metal oxide layer coats the second metal oxide Patterned sidewalls and top surfaces. 如請求項3所述的逆變器，其中該第一金屬氧化物層位於該第一金屬氧化物圖案與該基板之間，且該第二金屬氧化物層位於該第二金屬氧化物圖案與該基板之間。The inverter according to claim 3, wherein the first metal oxide layer is located between the first metal oxide pattern and the substrate, and the second metal oxide layer is located between the second metal oxide pattern and the substrate. between the substrates. 一種逆變器，包括： 一基板； 一第一薄膜電晶體，位於該基板之上，且包括： 一第一閘極； 一第一半導體結構，包括一第一源極區、一第一汲極區以及位於該第一源極區與該第一汲極區之間的一第一通道區，其中該第一閘極重疊於該第一通道區，且該第一通道區的厚度大於該第一源極區的厚度以及該第一汲極區的厚度； 一第一源極，電性連接該第一源極區以及該第一閘極；以及 一第一汲極，電性連接該第一汲極區；以及 一第二薄膜電晶體，位於該基板之上，且包括： 一第二閘極； 一第二半導體結構，包括一第二源極區、一第二汲極區以及位於該第二源極區與該第二汲極區之間的一第二通道區，其中該第二閘極重疊於該第二通道區，且該第二源極區的厚度大於該第二通道區的厚度以及該第二汲極區的厚度； 一第二源極，電性連接該第二源極區；以及 一第二汲極，電性連接該第二汲極區以及該第一源極。 An inverter comprising: a substrate; A first thin film transistor is located on the substrate and includes: a first gate; A first semiconductor structure, including a first source region, a first drain region, and a first channel region between the first source region and the first drain region, wherein the first gate overlapping the first channel region, and the thickness of the first channel region is greater than the thickness of the first source region and the thickness of the first drain region; a first source electrically connected to the first source region and the first gate; and a first drain electrically connected to the first drain region; and A second thin film transistor is located on the substrate and includes: a second gate; A second semiconductor structure, including a second source region, a second drain region, and a second channel region between the second source region and the second drain region, wherein the second gate overlapping with the second channel region, and the thickness of the second source region is greater than the thickness of the second channel region and the thickness of the second drain region; a second source electrically connected to the second source region; and A second drain is electrically connected to the second drain region and the first source. 如請求項9所述的逆變器，其中該第一半導體結構包括一第一金屬氧化物層以及一第一金屬氧化物圖案的堆疊，其中該第一金屬氧化物層設置於該第一源極區、該第一汲極區以及該第一通道區中，且該第一金屬氧化物圖案設置於該第一通道區中。The inverter as claimed in claim 9, wherein the first semiconductor structure comprises a stack of a first metal oxide layer and a first metal oxide pattern, wherein the first metal oxide layer is disposed on the first source electrode region, the first drain region and the first channel region, and the first metal oxide pattern is disposed in the first channel region. 如請求項10所述的逆變器，其中該第二半導體結構包括一第二金屬氧化物層以及一第二金屬氧化物圖案的堆疊，其中該第二金屬氧化物層設置於該第二源極區、該第二汲極區以及該第二通道區中，且該第二金屬氧化物圖案設置於該第二源極區中。The inverter according to claim 10, wherein the second semiconductor structure comprises a stack of a second metal oxide layer and a second metal oxide pattern, wherein the second metal oxide layer is disposed on the second source electrode region, the second drain region and the second channel region, and the second metal oxide pattern is disposed in the second source region. 如請求項11所述的逆變器，其中在該第一通道區中，該第一金屬氧化物圖案的載子遷移率大於或等於該第一金屬氧化物層的載子遷移率。The inverter as claimed in claim 11, wherein in the first channel region, the carrier mobility of the first metal oxide pattern is greater than or equal to the carrier mobility of the first metal oxide layer. 如請求項11所述的逆變器，其中該第一金屬氧化物層以及該第二金屬氧化物層的厚度為15奈米至25奈米，且該第一金屬氧化物圖案與該第二金屬氧化物圖案的厚度為5奈米至25奈米。The inverter according to claim 11, wherein the thickness of the first metal oxide layer and the second metal oxide layer is 15 nm to 25 nm, and the first metal oxide pattern and the second The metal oxide pattern has a thickness of 5 nm to 25 nm. 如請求項11所述的逆變器，其中該第一金屬氧化物圖案的一側壁與該第一閘極的一側壁之間的水平距離小於300奈米，且該第二金屬氧化物圖案的一側壁與該第二閘極的一側壁之間的水平距離小於300奈米。The inverter as claimed in claim 11, wherein the horizontal distance between the sidewall of the first metal oxide pattern and the sidewall of the first gate is less than 300 nm, and the second metal oxide pattern A horizontal distance between a sidewall and a sidewall of the second gate is less than 300 nanometers. 如請求項11所述的逆變器，其中該第一金屬氧化物層包覆該第一金屬氧化物圖案的側壁與頂面，且該第二金屬氧化物層包覆該第二金屬氧化物圖案的側壁與頂面。The inverter according to claim 11, wherein the first metal oxide layer covers the sidewall and top surface of the first metal oxide pattern, and the second metal oxide layer covers the second metal oxide Patterned sidewalls and top surfaces. 如請求項11所述的逆變器，其中該第一金屬氧化物層位於該第一金屬氧化物圖案與該基板之間，且該第二金屬氧化物層位於該第二金屬氧化物圖案與該基板之間。The inverter according to claim 11, wherein the first metal oxide layer is located between the first metal oxide pattern and the substrate, and the second metal oxide layer is located between the second metal oxide pattern and the substrate. between the substrates.
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