TWI685696B - Active device substrate and manufacturing method thereof - Google Patents

Active device substrate and manufacturing method thereof Download PDF

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Publication number
TWI685696B
TWI685696B TW107134629A TW107134629A TWI685696B TW I685696 B TWI685696 B TW I685696B TW 107134629 A TW107134629 A TW 107134629A TW 107134629 A TW107134629 A TW 107134629A TW I685696 B TWI685696 B TW I685696B
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layer
gate
semiconductor channel
scan line
active device
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TW107134629A
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TW202014768A (en
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陳銘耀
黃國有
徐文義
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友達光電股份有限公司
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Priority to TW107134629A priority Critical patent/TWI685696B/en
Priority to CN201811586721.XA priority patent/CN109686743B/en
Priority to US16/543,626 priority patent/US11127808B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

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Abstract

An active device substrate and a manufacturing method thereof are provided. The active device substrate includes a substrate, a first scan line, a second scan line, a data line, a first active device, a first pixel electrode, a second active device, and a second pixel electrode. The first active device includes a first semiconductor layer, a first gate, a first source, and a first drain. The first gate is electrically connected with the first scan line. The first pixel electrode is electrically connected with the first drain. The second active device includes a second semiconductor layer, a second gate, and a second drain. The first semiconductor layer connects a source region of the second semiconductor layer. The first semiconductor layer and the second semiconductor layer belong to same layer. The second gate is electrically connected with the second scan line. The second pixel electrode is electrically connected with the second drain.

Description

主動元件基板及其製造方法Active element substrate and manufacturing method thereof

本發明是有關於一種主動元件基板，且特別是有關於一種包括第一主動元件與第二主動元件的主動元件基板及其製造方法。 The invention relates to an active device substrate, and in particular to an active device substrate including a first active device and a second active device and a method of manufacturing the same.

近年來隨著顯示科技的進步，顯示器解析度、電腦運算技術與網路速度的提升，帶動了擴增實境(Augmented Reality)與虛擬實境(Virtual Reality)的技術快速發展。尤其在工業4.0趨勢推波助瀾之下，在可預見的將來，擴增實境與虛擬實境技術將普遍應用於教育、物流、醫療、軍事和製造等層面。 In recent years, with the advancement of display technology, the increase in display resolution, computer computing technology, and network speed has driven the rapid development of Augmented Reality and Virtual Reality technologies. Especially with the boost of Industry 4.0 trends, in the foreseeable future, augmented reality and virtual reality technologies will be widely used in education, logistics, medical, military and manufacturing.

擴增實境與虛擬實境應用所需的顯示面板主要裝載於頭戴式顯示裝置(Head-mounted Display)之內，提高顯示面板的畫面解析度可增進使用者沈浸感。因此，顯示面板解析度技術的提昇為擴增實境與虛擬實境應用可否加速推展之關鍵。 The display panels required for augmented reality and virtual reality applications are mainly mounted in a head-mounted display (Head-mounted Display), and improving the screen resolution of the display panel can increase the user's immersion. Therefore, the improvement of display panel resolution technology is the key to the accelerated development of augmented reality and virtual reality applications.

本發明提供一種主動元件基板，可以改善顯示面板的畫面解析度不足的問題。 The invention provides an active device substrate, which can improve the problem of insufficient display resolution of the display panel.

本發明提供一種主動元件基板的製造方法，可以改善顯示面板的畫面解析度不足的問題。 The invention provides a method for manufacturing an active device substrate, which can improve the problem of insufficient display resolution of a display panel.

本發明的至少一實施例提供一種主動元件基板，包括基板、第一掃描線、第二掃描線、資料線、第一主動元件、第一畫素電極、第二主動元件以及第二畫素電極。第一掃描線、第二掃描線與資料線設置於基板。第一主動元件包括第一半導體通道層、第一閘極、第一源極以及第一汲極。第一閘極重疊於第一半導體通道層，且電性連接第一掃描線。第一源極電性連接資料線與第一半導體通道層。第一汲極電性連接第一半導體通道層。第一畫素電極電性連接第一汲極。第二主動元件包括第二半導體通道層、第二閘極以及第二汲極。第一半導體通道層連接第二半導體通道層的源極區。第一半導體通道層以及第二半導體通道層屬於同一膜層。第二閘極重疊於第二半導體通道層，且電性連接第二掃描線。第二汲極電性連接第二半導體通道層。第二畫素電極電性連接第二汲極。 At least one embodiment of the present invention provides an active element substrate including a substrate, a first scan line, a second scan line, a data line, a first active element, a first pixel electrode, a second active element, and a second pixel electrode . The first scan line, the second scan line and the data line are disposed on the substrate. The first active device includes a first semiconductor channel layer, a first gate, a first source, and a first drain. The first gate electrode overlaps the first semiconductor channel layer and is electrically connected to the first scan line. The first source is electrically connected to the data line and the first semiconductor channel layer. The first drain is electrically connected to the first semiconductor channel layer. The first pixel electrode is electrically connected to the first drain. The second active device includes a second semiconductor channel layer, a second gate, and a second drain. The first semiconductor channel layer is connected to the source region of the second semiconductor channel layer. The first semiconductor channel layer and the second semiconductor channel layer belong to the same film layer. The second gate electrode overlaps the second semiconductor channel layer and is electrically connected to the second scan line. The second drain is electrically connected to the second semiconductor channel layer. The second pixel electrode is electrically connected to the second drain.

本發明的至少一實施例提供一種主動元件基板的製造方法，包括：提供基板；形成半導體層於基板上；形成閘極絕緣層於基板上；對半導體層進行處理製程，以形成第一半導體通道層以及第二半導體通道層，第一半導體通道層連接第二半導體通道層的源極區；形成第一掃描線、第二掃描線、第一閘極以及第二 閘極於閘極絕緣層上，第一閘極電性連接第一掃描線，第二閘極電性連接第二掃描線；形成層間介電層於第一掃描線、第二掃描線、第一閘極以及第二閘極上；形成第一源極、資料線、第一汲極以及第二汲極於層間介電層上，第一源極電性連接資料線與第一半導體通道層，第一汲極與第二汲極分別電性連接第一半導體通道層與第二半導體通道層；形成第一絕緣層於第一源極、第一汲極、第二汲極、資料線以及層間介電層上；形成第一畫素電極與第二畫素電極於第一絕緣層上，第一畫素電極與第二畫素電極分別電性連接第一汲極與第二汲極。 At least one embodiment of the present invention provides a method for manufacturing an active device substrate, including: providing a substrate; forming a semiconductor layer on the substrate; forming a gate insulating layer on the substrate; and processing the semiconductor layer to form a first semiconductor channel Layer and a second semiconductor channel layer, the first semiconductor channel layer is connected to the source region of the second semiconductor channel layer; forming a first scan line, a second scan line, a first gate and a second The gate is on the gate insulating layer, the first gate is electrically connected to the first scan line, and the second gate is electrically connected to the second scan line; an interlayer dielectric layer is formed on the first scan line, the second scan line, the first A gate electrode and a second gate electrode; forming a first source electrode, a data line, a first drain electrode and a second drain electrode on the interlayer dielectric layer, the first source electrode is electrically connected to the data line and the first semiconductor channel layer, The first drain and the second drain are electrically connected to the first semiconductor channel layer and the second semiconductor channel layer, respectively; forming a first insulating layer between the first source, the first drain, the second drain, the data line and the layer On the dielectric layer; forming a first pixel electrode and a second pixel electrode on the first insulating layer, the first pixel electrode and the second pixel electrode are electrically connected to the first drain electrode and the second drain electrode, respectively.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

10、20、30、40、50、60、70、80、90‧‧‧主動元件基板 10, 20, 30, 40, 50, 60, 70, 80, 90 ‧‧‧ active element substrate

AA’、BB’、CC’、DD’‧‧‧剖面線 AA’, BB’, CC’, DD’ ‧‧‧ hatch

BL‧‧‧緩衝層 BL‧‧‧Buffer layer

C1、C2、C3‧‧‧共通電極 C1, C2, C3‧‧‧Common electrode

CE‧‧‧電容電極 CE‧‧‧Capacitor electrode

D1、D2、D3‧‧‧汲極 D1, D2, D3 ‧‧‧ Drain

DL‧‧‧資料線 DL‧‧‧Data cable

G1、G2、G3‧‧‧閘極 G1, G2, G3 ‧‧‧ gate

GI‧‧‧閘極絕緣層 GI‧‧‧Gate insulation

H1、H2、H3、H4、OP1、OP2、OP3‧‧‧開口 H1, H2, H3, H4, OP1, OP2, OP3 ‧‧‧ opening

I1、I2‧‧‧絕緣層 I1, I2‧‧‧Insulation

ILD‧‧‧層間介電層 ILD‧‧‧Interlayer dielectric layer

IS1、IS2‧‧‧島狀結構 IS1, IS2 ‧‧‧ island structure

L1、L3‧‧‧導線 L1, L3‧‧‧wire

M1、M2‧‧‧金屬層 M1, M2‧‧‧Metal layer

P1‧‧‧重摻雜區 P1‧‧‧ heavily doped area

P2‧‧‧輕摻雜區 P2‧‧‧ lightly doped region

P3‧‧‧主動區 P3‧‧‧Active area

PE1、PE2、PE3‧‧‧畫素電極 PE1, PE2, PE3 ‧‧‧ pixel electrode

R1、R4、R7‧‧‧源極區 R1, R4, R7 ‧‧‧ source region

R2、R5、R8‧‧‧通道區 R2, R5, R8 ‧‧‧ channel area

R3、R6、R9‧‧‧汲極區 R3, R6, R9 ‧‧‧ Drain

RS1、RS2‧‧‧感光材料 RS1, RS2 ‧‧‧ photosensitive material

S1‧‧‧源極 S1‧‧‧Source

SB‧‧‧基板 SB‧‧‧Substrate

SC‧‧‧半導體層 SC‧‧‧Semiconductor layer

SC1、SC2、SC3‧‧‧半導體通道層 SC1, SC2, SC3 ‧‧‧ semiconductor channel layer

SL1、SL2、SL3‧‧‧掃描線 SL1, SL2, SL3 ‧‧‧ scanning line

SM‧‧‧遮光層 SM‧‧‧Light-shielding layer

T1、T2、T3‧‧‧主動元件 T1, T2, T3 ‧‧‧ active components

X1、X2‧‧‧延伸部 X1, X2‧‧‧Extension

Y1、Y2‧‧‧分支部 Y1, Y2‧‧‧ Branch

Z1、Z2‧‧‧部分 Z1, Z2‧‧‧‧

圖1A~圖1F是依照本發明的一實施例的一種主動元件基板的製造方法的上視示意圖。 1A-1F are schematic top views of a method for manufacturing an active device substrate according to an embodiment of the invention.

圖2是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 2 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention.

圖3是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 3 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention.

圖4是依照本發明的一實施例的一種主動元件基板的上視示意圖。 4 is a schematic top view of an active device substrate according to an embodiment of the invention.

圖5是依照本發明的一實施例的一種主動元件基板的剖面示 意圖。 5 is a cross-sectional view of an active device substrate according to an embodiment of the invention intention.

圖6A~圖6D是依照本發明的一實施例的一種主動元件基板的製造方法的上視示意圖。 6A-6D are schematic top views of a method for manufacturing an active device substrate according to an embodiment of the invention.

圖7是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 7 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention.

圖8是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention.

圖9是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 9 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention.

圖10是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 10 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention.

圖11A~圖11G是依照本發明的一實施例的一種主動元件基板的製造方法的上視示意圖。 11A-11G are schematic top views of a method for manufacturing an active device substrate according to an embodiment of the invention.

圖12是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 12 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention.

圖13是依照本發明的一實施例的一種主動元件基板的剖面示意圖。 13 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention.

圖1A~圖1F是依照本發明的一實施例的一種主動元件基板的製造方法的上視示意圖。圖2是依照本發明的一實施例的一種主動元件基板的剖面示意圖。圖2對應於圖1F的剖面線AA’。 1A-1F are schematic top views of a method for manufacturing an active device substrate according to an embodiment of the invention. 2 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention. Fig. 2 corresponds to section line AA' of Fig. 1F.

請參考圖1A與圖2，提供基板SB。基板SB之材質可為玻璃、石英、有機聚合物、或是不透光/反射材料(例如：導電材料、金屬、晶圓、陶瓷、或其它可適用的材料)、或是其它可適用的材料。若使用導電材料或金屬時，則在基板SB上覆蓋一層絕緣 層(未繪示)，以避免短路問題。在一些實施例中，選擇性的形成遮光層SM於基板SB上。遮光層SM有助於改善主動元件基板漏電的問題。 Please refer to FIGS. 1A and 2 to provide a substrate SB. The material of the substrate SB can be glass, quartz, organic polymer, or opaque/reflective materials (for example: conductive materials, metals, wafers, ceramics, or other applicable materials), or other applicable materials . If conductive material or metal is used, cover the substrate SB with a layer of insulation Layer (not shown) to avoid short circuit problems. In some embodiments, the light shielding layer SM is selectively formed on the substrate SB. The light shielding layer SM helps to improve the problem of leakage of the active device substrate.

請參考圖1B與圖2，形成半導體層SC於基板SB上。半導體層SC例如重疊於遮光層SM。在本實施例中，形成半導體層SC之前還會先形成緩衝層BL，緩衝層BL例如位於半導體層SC與遮光層SM之間，但本發明不以此為限。緩衝層BL的材料包含無機材料(例如：氧化矽、氮化矽、氮氧化矽、其它合適的材料或上述至少二種材料的堆疊層)、有機材料或其它合適的材料或上述之組合。 Please refer to FIGS. 1B and 2 to form a semiconductor layer SC on the substrate SB. The semiconductor layer SC overlaps with the light shielding layer SM, for example. In this embodiment, a buffer layer BL is formed before the semiconductor layer SC is formed. The buffer layer BL is located between the semiconductor layer SC and the light-shielding layer SM, for example, but the present invention is not limited to this. The material of the buffer layer BL includes inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride, other suitable materials or stacked layers of at least two of the above materials), organic materials or other suitable materials, or a combination thereof.

半導體層SC為單層或多層結構，其包含非晶矽、多晶矽、微晶矽、單晶矽、有機半導體材料、氧化物半導體材料(例如：銦鋅氧化物、銦鎵鋅氧化物或其它合適的材料或上述之組合)或其它合適的材料或含有摻雜物(dopant)於上述材料中或上述之組合。在本實施例中，半導體層SC是以多晶矽為例。 The semiconductor layer SC is a single-layer or multi-layer structure, which includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example: indium zinc oxide, indium gallium zinc oxide or other suitable Materials or combinations thereof) or other suitable materials or containing dopants in the above materials or combinations thereof. In this embodiment, the semiconductor layer SC is polysilicon as an example.

請參考圖1C、圖1D與圖2，形成閘極絕緣層GI於基板SB上。 Please refer to FIGS. 1C, 1D and 2 to form a gate insulating layer GI on the substrate SB.

形成第一金屬層M1於閘極絕緣層GI上。第一金屬層M1重疊於部分半導體層SC。以第一金屬層M1為罩幕，對半導體層SC進行重摻雜製程，以於半導體層SC中形成重摻雜區P1。 A first metal layer M1 is formed on the gate insulating layer GI. The first metal layer M1 overlaps a part of the semiconductor layer SC. Using the first metal layer M1 as a mask, the semiconductor layer SC is heavily doped to form a heavily doped region P1 in the semiconductor layer SC.

圖案化第一金屬層M1以形成第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2。第一掃描線SL1、第二 掃描線SL2、第一閘極G1以及第二閘極G2位於閘極絕緣層GI上，第一閘極G1電性連接第一掃描線SL1，第二閘極G2電性連接第二掃描線SL2。 The first metal layer M1 is patterned to form a first scan line SL1, a second scan line SL2, a first gate G1, and a second gate G2. First scan line SL1, second The scan line SL2, the first gate G1 and the second gate G2 are located on the gate insulating layer GI, the first gate G1 is electrically connected to the first scan line SL1, and the second gate G2 is electrically connected to the second scan line SL2 .

在一些實施例中，選擇性地對半導體層SC進行輕摻雜製程。舉例來說，以第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2為罩幕，對半導體層SC進行輕摻雜製程，以於半導體層SC中形成輕摻雜區P2。 In some embodiments, the semiconductor layer SC is selectively subjected to a light doping process. For example, using the first scan line SL1, the second scan line SL2, the first gate G1, and the second gate G2 as masks, a light doping process is performed on the semiconductor layer SC to form a light weight in the semiconductor layer SC Doped region P2.

對半導體層SC進行處理製程，以形成第一半導體通道層SC1以及第二半導體通道層SC2。在一些實施例中，第一半導體通道層SC1以及第二半導體通道層SC2例如為P形摻雜的半導體材料或N形摻雜的半導體材料。在本實施例中，處理製程為圖1C的重摻雜製程，且對半導體層SC進行圖1C的重摻雜製程以及圖1D的輕摻雜製程以形成第一半導體通道層SC1以及第二半導體通道層SC2，但本發明不以此為限。在其他實施例中，半導體層SC的材料包括金屬氧化物，且處理製程為電漿處理製程。 The semiconductor layer SC is processed to form a first semiconductor channel layer SC1 and a second semiconductor channel layer SC2. In some embodiments, the first semiconductor channel layer SC1 and the second semiconductor channel layer SC2 are, for example, P-type doped semiconductor materials or N-type doped semiconductor materials. In this embodiment, the processing process is the heavily doped process of FIG. 1C, and the heavily doped process of FIG. 1C and the lightly doped process of FIG. 1D are performed on the semiconductor layer SC to form the first semiconductor channel layer SC1 and the second semiconductor The channel layer SC2, but the invention is not limited thereto. In other embodiments, the material of the semiconductor layer SC includes a metal oxide, and the processing process is a plasma processing process.

第一半導體通道層SC1包括依序連接的源極區R1、通道區R2以及汲極區R3。第二半導體通道層SC2包括依序連接的源極區R4、通道區R5以及汲極區R6。 The first semiconductor channel layer SC1 includes a source region R1, a channel region R2, and a drain region R3 connected in sequence. The second semiconductor channel layer SC2 includes a source region R4, a channel region R5, and a drain region R6 connected in sequence.

在本實施例中，通道區R2以及通道區R5有部分(重疊於第一閘極G1以及第二閘極G2的部分)屬於沒有接受過重摻雜製程與輕摻雜製程的主動區P3，主動區P3的兩側屬於輕摻雜區P2，輕摻雜區P2的兩側屬於重摻雜區P1。 In this embodiment, part of the channel region R2 and the channel region R5 (the portion overlapping the first gate G1 and the second gate G2) belong to the active region P3 that has not undergone the overdoping process and the lightly doping process. Both sides of the region P3 belong to the lightly doped region P2, and both sides of the lightly doped region P2 belong to the heavily doped region P1.

第一閘極G1包括第一延伸部X1與第一分支部Y1。第一延伸部X1連接第一掃描線SL1。第一分支部Y1連接第一延伸部X1，且與第一延伸部X1之間具有夾角θ 1，夾角θ 1例如小於180度大於0度，於本實施例中，夾角為90度。第一延伸部X1與第一分支部Y1分別重疊於第一半導體通道層SC1，因此，通道區R2具有分開的兩個主動區P3，且分別重疊於第一延伸部X1與第一分支部Y1，因此可以減少漏電流問題。 The first gate G1 includes a first extension X1 and a first branch Y1. The first extension X1 is connected to the first scan line SL1. The first branch portion Y1 is connected to the first extension portion X1 and has an included angle θ 1 with the first extended portion X1. The included angle θ 1 is, for example, less than 180 degrees and greater than 0 degrees. In this embodiment, the included angle is 90 degrees. The first extending portion X1 and the first branch portion Y1 respectively overlap the first semiconductor channel layer SC1. Therefore, the channel region R2 has two active regions P3 separated, and overlaps the first extending portion X1 and the first branch portion Y1, respectively. , So the leakage current problem can be reduced.

第二閘極G2包括第二延伸部X2與第二分支部Y2。第二延伸部X2連接第二掃描線SL2。第二分支部Y2連接第二延伸部X2，且與第二延伸部X2之間具有夾角θ 2。第二延伸部X2與第二分支部Y2分別重疊於第二半導體通道層SC2，因此，通道區R5具有分開的兩個主動區P3，且分別重疊於第二延伸部X2與第二分支部Y2，因此可以減少漏電流問題。 The second gate G2 includes a second extension X2 and a second branch Y2. The second extension X2 is connected to the second scan line SL2. The second branch portion Y2 is connected to the second extension portion X2 and has an angle θ 2 with the second extension portion X2. The second extension portion X2 and the second branch portion Y2 respectively overlap the second semiconductor channel layer SC2. Therefore, the channel region R5 has two separate active regions P3 and overlaps the second extension portion X2 and the second branch portion Y2, respectively. , So the leakage current problem can be reduced.

源極區R1、汲極區R3、源極區R4以及汲極區R6接受過重摻雜製程，因此源極區R1、汲極區R3、源極區R4以及汲極區R6屬於重摻雜區P1。在一些實施例中，重摻雜區P1的摻雜濃度為1018~1020atom/cm3。在一些實施例中，重摻雜區P1的片電阻值

Figure 107134629-A0305-02-0010-1
104Ω/Square。 The source region R1, the drain region R3, the source region R4, and the drain region R6 undergo an overdoping process, so the source region R1, the drain region R3, the source region R4, and the drain region R6 are heavily doped regions P1. In some embodiments, the doping concentration of the heavily doped region P1 is 10 18 -10 20 atom/cm 3 . In some embodiments, the sheet resistance value of the heavily doped region P1
Figure 107134629-A0305-02-0010-1
10 4 Ω/Square.

第一半導體通道層SC1的汲極區R3連接第二半導體通道層SC2的源極區R4。 The drain region R3 of the first semiconductor channel layer SC1 is connected to the source region R4 of the second semiconductor channel layer SC2.

請參考圖1E與圖2，形成層間介電層ILD於第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2上。 Please refer to FIGS. 1E and 2 to form an interlayer dielectric layer ILD on the first scan line SL1, the second scan line SL2, the first gate G1 and the second gate G2.

形成第一源極S1、資料線DL、第一汲極D1以及第二汲極D2於層間介電層ILD上。第一源極S1電性連接資料線DL與第一半導體通道層SC1，第一汲極D1與第二汲極D2分別電性連接第一半導體通道層SC1與第二半導體通道層SC2。在本實施例中，層間介電層ILD具有開口H1、開口H2以及開口H3，第一源極S1透過開口H1而與第一半導體通道層SC1的源極區R1電性連接，第一汲極D1與第二汲極D2透過開口H2以及開口H3分別電性連接第一半導體通道層SC1的汲極區R3與第二半導體通道層SC2的汲極區R6。 A first source S1, a data line DL, a first drain D1, and a second drain D2 are formed on the interlayer dielectric layer ILD. The first source electrode S1 is electrically connected to the data line DL and the first semiconductor channel layer SC1, and the first drain electrode D1 and the second drain electrode D2 are electrically connected to the first semiconductor channel layer SC1 and the second semiconductor channel layer SC2, respectively. In this embodiment, the interlayer dielectric layer ILD has an opening H1, an opening H2, and an opening H3. The first source S1 is electrically connected to the source region R1 of the first semiconductor channel layer SC1 through the opening H1, and the first drain D1 and the second drain D2 are electrically connected to the drain region R3 of the first semiconductor channel layer SC1 and the drain region R6 of the second semiconductor channel layer SC2 through the opening H2 and the opening H3, respectively.

至此，第一主動元件T1與第二主動元件T2大致完成。第一主動元件T1與第二主動元件T2位於第一掃描線SL1與第二掃描線SL2之間。第一主動元件T1包括第一半導體通道層SC1、第一閘極G1、第一源極S1以及第一汲極D1。第一閘極G1重疊於第一半導體通道層SC1，且電性連接第一掃描線SL1。第一源極S1電性連接資料線DL與第一半導體通道層SC1。第一汲極D1電性連接第一半導體通道層SC1。第二主動元件T2包括第二半導體通道層SC2、第二閘極G2以及第二汲極D2。第一半導體通道層SC1連接第二半導體通道層SC2的源極區R4，其中第一半導體通道層SC1以及第二半導體通道層SC2屬於同一膜層。第二閘極G2重疊於第二半導體通道層SC2，且電性連接第二掃描線SL2。第二汲極D2電性連接第二半導體通道層SC2。 So far, the first active element T1 and the second active element T2 are substantially completed. The first active element T1 and the second active element T2 are located between the first scan line SL1 and the second scan line SL2. The first active element T1 includes a first semiconductor channel layer SC1, a first gate G1, a first source S1, and a first drain D1. The first gate G1 overlaps the first semiconductor channel layer SC1 and is electrically connected to the first scan line SL1. The first source electrode S1 is electrically connected to the data line DL and the first semiconductor channel layer SC1. The first drain D1 is electrically connected to the first semiconductor channel layer SC1. The second active element T2 includes a second semiconductor channel layer SC2, a second gate G2, and a second drain D2. The first semiconductor channel layer SC1 is connected to the source region R4 of the second semiconductor channel layer SC2, where the first semiconductor channel layer SC1 and the second semiconductor channel layer SC2 belong to the same film layer. The second gate G2 overlaps the second semiconductor channel layer SC2 and is electrically connected to the second scan line SL2. The second drain D2 is electrically connected to the second semiconductor channel layer SC2.

請參考圖1F與圖2，形成第一絕緣層I1於第一源極S1、 第一汲極D1、第二汲極D2、資料線DL以及層間介電層ILD上。形成第一共通電極C1以及第二共通電極C2於第一絕緣層I1上。 Please refer to FIGS. 1F and 2 to form a first insulating layer I1 on the first source S1 On the first drain D1, the second drain D2, the data line DL, and the interlayer dielectric layer ILD. The first common electrode C1 and the second common electrode C2 are formed on the first insulating layer I1.

在本實施例中，選擇性的在形成第一共通電極C1以及第二共通電極C2之後形成第二絕緣層I2。形成第一畫素電極PE1與第二畫素電極PE2於第二絕緣層I2上，第一開口OP1以及第二開口OP2貫穿第一絕緣層I1與第二絕緣層I2。第一畫素電極PE1與第二畫素電極PE2分別透過第一開口OP1以及第二開口OP2而電性連接第一汲極D1與第二汲極D2。換句話說，本實施例是以共通電極位於基板SB與畫素電極之間的結構為例，但本發明不以此為限。在其他實施例中，畫素電極位於基板SB與共通電極之間。 In this embodiment, the second insulating layer I2 is selectively formed after the first common electrode C1 and the second common electrode C2 are formed. The first pixel electrode PE1 and the second pixel electrode PE2 are formed on the second insulating layer I2, and the first opening OP1 and the second opening OP2 penetrate the first insulating layer I1 and the second insulating layer I2. The first pixel electrode PE1 and the second pixel electrode PE2 are electrically connected to the first drain D1 and the second drain D2 through the first opening OP1 and the second opening OP2, respectively. In other words, this embodiment takes the structure in which the common electrode is located between the substrate SB and the pixel electrode as an example, but the invention is not limited thereto. In other embodiments, the pixel electrode is located between the substrate SB and the common electrode.

至此，主動元件基板10大致完成。主動元件基板10包括基板SB、第一掃描線SL1、第二掃描線SL2、資料線DL、第一主動元件T1、第一共通電極C1、第二共通電極C2、第一畫素電極PE1、第二主動元件T2以及第二畫素電極PE2。 At this point, the active device substrate 10 is substantially completed. The active element substrate 10 includes a substrate SB, a first scan line SL1, a second scan line SL2, a data line DL, a first active element T1, a first common electrode C1, a second common electrode C2, a first pixel electrode PE1, a first Two active elements T2 and the second pixel electrode PE2.

基於上述，第一主動元件T1的第一半導體通道層SC1連接第二主動元件T2的第二半導體通道層SC2，因此第一主動元件T1與第二主動元件T2皆可以藉由同一條資料線DL驅動。相較於每個主動元件皆連接至一條資料線的主動元件基板，本實施例的主動元件基板10可以使用較少的資料線，增加了第一主動元件T1與第二主動元件T2之設計空間，能提升畫素的開口率以及解析度的設計極限。 Based on the above, the first semiconductor channel layer SC1 of the first active element T1 is connected to the second semiconductor channel layer SC2 of the second active element T2, so both the first active element T1 and the second active element T2 can pass the same data line DL drive. Compared to an active device substrate where each active device is connected to one data line, the active device substrate 10 of this embodiment can use fewer data lines, increasing the design space of the first active device T1 and the second active device T2 , Can increase the pixel aperture ratio and the design limit of resolution.

圖3是依照本發明的一實施例的一種主動元件基板的剖 面示意圖。在此必須說明的是，圖3的實施例沿用圖2的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 3 is a cross-section of an active device substrate according to an embodiment of the invention Schematic diagram. It must be noted here that the embodiment of FIG. 3 uses the element numbers and partial contents of the embodiment of FIG. 2, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

圖3的主動元件基板20與圖2的主動元件基板10的主要差異在於：主動元件基板20的第一半導體通道層SC1與第二半導體通道層SC2的材料包括金屬氧化物。 The main difference between the active device substrate 20 of FIG. 3 and the active device substrate 10 of FIG. 2 is that the materials of the first semiconductor channel layer SC1 and the second semiconductor channel layer SC2 of the active device substrate 20 include metal oxides.

在本實施例中，沒有對半導體層進行重摻雜製程以及輕摻雜製程，而是對半導體層SC進行電漿處理製程以形成第一半導體通道層SC1與第二半導體通道層SC2。 In this embodiment, the semiconductor layer is not subjected to a heavy doping process and a lightly doping process, but the semiconductor layer SC is subjected to a plasma process to form a first semiconductor channel layer SC1 and a second semiconductor channel layer SC2.

電漿處理製程例如是以第一閘極G1以及第二閘極G2為罩幕而進行。舉例來說，形成絕緣層以及導電材料層於半導體層SC上，接著蝕刻導電材料層以形成第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2，並蝕刻絕緣層以形成閘極絕緣層GI，閘極絕緣層GI暴露出半導體層SC，其中閘極絕緣層GI例如與第一閘極G1以及第二閘極G2對齊，接著以第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2為罩幕而對半導體層SC進行電漿處理製程。在其他實施例中，電漿處理製程是在形成第一閘極G1以及第二閘極G2之前進行，且電漿處理製程是以額外形成於半導體層SC上的遮罩圖案(未繪出)作為遮罩而進行。 The plasma processing process is performed with the first gate G1 and the second gate G2 as masks, for example. For example, forming an insulating layer and a conductive material layer on the semiconductor layer SC, and then etching the conductive material layer to form the first scan line SL1, the second scan line SL2, the first gate G1 and the second gate G2, and etching An insulating layer to form a gate insulating layer GI, the gate insulating layer GI exposes the semiconductor layer SC, wherein the gate insulating layer GI is aligned with the first gate G1 and the second gate G2, for example, and then the first scan line SL1 The second scan line SL2, the first gate G1, and the second gate G2 serve as masks to perform a plasma processing process on the semiconductor layer SC. In other embodiments, the plasma processing process is performed before forming the first gate G1 and the second gate G2, and the plasma processing process is a mask pattern (not shown) additionally formed on the semiconductor layer SC Perform as a mask.

第一半導體通道層SC1包括重疊於第一閘極G1的通道 區R2，以及分別位於通道區R2的兩側的源極區R1與汲極區R3。源極區R1與汲極區R3的電阻率小於通道區R2的電阻率。 The first semiconductor channel layer SC1 includes a channel overlapping the first gate G1 Region R2, and source region R1 and drain region R3 located on both sides of channel region R2, respectively. The resistivity of the source region R1 and the drain region R3 is smaller than that of the channel region R2.

第二半導體通道層SC2包括重疊於第二閘極G2的通道區R5，以及分別位於通道區R5的兩側的源極區R4與汲極區R6。源極區R4與汲極區R6的電阻率小於通道區R5的電阻率。 The second semiconductor channel layer SC2 includes a channel region R5 overlapping the second gate G2, and a source region R4 and a drain region R6 located on both sides of the channel region R5, respectively. The resistivity of the source region R4 and the drain region R6 is smaller than that of the channel region R5.

基於上述，第一主動元件T1的第一半導體通道層SC1連接第二主動元件T2的第二半導體通道層SC2，因此第一主動元件T1與第二主動元件T2皆可以藉由同一條資料線DL驅動。相較於每個主動元件皆連接至一條資料線的主動元件基板，本實施例的主動元件基板20可以使用較少的資料線，增加了第一主動元件T1與第二主動元件T2之設計空間，能提升畫素的開口率以及解析度的設計極限。 Based on the above, the first semiconductor channel layer SC1 of the first active element T1 is connected to the second semiconductor channel layer SC2 of the second active element T2, so both the first active element T1 and the second active element T2 can pass the same data line DL drive. Compared to an active device substrate where each active device is connected to one data line, the active device substrate 20 of this embodiment can use fewer data lines, increasing the design space of the first active device T1 and the second active device T2 , Can increase the pixel aperture ratio and the design limit of resolution.

圖4是依照本發明的一實施例的一種主動元件基板的上視示意圖。圖5是依照本發明的一實施例的一種主動元件基板的剖面示意圖。圖5對應於圖4的剖面線BB’。在此必須說明的是，圖4、圖5的實施例沿用圖2的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 4 is a schematic top view of an active device substrate according to an embodiment of the invention. 5 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention. Fig. 5 corresponds to the section line BB' of Fig. 4. It must be noted here that the embodiments of FIG. 4 and FIG. 5 follow the element numbers and partial contents of the embodiment of FIG. 2, wherein the same or similar reference numbers are used to indicate the same or similar elements, and the same technical content is omitted Instructions. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

圖4的主動元件基板30與圖2的主動元件基板10的主要差異在於：主動元件基板30更包括第三掃描線SL3以及第三主動元件T3，其中第三主動元件T3包括第三半導體通道層SC3、 第三閘極G3以及第三汲極D3。 The main difference between the active device substrate 30 of FIG. 4 and the active device substrate 10 of FIG. 2 is that the active device substrate 30 further includes a third scan line SL3 and a third active device T3, wherein the third active device T3 includes a third semiconductor channel layer SC3, The third gate G3 and the third drain D3.

在本實施例中，圖案化第一金屬層M1以形成第一掃描線SL1、第二掃描線SL2、第三掃描線SL3、第一閘極G1、第二閘極G2以及第三閘極G3。第一掃描線SL1、第二掃描線SL2、第三掃描線SL3、第一閘極G1、第二閘極G2以及第三閘極G3於閘極絕緣層GI上，第一閘極G1電性連接第一掃描線SL1，第二閘極G2電性連接第二掃描線SL2，第三閘極G3電性連接第三掃描線SL3。 In this embodiment, the first metal layer M1 is patterned to form a first scan line SL1, a second scan line SL2, a third scan line SL3, a first gate G1, a second gate G2, and a third gate G3 . The first scan line SL1, the second scan line SL2, the third scan line SL3, the first gate G1, the second gate G2, and the third gate G3 are on the gate insulating layer GI, and the first gate G1 is electrically The first scan line SL1 is connected, the second gate G2 is electrically connected to the second scan line SL2, and the third gate G3 is electrically connected to the third scan line SL3.

第一掃描線SL1、第二掃描線SL2、第三掃描線SL3各自包括互相平行的第一導線L1與第二導線L2。第一閘極G1、第二閘極G2以及第三閘極G3各自包括互相分離的第一部分Z1與第二部分Z2，第一部分Z1與第二部分Z2分別電性連接至第一導線L1與第二導線L2。 The first scan line SL1, the second scan line SL2, and the third scan line SL3 each include a first conductive line L1 and a second conductive line L2 that are parallel to each other. The first gate G1, the second gate G2, and the third gate G3 each include a first portion Z1 and a second portion Z2 that are separated from each other. The first portion Z1 and the second portion Z2 are electrically connected to the first wire L1 and the second Two wire L2.

對半導體層SC進行處理製程，以形成第一半導體通道層SC1、第二半導體通道層SC2以及第三半導體通道層SC3，在本實施例中，處理製程例如類似於圖1C的重摻雜製程，且對半導體層SC進行類似於圖1C的重摻雜製程以及類似於圖1D的輕摻雜製程，以形成第一半導體通道層SC1、第二半導體通道層SC2以及第三半導體通道層SC3，但本發明不以此為限。在其他實施例中，半導體層SC的材料包括金屬氧化物，處理製程為電漿處理製程。在本實施例中，第一半導體通道層SC1、第二半導體通道層SC2以及第三半導體通道層SC3屬於同一膜層。第三半導體通道層SC3 包括依序連接的源極區R7、通道區R8以及汲極區R9。第三閘極G3重疊於第三半導體通道層SC3的通道區R8。 The semiconductor layer SC is processed to form a first semiconductor channel layer SC1, a second semiconductor channel layer SC2, and a third semiconductor channel layer SC3. In this embodiment, the processing process is similar to the heavily doped process of FIG. 1C, And performing a heavily doped process similar to that of FIG. 1C and a lightly doped process similar to that of FIG. 1D on the semiconductor layer SC to form a first semiconductor channel layer SC1, a second semiconductor channel layer SC2, and a third semiconductor channel layer SC3, but The invention is not limited to this. In other embodiments, the material of the semiconductor layer SC includes metal oxide, and the processing process is a plasma processing process. In this embodiment, the first semiconductor channel layer SC1, the second semiconductor channel layer SC2, and the third semiconductor channel layer SC3 belong to the same film layer. Third semiconductor channel layer SC3 It includes a source region R7, a channel region R8 and a drain region R9 connected in sequence. The third gate G3 overlaps the channel region R8 of the third semiconductor channel layer SC3.

第一半導體通道層SC1、第二半導體通道層SC2以及第三半導體通道層SC3依序連接。舉例來說，第一半導體通道層SC1的汲極區R3連接第二半導體通道層SC2的源極區R4，第二半導體通道層SC2的汲極區R6連接第三半導體通道層SC3的源極區R7。 The first semiconductor channel layer SC1, the second semiconductor channel layer SC2, and the third semiconductor channel layer SC3 are sequentially connected. For example, the drain region R3 of the first semiconductor channel layer SC1 is connected to the source region R4 of the second semiconductor channel layer SC2, and the drain region R6 of the second semiconductor channel layer SC2 is connected to the source region of the third semiconductor channel layer SC3 R7.

第三汲極D3透過開口H4電性連接第三半導體通道層SC3的汲極區R9。第三畫素電極PE3透過開口OP3電性連接第三汲極D3。第一共通電極C1、第二共通電極C2以及第三共通電極C3重疊於第一畫素電極PE1、第二畫素電極PE2與第三畫素電極PE3。 The third drain D3 is electrically connected to the drain region R9 of the third semiconductor channel layer SC3 through the opening H4. The third pixel electrode PE3 is electrically connected to the third drain electrode D3 through the opening OP3. The first common electrode C1, the second common electrode C2, and the third common electrode C3 overlap the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

基於上述，第一主動元件T1的第一半導體通道層SC1連接第二主動元件T2的第二半導體通道層SC2，且第二主動元件T2的第二半導體通道層SC2連接第三主動元件T3的第三半導體通道層SC3，因此第一主動元件T1、第二主動元件T2與第三主動元件T3皆可以藉由同一條資料線DL驅動。相較於每個主動元件皆連接至一條資料線的主動元件基板，本實施例的主動元件基板30可以使用較少的資料線，增加了第一主動元件T1、第二主動元件T2與第三主動元件T3之設計空間，能提升畫素的開口率以及解析度的設計極限。 Based on the above, the first semiconductor channel layer SC1 of the first active device T1 is connected to the second semiconductor channel layer SC2 of the second active device T2, and the second semiconductor channel layer SC2 of the second active device T2 is connected to the third semiconductor device T3 Since the three semiconductor channel layers SC3, the first active device T1, the second active device T2, and the third active device T3 can all be driven by the same data line DL. Compared to an active device substrate in which each active device is connected to one data line, the active device substrate 30 of this embodiment can use fewer data lines, adding the first active device T1, the second active device T2, and the third The design space of the active element T3 can increase the pixel aperture ratio and the design limit of resolution.

雖然在本實施例中是以三個主動元件的半導體通道層依 序連接為例，但本發明不以此為限。在其他實施例中，可以是超過三個主動元件的半導體通道層依序連接。 Although in this embodiment, the semiconductor channel layer with three active devices Sequential connection is an example, but the invention is not limited to this. In other embodiments, the semiconductor channel layers of more than three active devices may be connected in sequence.

圖6A~圖6D是依照本發明的一實施例的一種主動元件基板的製造方法的上視示意圖。圖7是依照本發明的一實施例的一種主動元件基板的剖面示意圖。圖7對應於圖6D的剖面線CC’。 6A-6D are schematic top views of a method for manufacturing an active device substrate according to an embodiment of the invention. 7 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention. Fig. 7 corresponds to the section line CC' of Fig. 6D.

在此必須說明的是，圖6A~圖6D、圖7的實施例沿用圖1A~圖1F、圖2的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 It should be noted here that the embodiments of FIGS. 6A to 6D and FIG. 7 follow the element labels and partial contents of the embodiments of FIGS. 1A to 1F and 2, wherein the same or similar reference numerals are used to indicate the same or similar Components, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

圖6A~圖6D之實施例與圖1A~圖1F之實施例的主要差異在於：在圖6A~圖6D之主動元件基板40的製造方法中，處理製程係在形成第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2於閘極絕緣層GI上之前進行。 The main difference between the embodiments of FIGS. 6A-6D and the embodiments of FIGS. 1A-1F is that in the method of manufacturing the active device substrate 40 of FIGS. 6A-6D, the processing process is to form the first scan lines SL1, The second scan line SL2, the first gate G1, and the second gate G2 are performed before the gate insulating layer GI.

圖6A延續圖1B的製造步驟，請參考圖6A與圖7，對半導體層SC進行處理製程，處理製程例如為重摻雜製程，以於半導體層SC中形成重摻雜區P1。 FIG. 6A continues the manufacturing steps of FIG. 1B. Please refer to FIGS. 6A and 7 to perform a processing process on the semiconductor layer SC. The processing process is, for example, a heavily doped process to form a heavily doped region P1 in the semiconductor layer SC.

在本實施例中，例如是先於半導體層SC上形成遮罩圖案(未繪出)，以於半導體層SC中定義出欲形成重摻雜區P1的區域，接著再移除遮罩圖案。遮罩圖案可以是在閘極絕緣層GI之前形成，也可以是在閘極絕緣層GI之後形成，本發明並未特別限制。 In this embodiment, for example, a mask pattern (not shown) is first formed on the semiconductor layer SC to define a region in the semiconductor layer SC where the heavily doped region P1 is to be formed, and then the mask pattern is removed. The mask pattern may be formed before the gate insulating layer GI or may be formed after the gate insulating layer GI, and the present invention is not particularly limited.

請參考圖6B與圖7，形成第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2於閘極絕緣層GI上。第一閘 極G1以及第二閘極G2重疊於半導體層SC，且重疊的面積小於半導體層SC未接受重摻雜製程之面積。在形成第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2於閘極絕緣層GI上之後，以第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2為罩幕，對半導體層SC進行輕摻雜製程，以於半導體層SC中形成輕摻雜區P2。 6B and 7, the first scan line SL1, the second scan line SL2, the first gate G1, and the second gate G2 are formed on the gate insulating layer GI. First brake The electrode G1 and the second gate G2 overlap the semiconductor layer SC, and the overlapped area is smaller than the area of the semiconductor layer SC not receiving the heavy doping process. After forming the first scan line SL1, the second scan line SL2, the first gate G1, and the second gate G2 on the gate insulating layer GI, the first scan line SL1, the second scan line SL2, the first gate The electrode G1 and the second gate G2 are masks, and a light doping process is performed on the semiconductor layer SC to form a lightly doped region P2 in the semiconductor layer SC.

在本實施例中，形成第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2於閘極絕緣層GI上的同時，會形成電容電極CE於閘極絕緣層GI上，換句話說，電容電極CE與第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2屬於同一膜層。電容電極CE的延伸方向、第一掃描線SL1的延伸方向以及第二掃描線SL2的延伸方向實質上相同，但本發明不以此為限。 In this embodiment, when the first scan line SL1, the second scan line SL2, the first gate G1, and the second gate G2 are formed on the gate insulating layer GI, a capacitor electrode CE is formed on the gate insulating layer On the GI, in other words, the capacitor electrode CE and the first scan line SL1, the second scan line SL2, the first gate G1, and the second gate G2 belong to the same film layer. The extending direction of the capacitor electrode CE, the extending direction of the first scanning line SL1 and the extending direction of the second scanning line SL2 are substantially the same, but the invention is not limited thereto.

在本實施例中，由於電容電極CE與第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2屬於同一膜層，且電容電極CE重疊於半導體層SC(也可以說電容電極CE重疊於第一半導體通道層SC1及/或第二半導體通道層SC2)，因此，輕摻雜製程是以電容電極CE與第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2為罩幕而進行。在本實施例中，電容電極CE可以與第一半導體通道層SC1及/或第二半導體通道層SC2構成電容。 In this embodiment, the capacitor electrode CE and the first scan line SL1, the second scan line SL2, the first gate G1 and the second gate G2 belong to the same film layer, and the capacitor electrode CE overlaps the semiconductor layer SC (also It can be said that the capacitor electrode CE overlaps the first semiconductor channel layer SC1 and/or the second semiconductor channel layer SC2). Therefore, the light doping process is based on the capacitor electrode CE and the first scan line SL1, the second scan line SL2, the first The gate G1 and the second gate G2 are performed as a mask. In this embodiment, the capacitor electrode CE may form a capacitor with the first semiconductor channel layer SC1 and/or the second semiconductor channel layer SC2.

請參考圖6C與圖7，形成層間介電層ILD於第一掃描線 SL1、第二掃描線SL2、第一閘極G1、第二閘極G2以及電容電極CE上。 Please refer to FIGS. 6C and 7 to form an interlayer dielectric layer ILD on the first scan line SL1, the second scan line SL2, the first gate G1, the second gate G2, and the capacitor electrode CE.

形成第一源極S1、資料線DL、第一汲極D1以及第二汲極D2於層間介電層ILD上。第一源極S1電性連接資料線DL與第一半導體通道層SC1，第一汲極D1與第二汲極D2分別電性連接第一半導體通道層SC1與第二半導體通道層SC2。在本實施例中，層間介電層ILD具有開口H1、開口H2以及開口H3，第一源極S1透過開口H1而電性連接第一半導體通道層SC1的源極區R1，第一汲極D1與第二汲極D2透過開口H2以及開口H3分別電性連接第一半導體通道層SC1的汲極區R3與第二半導體通道層SC2的汲極區R6。 A first source S1, a data line DL, a first drain D1, and a second drain D2 are formed on the interlayer dielectric layer ILD. The first source electrode S1 is electrically connected to the data line DL and the first semiconductor channel layer SC1, and the first drain electrode D1 and the second drain electrode D2 are electrically connected to the first semiconductor channel layer SC1 and the second semiconductor channel layer SC2, respectively. In this embodiment, the interlayer dielectric layer ILD has an opening H1, an opening H2, and an opening H3, the first source S1 is electrically connected to the source region R1 of the first semiconductor channel layer SC1 through the opening H1, and the first drain D1 The second drain D2 is electrically connected to the drain region R3 of the first semiconductor channel layer SC1 and the drain region R6 of the second semiconductor channel layer SC2 through the opening H2 and the opening H3, respectively.

至此，第一主動元件T1與第二主動元件T2大致完成。 So far, the first active element T1 and the second active element T2 are substantially completed.

請參考圖6D與圖7，形成第一絕緣層I1於第一源極S1、第一汲極D1、第二汲極D2、資料線DL以及層間介電層ILD上。形成第一共通電極C1以及第二共通電極C2於第一絕緣層I1上。 6D and 7, a first insulating layer I1 is formed on the first source S1, the first drain D1, the second drain D2, the data line DL, and the interlayer dielectric layer ILD. The first common electrode C1 and the second common electrode C2 are formed on the first insulating layer I1.

在本實施例中，選擇性的在形成第一共通電極C1以及第二共通電極C2之後形成第二絕緣層I2。在形成第二絕緣層I2後形成第一畫素電極PE1與第二畫素電極PE2。第一畫素電極PE1與第二畫素電極PE2位於第二絕緣層I2上，第一開口OP1以及第二開口OP2貫穿第一絕緣層I1與第二絕緣層I2。換句話說，本實施例是以共通電極位於基板SB與畫素電極之間的結構為例，但本發明不以此為限。在其他實施例中，畫素電極位於基板SB與共通 電極之間。 In this embodiment, the second insulating layer I2 is selectively formed after the first common electrode C1 and the second common electrode C2 are formed. After forming the second insulating layer I2, the first pixel electrode PE1 and the second pixel electrode PE2 are formed. The first pixel electrode PE1 and the second pixel electrode PE2 are located on the second insulating layer I2, and the first opening OP1 and the second opening OP2 penetrate the first insulating layer I1 and the second insulating layer I2. In other words, this embodiment takes the structure in which the common electrode is located between the substrate SB and the pixel electrode as an example, but the invention is not limited thereto. In other embodiments, the pixel electrode is located on the substrate SB and is common Between electrodes.

至此，主動元件基板40大致完成。主動元件基板40包括基板SB、第一掃描線SL1、第二掃描線SL2、資料線DL、第一主動元件T1、第一共通電極C1、第二共通電極C2、第一畫素電極PE1、第二主動元件T2、第二畫素電極PE2以及電容電極CE。 At this point, the active device substrate 40 is substantially completed. The active element substrate 40 includes a substrate SB, a first scan line SL1, a second scan line SL2, a data line DL, a first active element T1, a first common electrode C1, a second common electrode C2, a first pixel electrode PE1, a first Two active elements T2, a second pixel electrode PE2 and a capacitor electrode CE.

基於上述，第一主動元件T1的第一半導體通道層SC1連接第二主動元件T2的第二半導體通道層SC2，因此第一主動元件T1與第二主動元件T2皆可以藉由同一條資料線DL驅動。相較於每個主動元件皆連接至一條資料線的主動元件基板，本實施例的主動元件基板40可以使用較少的資料線，增加了第一主動元件T1與第二主動元件T2之設計空間，能提升畫素的開口率以及解析度的設計極限。 Based on the above, the first semiconductor channel layer SC1 of the first active element T1 is connected to the second semiconductor channel layer SC2 of the second active element T2, so both the first active element T1 and the second active element T2 can pass the same data line DL drive. Compared to an active device substrate where each active device is connected to one data line, the active device substrate 40 of this embodiment can use fewer data lines, increasing the design space of the first active device T1 and the second active device T2 , Can increase the pixel aperture ratio and the design limit of resolution.

圖8是依照本發明的一實施例的一種主動元件基板的剖面示意圖。在此必須說明的是，圖8的實施例沿用圖7的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 8 follows the element numbers and partial contents of the embodiment of FIG. 7, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

圖8的主動元件基板50與圖7的主動元件基板40的主要差異在於：主動元件基板50的第一半導體通道層SC1與第二半導體通道層SC2的材料包括金屬氧化物。 The main difference between the active device substrate 50 of FIG. 8 and the active device substrate 40 of FIG. 7 is that the materials of the first semiconductor channel layer SC1 and the second semiconductor channel layer SC2 of the active device substrate 50 include metal oxides.

在本實施例中，閘極絕緣層GI暴露出半導體層，閘極絕緣層GI例如與第一閘極G1、第二閘極G2以及電容電極CE對齊。 在本實施例中，沒有對半導體層進行重摻雜製程以及輕摻雜製程，而是對半導體層進行電漿處理製程以形成第一半導體通道層SC1與第二半導體通道層SC2。 In this embodiment, the gate insulating layer GI exposes the semiconductor layer, and the gate insulating layer GI is aligned with the first gate G1, the second gate G2, and the capacitor electrode CE, for example. In this embodiment, the semiconductor layer is not heavily doped and lightly doped, but the semiconductor layer is subjected to a plasma process to form the first semiconductor channel layer SC1 and the second semiconductor channel layer SC2.

在本實施例中，電漿處理製程例是以額外形成於半導體層SC上的遮罩圖案作為遮罩而進行。舉例來說，於形成第一閘極G1、第二閘極G2以及電容電極CE之前，先形成遮罩圖案於半導體層SC上以定義出欲進行電漿處理製程的區域(源極區R1、R4與汲極區R3、R6)，進行電漿處理製程後再形成第一閘極G1、第二閘極G2以及電容電極CE。前述之遮罩圖案例如於進行電漿處理製程之後移除前述之遮罩圖案。 In this embodiment, the plasma processing process example is performed using a mask pattern additionally formed on the semiconductor layer SC as a mask. For example, before forming the first gate G1, the second gate G2, and the capacitor electrode CE, a mask pattern is formed on the semiconductor layer SC to define a region (source region R1) to be subjected to a plasma processing process R4 and the drain regions R3, R6), after the plasma treatment process is performed, the first gate G1, the second gate G2, and the capacitor electrode CE are formed. For example, the aforementioned mask pattern is removed after performing the plasma processing process.

第一半導體通道層SC1包括重疊於第一閘極G1的通道區R2，以及分別位於通道區R2的兩側的源極區R1與汲極區R3。源極區R1與汲極區R3的電阻率小於通道區R2的電阻率。 The first semiconductor channel layer SC1 includes a channel region R2 overlapping the first gate G1, and a source region R1 and a drain region R3 located on both sides of the channel region R2. The resistivity of the source region R1 and the drain region R3 is smaller than that of the channel region R2.

第二半導體通道層SC2包括重疊於第二閘極G2的通道區R5，以及分別位於通道區R5的兩側的源極區R4與汲極區R6。源極區R4與汲極區R6的電阻率小於通道區R5的電阻率。 The second semiconductor channel layer SC2 includes a channel region R5 overlapping the second gate G2, and a source region R4 and a drain region R6 located on both sides of the channel region R5, respectively. The resistivity of the source region R4 and the drain region R6 is smaller than that of the channel region R5.

基於上述，第一主動元件T1的第一半導體通道層SC1連接第二主動元件T2的第二半導體通道層SC2，因此第一主動元件T1與第二主動元件T2皆可以藉由同一條資料線DL驅動。相較於每個主動元件皆連接至一條資料線的主動元件基板，本實施例的主動元件基板50可以使用較少的資料線，增加了第一主動元件T1與第二主動元件T2之設計空間，能提升畫素的開口率以及 解析度的設計極限。 Based on the above, the first semiconductor channel layer SC1 of the first active element T1 is connected to the second semiconductor channel layer SC2 of the second active element T2, so both the first active element T1 and the second active element T2 can pass the same data line DL drive. Compared to an active device substrate where each active device is connected to one data line, the active device substrate 50 of this embodiment can use fewer data lines, increasing the design space of the first active device T1 and the second active device T2 , Can improve the pixel aperture ratio and The design limit of resolution.

圖9是依照本發明的一實施例的一種主動元件基板的剖面示意圖。在此必須說明的是，圖9的實施例沿用圖7的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 9 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 9 uses the element numbers and partial contents of the embodiment of FIG. 7, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

圖9的主動元件基板60與圖7的主動元件基板40的主要差異在於：第一汲極D1重疊於電容電極CE。 The main difference between the active device substrate 60 of FIG. 9 and the active device substrate 40 of FIG. 7 is that the first drain electrode D1 overlaps the capacitor electrode CE.

在本實施例中，電容電極CE除了可以與第一半導體通道層SC1及/或第二半導體通道層SC2構成電容之外，還可以與第一汲極D1構成電容。 In this embodiment, the capacitor electrode CE can form a capacitor with the first drain D1 in addition to the first semiconductor channel layer SC1 and/or the second semiconductor channel layer SC2.

基於上述，本實施例的電容電極CE可以提供較高的儲存電容。 Based on the above, the capacitor electrode CE of this embodiment can provide a higher storage capacitance.

圖10是依照本發明的一實施例的一種主動元件基板的剖面示意圖。在此必須說明的是，圖10的實施例沿用圖8的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 10 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 10 uses the element numbers and partial contents of the embodiment of FIG. 8, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

圖10的主動元件基板70與圖8的主動元件基板50的主要差異在於：第一汲極D1重疊於電容電極CE。 The main difference between the active device substrate 70 of FIG. 10 and the active device substrate 50 of FIG. 8 is that the first drain electrode D1 overlaps the capacitor electrode CE.

在本實施例中，電容電極CE除了可以與第一半導體通道層SC1及/或第二半導體通道層SC2構成電容之外，還可以與第一 汲極D1構成電容。 In this embodiment, in addition to forming capacitance with the first semiconductor channel layer SC1 and/or the second semiconductor channel layer SC2, the capacitor electrode CE may also Drain D1 constitutes a capacitor.

基於上述，本實施例的電容電極CE可以提供較高的儲存電容。 Based on the above, the capacitor electrode CE of this embodiment can provide a higher storage capacitance.

圖11A~圖11G是依照本發明的一實施例的一種主動元件基板的製造方法的上視示意圖。圖12是依照本發明的一實施例的一種主動元件基板的剖面示意圖。圖12對應於圖11G的剖面線DD’。 11A-11G are schematic top views of a method for manufacturing an active device substrate according to an embodiment of the invention. 12 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention. Fig. 12 corresponds to the section line DD' of Fig. 11G.

在此必須說明的是，圖11A~圖11G、圖12的實施例沿用圖1A~圖1F、圖2的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 It must be noted here that the embodiments of FIGS. 11A to 11G and FIG. 12 continue to use the element labels and partial contents of the embodiments of FIGS. 1A to 1F and 2, wherein the same or similar reference numbers are used to indicate the same or similar Components, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

圖11G、圖12之主動元件基板80與圖1F、圖2之主動元件基板10的主要差異在於：主動元件基板80更包括第一島狀結構IS1以及第二島狀結構IS2。 The main difference between the active device substrate 80 of FIGS. 11G and 12 and the active device substrate 10 of FIGS. 1F and 2 is that the active device substrate 80 further includes a first island structure IS1 and a second island structure IS2.

圖11A延續圖1D的製造步驟，請參考圖11A與圖12，形成層間介電層ILD於第一掃描線SL1、第二掃描線SL2、第一閘極G1以及第二閘極G2上。層間介電層ILD具有開口H1、開口H2以及開口H3。形成第二金屬層M2於層間介電層ILD上。 FIG. 11A continues the manufacturing steps of FIG. 1D. Please refer to FIGS. 11A and 12 to form an interlayer dielectric layer ILD on the first scan line SL1, the second scan line SL2, the first gate G1, and the second gate G2. The interlayer dielectric layer ILD has openings H1, H2, and H3. A second metal layer M2 is formed on the interlayer dielectric layer ILD.

請參考圖11B、圖11C，形成第一感光材料RS1於第二金屬層M2上，圖案化第一感光材料RS1，接著固化所述圖案化的第一感光材料RS1以形成第一島狀結構IS1以及第二島狀結構IS2 於第二金屬層M2上。換句話說，第一島狀結構IS1以及第二島狀結構IS2的材料包括固化的感光材料。第一島狀結構IS1以及第二島狀結構IS2分別對應開口H2以及開口H3設置。 11B and 11C, a first photosensitive material RS1 is formed on the second metal layer M2, the first photosensitive material RS1 is patterned, and then the patterned first photosensitive material RS1 is cured to form a first island-like structure IS1 And the second island structure IS2 On the second metal layer M2. In other words, the materials of the first island-shaped structure IS1 and the second island-shaped structure IS2 include cured photosensitive materials. The first island-shaped structure IS1 and the second island-shaped structure IS2 are respectively provided corresponding to the opening H2 and the opening H3.

請參考圖11D與圖12，形成圖案化的第二感光材料RS2於第二金屬層M2上。圖案化的第二感光材料RS2對應開口H1設置。在本實施例中，第一島狀結構IS1以及第二島狀結構IS2的固化程度例如大於圖案化的第二感光材料RS2的固化程度，因此，在形成圖案化的第二感光材料RS2的製程中(例如顯影製程)，第一島狀結構IS1以及第二島狀結構IS2比較不容易受到損傷。 Please refer to FIGS. 11D and 12 to form a patterned second photosensitive material RS2 on the second metal layer M2. The patterned second photosensitive material RS2 is provided corresponding to the opening H1. In this embodiment, the curing degree of the first island-shaped structure IS1 and the second island-shaped structure IS2 is, for example, greater than that of the patterned second photosensitive material RS2. Therefore, in the process of forming the patterned second photosensitive material RS2 In the middle (for example, the development process), the first island-shaped structure IS1 and the second island-shaped structure IS2 are less susceptible to damage.

請參考圖11E、11F與圖12，以圖案化的第二感光材料RS2、第一島狀結構IS1以及第二島狀結構IS2為罩幕圖案化第二金屬層M2以形成第一源極S1、資料線DL、第一汲極D1以及第二汲極D2。第一源極S1透過開口H1而電性連接第一半導體通道層SC1的源極區R1，第一汲極D1與第二汲極D2透過開口H2以及開口H3分別電性連接第一半導體通道層SC1的汲極區R3與第二半導體通道層SC2的汲極區R6。第一島狀結構IS1以及第二島狀結構IS2分別位於第一汲極D1以及第二汲極D2上方，圖案化的第二感光材料RS2位於資料線DL上方。第一島狀結構IS1於基板SB之垂直投影面積和第一汲極D1於基板SB之垂直投影面積實質相同，第二島狀結構IS2於基板SB之垂直投影面積和第二汲極D2於基板SB之垂直投影面積實質相同，圖案化的第二感光 材料RS2於基板SB之垂直投影面積和資料線DL於基板SB之垂直投影面積實質相同。 Please refer to FIGS. 11E, 11F and FIG. 12, the patterned second photosensitive material RS2, the first island-shaped structure IS1 and the second island-shaped structure IS2 are used as a mask to pattern the second metal layer M2 to form the first source electrode S1 , The data line DL, the first drain D1 and the second drain D2. The first source electrode S1 is electrically connected to the source region R1 of the first semiconductor channel layer SC1 through the opening H1, and the first drain electrode D1 and the second drain electrode D2 are electrically connected to the first semiconductor channel layer through the opening H2 and the opening H3, respectively The drain region R3 of SC1 and the drain region R6 of the second semiconductor channel layer SC2. The first island-shaped structure IS1 and the second island-shaped structure IS2 are respectively located above the first drain D1 and the second drain D2, and the patterned second photosensitive material RS2 is located above the data line DL. The vertical projection area of the first island-like structure IS1 on the substrate SB is substantially the same as the vertical projection area of the first drain D1 on the substrate SB, and the vertical projection area of the second island-like structure IS2 on the substrate SB and the second drain D2 on the substrate The vertical projection area of SB is substantially the same, and the patterned second photosensitive The vertical projection area of the material RS2 on the substrate SB and the vertical projection area of the data line DL on the substrate SB are substantially the same.

移除(或剝離)圖案化的第二感光材料RS2。在本實施例中，第一島狀結構IS1以及第二島狀結構IS2的固化程度例如大於圖案化的第二感光材料RS2的固化程度，在移除圖案化的第二感光材料RS2後，第一島狀結構IS1以及第二島狀結構IS2會殘留下來。 The patterned second photosensitive material RS2 is removed (or stripped). In this embodiment, the curing degree of the first island-shaped structure IS1 and the second island-shaped structure IS2 is, for example, greater than that of the patterned second photosensitive material RS2. After removing the patterned second photosensitive material RS2, the first An island structure IS1 and a second island structure IS2 will remain.

在本實施例中，形成第一島狀結構IS1、第二島狀結構IS2以及圖案化的第二感光材料RS2的製程包括了兩次圖案化製程，因此可以提升形成第一源極S1、資料線DL、第一汲極D1以及第二汲極D2之製程的解析極限，換句話說，第一源極S1、資料線DL、第一汲極D1以及第二汲極D2之間的距離可以較小。 In this embodiment, the process of forming the first island-shaped structure IS1, the second island-shaped structure IS2 and the patterned second photosensitive material RS2 includes two patterning processes, so the formation of the first source S1 can be improved The analytical limit of the process of the line DL, the first drain D1 and the second drain D2, in other words, the distance between the first source S1, the data line DL, the first drain D1 and the second drain D2 can be Smaller.

請參考圖11G與圖12，形成第一絕緣層I1於第一源極S1、第一汲極D1、第二汲極D2、資料線DL、層間介電層ILD、第一島狀結構IS1以及第二島狀結構IS2上。第一絕緣層I1覆蓋第一島狀結構IS1、第二島狀結構IS2以及資料線DL。 11G and 12, a first insulating layer I1 is formed on the first source S1, the first drain D1, the second drain D2, the data line DL, the interlayer dielectric layer ILD, the first island-like structure IS1 and On the second island structure IS2. The first insulating layer I1 covers the first island-like structure IS1, the second island-like structure IS2, and the data line DL.

形成第一共通電極C1以及第二共通電極C2於第一絕緣層I1上。 The first common electrode C1 and the second common electrode C2 are formed on the first insulating layer I1.

在本實施例中，選擇性的在形成第一共通電極C1以及第二共通電極C2之後形成第二絕緣層I2。在形成第二絕緣層I2之後形成第一畫素電極PE1與第二畫素電極PE2，第一畫素電極PE1透過第一開口OP1而電性連接第一汲極D1，第二畫素電極PE2 透過第二開口OP2而電性連接第二汲極D2。第一開口OP1貫穿第一島狀結構IS1與第一絕緣層I1，第二開口OP2貫穿第二島狀結構IS2與第一絕緣層I1。換句話說，本實施例是以共通電極位於基板SB與畫素電極之間的結構為例，但本發明不以此為限。在其他實施例中，畫素電極位於基板SB與共通電極之間。 In this embodiment, the second insulating layer I2 is selectively formed after the first common electrode C1 and the second common electrode C2 are formed. After forming the second insulating layer I2, a first pixel electrode PE1 and a second pixel electrode PE2 are formed. The first pixel electrode PE1 is electrically connected to the first drain electrode D1 through the first opening OP1, and the second pixel electrode PE2 The second drain D2 is electrically connected through the second opening OP2. The first opening OP1 penetrates the first island-shaped structure IS1 and the first insulating layer I1, and the second opening OP2 penetrates the second island-shaped structure IS2 and the first insulating layer I1. In other words, this embodiment takes the structure in which the common electrode is located between the substrate SB and the pixel electrode as an example, but the invention is not limited thereto. In other embodiments, the pixel electrode is located between the substrate SB and the common electrode.

至此，主動元件基板80大致完成。主動元件基板80包括基板SB、第一掃描線SL1、第二掃描線SL2、資料線DL、第一主動元件T1、第一畫素電極PE1、第二主動元件T2、第二畫素電極PE2、第一島狀結構IS1以及第二島狀結構IS2。 At this point, the active device substrate 80 is substantially completed. The active element substrate 80 includes a substrate SB, a first scan line SL1, a second scan line SL2, a data line DL, a first active element T1, a first pixel electrode PE1, a second active element T2, a second pixel electrode PE2, The first island-like structure IS1 and the second island-like structure IS2.

基於上述，第一主動元件T1的第一半導體通道層SC1連接第二主動元件T2的第二半導體通道層SC2，因此第一主動元件T1與第二主動元件T2皆可以藉由同一條資料線DL驅動。相較於每個主動元件皆連接至一條資料線的主動元件基板，本實施例的主動元件基板80可以使用較少的資料線，增加了第一主動元件T1與第二主動元件T2之設計空間，能提升畫素的開口率以及解析度的設計極限。 Based on the above, the first semiconductor channel layer SC1 of the first active element T1 is connected to the second semiconductor channel layer SC2 of the second active element T2, so both the first active element T1 and the second active element T2 can pass the same data line DL drive. Compared to an active device substrate where each active device is connected to one data line, the active device substrate 80 of this embodiment can use fewer data lines, increasing the design space of the first active device T1 and the second active device T2 , Can increase the pixel aperture ratio and the design limit of resolution.

圖13是依照本發明的一實施例的一種主動元件基板的剖面示意圖。在此必須說明的是，圖13的實施例沿用圖12的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 13 is a schematic cross-sectional view of an active device substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 13 uses the element numbers and partial contents of the embodiment of FIG. 12, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

圖13的主動元件基板90與圖12的主動元件基板80的 主要差異在於：主動元件基板90的第一半導體通道層SC1與第二半導體通道層SC2的材料包括金屬氧化物。 The active device substrate 90 of FIG. 13 and the active device substrate 80 of FIG. 12 The main difference is that the materials of the first semiconductor channel layer SC1 and the second semiconductor channel layer SC2 of the active device substrate 90 include metal oxides.

在本實施例中，沒有對半導體層進行重摻雜製程以及輕摻雜製程，而是對半導體層進行電漿處理製程以形成第一半導體通道層SC1與第二半導體通道層SC2。 In this embodiment, the semiconductor layer is not heavily doped and lightly doped, but the semiconductor layer is subjected to a plasma process to form the first semiconductor channel layer SC1 and the second semiconductor channel layer SC2.

第一半導體通道層SC1包括重疊於第一閘極G1的通道區R2，以及分別位於通道區R2的兩側的源極區R1與汲極區R3。源極區R1與汲極區R3的電阻率小於通道區R2的電阻率。 The first semiconductor channel layer SC1 includes a channel region R2 overlapping the first gate G1, and a source region R1 and a drain region R3 located on both sides of the channel region R2. The resistivity of the source region R1 and the drain region R3 is smaller than that of the channel region R2.

第二半導體通道層SC2包括重疊於第二閘極G2的通道區R5，以及分別位於通道區R5的兩側的源極區R4與汲極區R6。源極區R4與汲極區R6的電阻率小於通道區R5的電阻率。 The second semiconductor channel layer SC2 includes a channel region R5 overlapping the second gate G2, and a source region R4 and a drain region R6 located on both sides of the channel region R5, respectively. The resistivity of the source region R4 and the drain region R6 is smaller than that of the channel region R5.

基於上述，第一主動元件T1的第一半導體通道層SC1連接第二主動元件T2的第二半導體通道層SC2，因此第一主動元件T1與第二主動元件T2皆可以藉由同一條資料線DL驅動。相較於每個主動元件皆連接至一條資料線的主動元件基板，本實施例的主動元件基板90可以使用較少的資料線，增加了第一主動元件T1與第二主動元件T2之設計空間，能提升畫素的開口率以及解析度的設計極限。 Based on the above, the first semiconductor channel layer SC1 of the first active element T1 is connected to the second semiconductor channel layer SC2 of the second active element T2, so both the first active element T1 and the second active element T2 can pass the same data line DL drive. Compared to an active device substrate where each active device is connected to one data line, the active device substrate 90 of this embodiment can use fewer data lines, increasing the design space of the first active device T1 and the second active device T2 , Can increase the pixel aperture ratio and the design limit of resolution.

綜上所述，本發明的第一主動元件與第二主動元件皆可以藉由同一條資料線驅動。相較於每個主動元件皆連接至一條資料線的主動元件基板，本發明的主動元件基板可以使用較少的資料線，增加了第一主動元件與第二主動元件之設計空間，能提升 畫素的開口率以及解析度的設計極限。 In summary, both the first active element and the second active element of the present invention can be driven by the same data line. Compared to an active device substrate in which each active device is connected to one data line, the active device substrate of the present invention can use fewer data lines, which increases the design space of the first active device and the second active device and can be improved The design limit of pixel aperture ratio and resolution.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10‧‧‧主動元件基板 10‧‧‧Active component substrate

AA’‧‧‧剖面線 AA’‧‧‧hatching

BL‧‧‧緩衝層 BL‧‧‧Buffer layer

C1、C2‧‧‧共通電極 C1, C2‧‧‧Common electrode

D1、D2‧‧‧汲極 D1, D2‧‧‧ji

G1、G2‧‧‧閘極 G1, G2 ‧‧‧ gate

GI‧‧‧閘極絕緣層 GI‧‧‧Gate insulation

H1、H2、H3、OP1、OP2‧‧‧開口 H1, H2, H3, OP1, OP2 ‧‧‧ opening

I1‧‧‧第一絕緣層 I1‧‧‧First insulation layer

I2‧‧‧第二絕緣層 I2‧‧‧Second insulation layer

ILD‧‧‧層間介電層 ILD‧‧‧Interlayer dielectric layer

P1‧‧‧重摻雜區 P1‧‧‧ heavily doped area

P2‧‧‧輕摻雜區 P2‧‧‧ lightly doped region

P3‧‧‧主動區 P3‧‧‧Active area

PE1、PE2‧‧‧畫素電極 PE1, PE2 ‧‧‧ pixel electrode

R1、R4‧‧‧源極區 R1, R4‧‧‧Source region

R2、R5‧‧‧通道區 R2, R5‧‧‧channel area

R3、R6‧‧‧汲極區 R3, R6 ‧‧‧ Drain

S1‧‧‧源極 S1‧‧‧Source

SB‧‧‧基板 SB‧‧‧Substrate

SC‧‧‧半導體層 SC‧‧‧Semiconductor layer

SC1、SC2‧‧‧半導體通道層 SC1, SC2‧‧‧‧ semiconductor channel layer

SM‧‧‧遮光層 SM‧‧‧Light-shielding layer

T1、T2‧‧‧主動元件 T1, T2‧‧‧Active components

X1、X2‧‧‧延伸部 X1, X2‧‧‧Extension

Y1、Y2‧‧‧分支部 Y1, Y2‧‧‧ Branch

Claims (19)

一種主動元件基板，包括：一基板；一第一掃描線、一第二掃描線與一資料線設置於該基板；一第一主動元件，包括：一第一半導體通道層；一第一閘極，重疊於該第一半導體通道層，且電性連接該第一掃描線；一第一源極，電性連接該資料線與該第一半導體通道層；以及一第一汲極，電性連接該第一半導體通道層；一第一畫素電極，電性連接該第一汲極；一第二主動元件，包括：一第二半導體通道層，該第一半導體通道層連接該第二半導體通道層的一源極區，其中該第一半導體通道層以及該第二半導體通道層屬於同一膜層；一第二閘極，重疊於該第二半導體通道層，且電性連接該第二掃描線；以及一第二汲極，電性連接該第二半導體通道層；以及一第二畫素電極，電性連接該第二汲極。 An active device substrate includes: a substrate; a first scan line, a second scan line and a data line are disposed on the substrate; a first active device includes: a first semiconductor channel layer; a first gate , Which overlaps the first semiconductor channel layer and is electrically connected to the first scan line; a first source electrode, which is electrically connected to the data line and the first semiconductor channel layer; and a first drain electrode, which is electrically connected The first semiconductor channel layer; a first pixel electrode electrically connected to the first drain electrode; a second active element, including: a second semiconductor channel layer, the first semiconductor channel layer connected to the second semiconductor channel A source region of the layer, wherein the first semiconductor channel layer and the second semiconductor channel layer belong to the same film layer; a second gate electrode overlaps the second semiconductor channel layer and is electrically connected to the second scan line And a second drain electrode electrically connected to the second semiconductor channel layer; and a second pixel electrode electrically connected to the second drain electrode. 如申請專利範圍第1項所述的主動元件基板，更包括：一第三掃描線；以及 一第三主動元件，包括：一第三半導體通道層，該第二半導體通道層連接該第三半導體通道層的一源極區，其中該第一半導體通道層、該第二半導體通道層以及該第三半導體通道層依序連接，且該第一半導體通道層、該第二半導體通道層以及該第三半導體通道層屬於同一膜層；一第三閘極，重疊於該第三半導體通道層，且電性連接該第三掃描線；以及一第三汲極，電性連接該第三半導體通道層；以及一第三畫素電極，電性連接該第三汲極。 The active component substrate as described in item 1 of the patent application scope further includes: a third scanning line; and A third active device includes: a third semiconductor channel layer, the second semiconductor channel layer is connected to a source region of the third semiconductor channel layer, wherein the first semiconductor channel layer, the second semiconductor channel layer and the The third semiconductor channel layer is connected in sequence, and the first semiconductor channel layer, the second semiconductor channel layer and the third semiconductor channel layer belong to the same film layer; a third gate electrode overlaps the third semiconductor channel layer, And electrically connected to the third scan line; and a third drain electrode, electrically connected to the third semiconductor channel layer; and a third pixel electrode, electrically connected to the third drain electrode. 如申請專利範圍第1項所述的主動元件基板，更包括：一電容電極，重疊於該第一半導體通道層。 The active device substrate as described in item 1 of the scope of the patent application further includes: a capacitor electrode overlapping the first semiconductor channel layer. 如申請專利範圍第3項所述的主動元件基板，其中該第一汲極重疊於該電容電極。 The active device substrate as described in item 3 of the patent application range, wherein the first drain electrode overlaps the capacitor electrode. 如申請專利範圍第3項所述的主動元件基板，其中該電容電極的延伸方向、該第一掃描線的延伸方向以及該第二掃描線的延伸方向實質上相同。 The active device substrate as described in item 3 of the patent application range, wherein the extending direction of the capacitor electrode, the extending direction of the first scanning line and the extending direction of the second scanning line are substantially the same. 如申請專利範圍第1項所述的主動元件基板，更包括：一第一島狀結構，位於該第一汲極上；一第二島狀結構，位於該第二汲極上；以及一第一絕緣層，覆蓋該第一島狀結構、該第二島狀結構以及該資料線，其中該第一畫素電極透過一第一開口而電性連接該第一 汲極，該第二畫素電極透過一第二開口而電性連接該第二汲極，且該第一開口貫穿該第一島狀結構與該第一絕緣層，該第二開口貫穿該第二島狀結構與該第一絕緣層。 The active device substrate as described in item 1 of the patent scope further includes: a first island-shaped structure on the first drain; a second island-shaped structure on the second drain; and a first insulation Layer covering the first island-like structure, the second island-like structure and the data line, wherein the first pixel electrode is electrically connected to the first through a first opening The drain electrode, the second pixel electrode is electrically connected to the second drain electrode through a second opening, and the first opening penetrates the first island-like structure and the first insulating layer, and the second opening penetrates the first Two island structures and the first insulating layer. 如申請專利範圍第6項所述的主動元件基板，其中該第一島狀結構與該第二島狀結構的材料包括固化的感光材料。 The active device substrate as described in item 6 of the patent application range, wherein the materials of the first island-shaped structure and the second island-shaped structure include cured photosensitive materials. 如申請專利範圍第6項所述的主動元件基板，其中該第一島狀結構於該基板之垂直投影面積和該第一汲極於該基板之垂直投影面積實質相同。 The active device substrate as recited in item 6 of the patent application range, wherein the vertical projection area of the first island-like structure on the substrate and the vertical projection area of the first drain on the substrate are substantially the same. 如申請專利範圍第6項所述的主動元件基板，更包括：一第一共通電極，位於該第一絕緣層上；一第二共通電極，位於該第一絕緣層上；以及一第二絕緣層，位於該第一共通電極、該第二共通電極以及該第一絕緣層上，且該第一畫素電極與該第二畫素電極位於該第二絕緣層上，其中該第一開口與該第二開口貫穿該第二絕緣層。 The active device substrate as described in item 6 of the patent application scope further includes: a first common electrode on the first insulating layer; a second common electrode on the first insulating layer; and a second insulating Layer is located on the first common electrode, the second common electrode and the first insulating layer, and the first pixel electrode and the second pixel electrode are located on the second insulating layer, wherein the first opening and The second opening penetrates the second insulating layer. 如申請專利範圍第1項所述的主動元件基板，其中該第一主動元件與該第二主動元件位於該第一掃描線與該第二掃描線之間。 The active device substrate as described in item 1 of the patent application scope, wherein the first active device and the second active device are located between the first scan line and the second scan line. 如申請專利範圍第1項所述的主動元件基板，其中該第一閘極包括：一第一延伸部，連接該第一掃描線；以及 一第一分支部，連接該第一延伸部，且與該第一延伸部之間具有夾角，其中該第一延伸部與該第一分支部分別重疊於該第一半導體通道層。 The active device substrate as described in item 1 of the patent application scope, wherein the first gate includes: a first extension portion connected to the first scan line; and A first branch portion is connected to the first extension portion and has an angle with the first extension portion, wherein the first extension portion and the first branch portion overlap the first semiconductor channel layer, respectively. 如申請專利範圍第2項所述的主動元件基板，其中該第一掃描線包括互相平行的一第一導線與一第二導線，該第一閘極包括互相分離的一第一部分與一第二部分，該第一部分與該第二部分分別電性連接至該第一導線與該第二導線。 The active device substrate as described in item 2 of the patent application scope, wherein the first scan line includes a first wire and a second wire parallel to each other, and the first gate includes a first part and a second part separated from each other Part, the first part and the second part are electrically connected to the first wire and the second wire respectively. 一種主動元件基板的製造方法，包括：提供一基板；形成一半導體層於該基板上；形成一閘極絕緣層於該半導體層上；對該半導體層進行一處理製程，以形成一第一半導體通道層以及一第二半導體通道層，該第一半導體通道層連接該第二半導體通道層的一源極區；形成一第一掃描線、一第二掃描線、一第一閘極以及一第二閘極於該閘極絕緣層上，該第一閘極電性連接該第一掃描線，該第二閘極電性連接該第二掃描線；形成一層間介電層於該第一掃描線、該第二掃描線、該第一閘極以及該第二閘極上；形成一第一源極、一資料線、一第一汲極以及一第二汲極於該層間介電層上，該第一源極電性連接該資料線與該第一半導體通道層，該第一汲極與該第二汲極分別電性連接該第一半導體通道 層與該第二半導體通道層；形成一第一絕緣層於該第一源極、該第一汲極、該第二汲極、該資料線以及該層間介電層上；形成一第一畫素電極與一第二畫素電極於該第一絕緣層上，該第一畫素電極與該第二畫素電極分別電性連接該第一汲極與該第二汲極。 A method for manufacturing an active device substrate includes: providing a substrate; forming a semiconductor layer on the substrate; forming a gate insulating layer on the semiconductor layer; performing a processing process on the semiconductor layer to form a first semiconductor A channel layer and a second semiconductor channel layer, the first semiconductor channel layer is connected to a source region of the second semiconductor channel layer; forming a first scan line, a second scan line, a first gate electrode and a first Two gates are on the gate insulating layer, the first gate is electrically connected to the first scan line, and the second gate is electrically connected to the second scan line; an interlayer dielectric layer is formed on the first scan Line, the second scan line, the first gate and the second gate; forming a first source, a data line, a first drain and a second drain on the interlayer dielectric layer, The first source is electrically connected to the data line and the first semiconductor channel layer, and the first drain and the second drain are electrically connected to the first semiconductor channel, respectively Layer and the second semiconductor channel layer; forming a first insulating layer on the first source, the first drain, the second drain, the data line and the interlayer dielectric layer; forming a first picture A pixel electrode and a second pixel electrode are on the first insulating layer, and the first pixel electrode and the second pixel electrode are electrically connected to the first drain electrode and the second drain electrode, respectively. 如申請專利範圍第13項所述的主動元件基板的製造方法，其中上述形成該第一掃描線、該第二掃描線、該第一閘極以及該第二閘極於該閘極絕緣層上之步驟包括：形成一第一金屬層於該閘極絕緣層上；以及圖案化該第一金屬層以形成該第一掃描線、該第二掃描線、該第一閘極以及該第二閘極；其中上述處理製程包括：以該第一金屬層為罩幕，對該半導體層進行一重摻雜製程；以及以該第一掃描線、該第二掃描線、該第一閘極以及該第二閘極為罩幕，對該半導體層進行一輕摻雜製程。 The method for manufacturing an active device substrate as described in item 13 of the patent application range, wherein the first scan line, the second scan line, the first gate and the second gate are formed on the gate insulating layer The steps include: forming a first metal layer on the gate insulating layer; and patterning the first metal layer to form the first scan line, the second scan line, the first gate, and the second gate Pole; wherein the above process includes: using the first metal layer as a mask, a heavily doped process for the semiconductor layer; and the first scan line, the second scan line, the first gate and the first The second gate is a mask, and a light doping process is performed on the semiconductor layer. 如申請專利範圍第13項所述的主動元件基板的製造方法，更包括：形成一電容電極於該閘極絕緣層上。 The method for manufacturing an active device substrate as described in item 13 of the patent scope further includes: forming a capacitor electrode on the gate insulating layer. 如申請專利範圍第15項所述的主動元件基板的製造方法，其中該處理製程係在上述形成該第一掃描線、該第二掃描線、該第一閘極以及該第二閘極於該閘極絕緣層上之前進行，該處理製程為一重摻雜製程；以及在形成該第一掃描線、該第二掃描線、該第一閘極以及該第二閘極於該閘極絕緣層上之後，以該第一掃描線、該第二掃描線、該第一閘極以及該第二閘極以及該電容電極為罩幕，對該半導體層進行一輕摻雜製程。 The method for manufacturing an active device substrate as described in item 15 of the patent application range, wherein the processing process is to form the first scan line, the second scan line, the first gate, and the second gate above the Before the gate insulating layer, the processing process is a heavily doped process; and before forming the first scan line, the second scan line, the first gate and the second gate on the gate insulating layer Then, using the first scan line, the second scan line, the first gate, the second gate, and the capacitor electrode as a mask, a light doping process is performed on the semiconductor layer. 如申請專利範圍第13項所述的主動元件基板的製造方法，其中該處理製程為一電漿處理製程。 The method for manufacturing an active device substrate as described in item 13 of the patent application range, wherein the processing process is a plasma processing process. 如申請專利範圍第13項所述的主動元件基板的製造方法，其中上述形成該第一源極、該資料線、該第一汲極以及該第二汲極於該層間介電層上之步驟包括：形成一第二金屬層於該層間介電層上；形成一第一島狀結構以及一第二島狀結構於該第二金屬層上；以及圖案化該第二金屬層以形成該第一源極、該資料線、該第一汲極以及該第二汲極，其中該第一島狀結構以及該第二島狀結構分別位於該第一汲極以及該第二汲極上方。 The method for manufacturing an active device substrate as described in item 13 of the patent application scope, wherein the step of forming the first source electrode, the data line, the first drain electrode and the second drain electrode on the interlayer dielectric layer The method includes: forming a second metal layer on the interlayer dielectric layer; forming a first island-like structure and a second island-like structure on the second metal layer; and patterning the second metal layer to form the first A source electrode, the data line, the first drain electrode and the second drain electrode, wherein the first island structure and the second island structure are respectively located above the first drain electrode and the second drain electrode. 如申請專利範圍第13項所述的主動元件基板的製造方法，更包括： 形成一第一共通電極以及一第二共通電極於該第一絕緣層上；以及形成一第二絕緣層於該第一絕緣層、該第一共通電極以及該第二共通電極上，且該第一畫素電極與該第二畫素電極位於該第二絕緣層上。 The method for manufacturing an active component substrate as described in item 13 of the patent application scope further includes: Forming a first common electrode and a second common electrode on the first insulating layer; and forming a second insulating layer on the first insulating layer, the first common electrode and the second common electrode, and the first A pixel electrode and the second pixel electrode are located on the second insulating layer.
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