TWI803288B - 集成的平面-溝道閘極功率mosfet - Google Patents

集成的平面-溝道閘極功率mosfet Download PDF

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TWI803288B
TWI803288B TW111114890A TW111114890A TWI803288B TW I803288 B TWI803288 B TW I803288B TW 111114890 A TW111114890 A TW 111114890A TW 111114890 A TW111114890 A TW 111114890A TW I803288 B TWI803288 B TW I803288B
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channel
conductivity type
epitaxial layer
gate
planar
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TW202308159A (zh
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文軍 李
靈鵬 管
健 王
淩兵 陳
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加拿大商萬國半導體國際有限合夥公司
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Abstract

電晶體器件及其製造方法，包括重摻雜第一導電類型的襯底和在襯底頂部輕摻雜第一導電類型的外延層。在外延層中形成摻雜有第二導電類型的本體區，其中第二導電類型與第一導電類型相對，並且在外延層的本體區中形成摻雜有第一導電類型的源區域。具有平面閘極部分的集成平面溝道閘極形成在外延層的表面上，該外延層與在外延層中形成的閘極溝道部分相連。

Description

集成的平面-溝道閘極功率MOSFET
本發明的各個方面通常涉及電晶體，更具體地說，涉及垂直雙擴散金屬氧化物半導體（VDMOS）場效應電晶體和溝道柵金屬氧化物半導體場效應電晶體（MOSFET）。
消費市場需要更小的設備。此外，計算能力和性能隨著可安裝在單個晶圓上的電晶體數量的增加而增加。減小電晶體節距，降低導通電阻（Rdson），可以降低製冷用量和功耗。
目前對於高壓應用來說，平面電晶體的間距存在限制。當共用閘極的本體區之間的距離減小時，兩個本體區之間的JFET區中電荷載流子的橫向耗盡率增大。這導致從汲極到源極（RDS）的電阻增加。解決這個問題的辦法是增加JFET區域的摻雜濃度，惟由此產生的尺寸減小是有限的。
正是在這一前提下，提出了本發明的各種實施例。
本發明提供一種電晶體器件，包括：一個重摻雜第一導電類型的襯底；一個輕摻雜第一導電類型的外延層，形成在襯底上；一個摻雜第二導電類型的本體區，形成在外延層中，其中第二導電類型與第一導電類型相反；一個摻雜第一導電類型的源極區，形成在外延層的本體區中；一個集成平面-溝道閘極，其具有一平面閘極部分形成在外延層的表面上，與在外延層中的溝道中形成的溝道閘極部分相連，其中襯底中的溝道閘極部分底部的深度，小於本體區的最低摻雜深度。
儘管為了說明的目的，以下詳細描述包含許多特定細節，惟本創作所屬技術領域中具有通常知識者將理解，對以下細節的許多變化和修改都在本發明的範圍內。因此，下文描述的本發明的示例性實施例對所要求保護的發明沒有任何一般性損失，也沒有施加限制。
本發明涉及摻雜有第一導電類型或第二導電類型離子的矽。第一導電類型的離子可以是第二導電類型的相反離子。例如，第一導電類型的離子可以是n型，其在摻雜到矽中時產生電荷載流子。第一種導電類型的離子包括磷、銻、鉍、鋰和砷。第二導電性的離子可以是p型，當摻雜到矽中時，其為電荷載流子創建空穴，並且以這種方式被稱為與n型相反。p型離子包括硼、鋁、鎵和銦。儘管上述描述將n型稱為第一導電類型，將p型稱為第二導電類型，惟本發明並不限於此，p型可以是第一導電類型，而n型可以是第二導電類型。
在下面的詳細描述中，參考附圖，附圖構成了本發明的一部分，並且在附圖中通過圖示的方式表示出了可以實施本發明的特定實施例。為了方便起見，在指定導電性或淨雜質載流子類型（p或n）之後使用+或–通常指半導體材料內指定類型的淨雜質載流子的相對濃度。一般而言，n+材料具有比n材料更高的n型淨摻雜物（例如電子）濃度，並且n材料具有比n-材料更高的載流子濃度。類似地，p+材料具有比p材料更高的p型淨摻雜物（例如空穴）濃度，並且p材料具有比p-材料更高的濃度。要注意的是，相關的是載流子的淨濃度，而不一定是摻雜物。例如材料可以重摻雜n型摻雜物，但是如果材料也充分反摻雜p型摻雜物，則材料仍然具有相對低的淨載流子濃度。如本文所用，小於約10 16/cm 3的摻雜物濃度可被視為“輕摻雜”，而大於約10 17/cm 3的摻雜物濃度可被視為“重摻雜”。 引言
根據本發明的各個方面，可通過創建具有連續閘極部分和溝道部分的集成平面溝道閘極來改善電晶體器件的間距。集成的平面溝道閘極允許更小的平面閘極尺寸，並減少R DS。先前的器件已經實現了由絕緣層分離並透過導線電耦合的平面閘極和溝道閘極的組合。該等先前的器件由大的深溝道製成，因此不可能形成在平面閘極部分和溝道閘極部分之間相連的具有平面閘極的集成閘極溝道。先前器件用絕緣層和導電層填充較大溝道導致閘極不夠平坦。平面閘極和溝道閘極之間的中間絕緣層用於創建平面閘極。由於溝道閘極和平面閘極的對準困難，透過平面閘極和溝道閘極之間的絕緣層創建開口以電耦合兩個閘極是不切實際的。因此，平面閘極和溝道閘極使用引線進行電氣連接，而不是兩個閘極的導電層之間的直接接觸。現有器件中兩個閘極的深溝道和間接連接增加了現有器件的複雜性，並且使得縮小現有器件的尺寸變得困難。
為了解決這個問題，設計了一種電晶體器件及其製造方法，該電晶體器件包括重摻雜第一導電類型的襯底和在襯底頂部輕摻雜第一導電類型的外延層。在外延層中形成摻雜有與第一導電類型相反的第二導電類型的本體區，並且在外延層的本體區中形成摻雜有第一導電類型的源極區域。該器件包括集成平面溝道閘極，該集成平面溝道閘極具有形成在外延層的表面上的平面閘極部分，該平面閘極部分與在外延層中的溝道中形成的溝道閘極部分相連。在一些實施方案中，該器件還可包括局部JFET注入區，該區域重摻雜有圍繞溝道閘極部分的底部和側面形成的第一導電類型。輕摻雜第一導電類型的外延層的區域可分離局部JFET注入物和本體區。在一些實施方式中，溝道閘極部分可以形成在外延層的本體區中。
在一些其它實施例中，襯底中溝道閘極部分的底部深度可小於本體區的最低摻雜深度。在其他實施例中，溝道閘極部分可透過閘極溝道底部的厚絕緣層與外延層絕緣，該厚絕緣層比閘極溝道至少一側的絕緣層厚。在又一個其它實施例中，外延層可進一步包括摻雜有第二導電類型的交替體區柱和輕摻雜有第一導電類型的形成所謂超結結構的外延層柱。在一些實施例中，裝置的閘極溝道部分的溝道的側壁可以與閘極溝道部分的溝道的底部以大於90度的角度相交。電晶體器件的閘極溝道部分的溝道深度可以在0.3到0.8微米之間。在本發明的一些實施例中，該器件的閘極溝道部分的溝道底部絕緣層的厚度可以是溝道一側的絕緣層厚度的1.5到2倍。 器件
第1圖表示了根據本發明的各個方面，集成的平面溝道柵電晶體器件的側面剖視圖。如圖所示，集成的平面溝道柵電晶體器件包括重摻雜有第一導電類型離子的襯底101。外延層102可以形成在襯底101的頂部。作為示例，而非限制，外延層102可使用外延生長在襯底101的表面上生長或以其他方式沉積在襯底的表面上。在外延層102中形成溝道103。在一些實施例中，溝道103的側面和底部周圍的區域可重摻雜第一導電類型的離子，形成局部JFET注入區域108。介電層106形成在襯底的表面上，以將集成平面溝道閘極的平面閘極部分107與外延層102電絕緣。介電層106還排列溝道103的側壁和底部，為集成平面溝道閘極的溝道部分的側壁105和底部104創建絕緣層。在一些實施方案中，溝道103底部104上的絕緣層的厚度可以是本文中稱為厚底部絕緣體的溝道側面103上的絕緣層的1.5到2倍。絕緣層可由諸如氧化矽的介電材料組成。平面閘極部分107可以透過圖案化形成在絕緣層106的表面上的導電層而形成。導電層的一部分填充溝道103中未被介電層106佔據的部分，並且透過溝道的側壁105和底部104上的部分絕緣層與外延層102絕緣。導電層創建在閘極的平面部分107和閘極的溝道部分112之間連接的集成平面溝道閘極。導電層可由多晶矽或其他導電材料（例如氮化鈦（TiN）或鎢）組成。閘極觸點113耦合到導電層107。由於閘極的平面閘極部分107和溝道閘極部分112的連續性，溝道部分112不具有單獨的閘極接觸。取而代之的是，溝道部分112由於與閘極的平面閘極部分107相連而保持在閘極電勢水準。可以在外延層102中形成一個或複數個本體區109。源極區110可以形成在外延層102的本體區109中。源觸點111將源極區域耦合到源極，並且還可以包括本體短路觸點。可在基板101的底部形成汲極金屬114。汲極觸點115可耦合到汲極金屬114上。
在操作期間，閘極觸點113處的閘極電勢允許電流透過電晶體器件傳導。例如，在不限制N型MOSFET配置的情況下，施加到汲極觸點115的電流透過汲極金屬114、襯底101和外延層102傳導。來自外延層102的電荷載流子與本體區109中的相反電荷空穴結合，從而允許電流傳導到源極區域110和源極觸點111。
第2圖表示根據本發明各個方面，集成的平面-溝道柵電晶體器件的可選實施例的側面剖視圖。在第2圖所示的實施例中，本體區209接觸一個局域化的結型場效應電晶體（JFET）注入區域208。此外，源極區210比在沒有相交本體區和集成的平面-溝道閘極的實施例中更靠近閘極溝道203。如圖所示，兩個本體區209佈置得非常靠近溝道203，使得區域在溝道203下方相交。集成的平面-溝道閘極的平面部分207比在溝道下方不包括相交本體區的實施例中短。集成的平面溝道閘極和局部JFET植入物208允許電晶體器件的節距減小，其原因在於集成的平面-溝道閘極的平面部分207的寬度可以減小而不會顯著影響器件的R DS。
第3圖表示根據本發明的各個方面，具有集成的平面-溝道閘極的超級結電晶體器件的側面剖視圖。如圖所示，該器件的本體區309包括摻雜有第二導電類型的離子的柱320，該第二導電類型的離子終止於襯底101附近。外延層302形成摻雜有第一導電類型的離子的柱。因此，摻雜體柱320和摻雜有第一導電性離子302的外延層區域的組合為超級結器件在外延層中分別創建摻雜有第一導電性類型和第二導電性類型的交替柱。 製備方法
第4A-4J圖表示根據本發明各個方面，製造集成的平面-溝道閘極電晶體器件的方法的側面剖視圖。第4A圖表示根據本發明的各個方面，重摻雜第一導電類型離子的襯底401和更輕摻雜的外延層402。襯底401可在1x10 19和1x10 20cm -3之間的離子濃度下摻雜。襯底可由例如但不限於矽、碳化矽、氮化鎵或砷化鎵組成。外延層402可以形成在襯底401的表面上。外延層402可以透過諸如氣相外延之類的過程生長在外延層401的上表面上。外延層402可在形成期間或之後輕摻雜第一導電類型的離子。外延層402可在1x10 17和6x10 17cm -3之間的離子濃度下摻雜。
第4B圖表示根據本發明的各個方面，用於集成平面溝道閘極電晶體器件的外延層402中溝道403的形成的側面剖視圖。最初，包括氧化矽層407、氮化矽層406、氧化矽層405堆疊的硬光罩可沉積在外延層402的表面上。氧化層407、405和氮化物層406可透過化學氣相沉積技術（CVD）形成，以形成SiO 2和氮化矽，或透過熱氧化過程形成SiO 2。在硬光罩的表面上形成光罩圖案404。光罩圖案404可使用光刻技術創建或透過機械光罩工藝應用。光罩圖案404包括溝道間隙408。對光罩圖案和硬光罩應用刻蝕工藝，例如使用磷酸或其他此類選擇刻蝕劑的等離子體幹法刻蝕或濕法刻蝕。硬光罩在溝道間隙408處刻蝕掉，在溝道間隙中暴露外延層402。外延層402隨後可透過諸如深反應離子刻蝕（DRIE）的等離子體刻蝕技術經由溝道間隙408刻蝕至所需深度。所創建的溝道403的深度可以在外延層的0.3微米到0.8微米之間。或者，可以基於期望的器件特性來選擇溝道的深度。對溝道深度的一般影響是，隨著兩個P型本體區之間的間距減小，溝道深度增加。溝道403的側面可以形成一定角度，使得溝道的側面與溝道的底部以大於90度的角度相交。例如，在不受限制的情況下，溝道的一側與溝道底表面形成的角度可以在101度和105度之間。
第4C圖表示根據本發明的方面的局部JFET植入區409的形成的側剖視圖。如圖所示，可在圍繞溝道403的底部和側面的外延層402中形成局部JFET植入區409。在一些實施方案中，局部JFET注入區409可透過穿過圖案光罩和硬光罩的離子注入410形成。局部JFET植入區411可重摻雜第一導電類型的離子。局部JFET注入區可以以2到3倍於外延層的離子濃度摻雜。局部JFET注入區可減少耗盡電荷載流子，因此有助於減少器件的RDS。
第4D圖表示根據本發明的各個方面，在溝道403底部形成厚底部絕緣層411的剖視圖。厚底絕緣層411可藉此諸如高密度等離子體（HDP）沉積或化學氣相沉積技術（CVD）等沉積技術形成。厚的底部絕緣層可由氧化矽或氮化物或ONO（SiO 2/氮化物/SiO 2）薄膜組成。然後對溝道403的側壁施加等離子體幹刻蝕或濕刻蝕，以去除沉積在溝道側面上的任何多餘絕緣層。厚的底部絕緣層最初形成的厚度在1500和2500埃（Å）之間。在一些實施例中，厚底部絕緣層的最終厚度為溝道側壁絕緣層厚度的1.5至2倍，該最終厚度在溝道側面和底部形成絕緣層後實現，如第4E圖所示。
第4E圖顯示根據本發明的各個方面，具有平面部分412和溝道部分413的閘極絕緣層的形成的剖面側視圖。如圖所示，在外延層402的表面上沉積絕緣層。外延層402表面上的絕緣層的平面部分412將形成集成平面溝道閘極的平面部分的一部分。絕緣層材料也沉積在溝道403的底部和側壁413上。在實施方式中，具有厚的底部絕緣層的絕緣材料沉積在先前沉積的絕緣材料的頂部，形成厚的底部絕緣層411的最終厚度。絕緣層可由氧化矽組成。絕緣層的平面部分412和溝道403底部的溝道部分413的厚度可以大致相同，例如，在800到1000埃之間。
如第4F圖所示，導電層包括絕緣層的平面部分412上的平面部分415和溝道部分416。導電層可以沉積在絕緣層的表面上。導電層的溝道部分416填充溝道413中未被絕緣層部分佔據的部分，包括厚底絕緣體（可選）411和溝道413側面的絕緣層。導電層的平面部分415覆蓋絕緣層的平面部分412。本文描述的技術在絕緣層的平面部分和溝道部分上創建導電層的極平坦表面，而不在平面部分和溝道部分之間形成中間絕緣層。
第4G圖表示根據本發明的各個方面，在將導電層圖案化以形成具有相連平面閘極部分415和溝道閘極部分416的平面溝道閘極之後，形成集成平面溝道閘極的剖面側視圖。遮罩並刻蝕導電層415，留下平面溝道閘極的最終尺寸。在移除光罩之後，平面閘極部分415隨後可充當用於絕緣層的平面部分412的後續刻蝕的光罩。優選地，刻蝕導電層的過程對導電層的材料具有選擇性，即以比導電層材料低得多的速率刻蝕絕緣層的材料。與之相反地，刻蝕絕緣層的過程對絕緣層的材料具有選擇性，即以比絕緣層低得多的速率刻蝕導電層。
第4H圖表示根據本發明的各個方面，具有集成平面溝道閘極的電晶體器件的本體區417的形成的剖面側視圖。可以在外延層的表面上形成光罩419，在本體區417的位置上具有間隙。光罩可以是應用於外延層表面的光阻光罩。離子注入418可用於用第二導電類型的離子摻雜外延層402（例如如果第一導電類型為n型，則第二導電類型為p型）。在形成本體區417之後，可以透過等離子體灰化和使用去除溶液或任何其他已知光罩去除技術（例如惟不限於平面化或拋光）來去除光罩419。
在一些實施例中，本體區可在形成溝道和集成平面溝道閘極之前形成。在該等實施方案中，溝道可以形成在外延層的本體區中。然後，可藉此反離子摻雜在本體區中形成局部JFET注入區域。該方法的這種實現可用於產生第2圖中所示的裝置。在又一實施例中，摻雜柱可形成在本體區下。該等摻雜柱形成如第3圖所示的超級結器件。
第4I圖表示根據本發明的各個方面，具有集成平面溝道閘極的電晶體器件的源極區形成的剖面側視圖。源極光罩420可以形成在外延層的表面上，在源極區422的位置處具有間隙。一個或複數個源極區422可以透過離子421透過源極光罩420中的開口注入而形成在外延層402的本體區417中。源極區422可摻雜濃度大於外延層的第一導電類型的離子。在形成源極區域422之後，可以透過等離子體灰化和使用任何其他已知光罩去除技術的去除溶液清洗來去除源光罩420，例如但不限於平面化或拋光。
第4J圖表示根據本發明的各個方面，集成平面溝道柵電晶體器件上其他結構的形成的剖面側視圖。在形成源極區422之後，在外延層402的表面上形成隔離層424。隔離層可以是例如但不限於沉積在外延層表面上的氧化矽。隔離層還可以覆蓋423集成閘極溝道，完成閘極的絕緣層。源極接觸光罩應用於外延層的源極區域422和本體區417上方的隔離層424。將隔離層刻蝕掉並且在源極區422和本體區417上方的外延層402的表面上沉積源極接觸金屬426。閘極接觸光罩被施加到閘極絕緣426，閘極接觸被刻蝕掉並且閘極接觸金屬425沉積在閘極的導電層415上。閘極接觸和源極接觸的刻蝕可藉此使用等離子體幹刻蝕來執行，刻蝕後，閘極接觸光罩和源極接觸光罩可透過等離子體灰化和使用合適的光罩去除溶液或任何其他已知光罩去除技術（例如但不限於平面化或拋光）來去除。汲極導電層427可以形成在襯底401的背面。汲極導電層427可以是例如但不限於沉積在襯底401背面的金屬。
儘管本發明攸關某些較佳的版本已經做了詳細的敘述，但是仍可能存在各種替代、修正和等效的其他版本。因此，本發明的範圍不應由上述說明決定，與之相反，本發明的範圍應參照所附的申請專利範圍及其全部等效內容。任何可選件（無論首選與否），都可與其他任何可選件（無論首選與否）組合。在以下權利要求中，除非特別聲明，否則不定冠詞“一個”或“一種”都指下文內容中的一個或複數個項目的數量。除非用“意思是”明確指出限定功能，否則所附的申請專利範圍並不應認為是意義和功能的局限。所附的申請專利範圍不應被解釋為包括手段加功能限制，除非在給定申請專利範圍中使用短語“意義是”明確敘述了該限制。
101:襯底 102:外延層 103:溝道 104:底部 105:側壁 106:介電層 107:平面閘極部分 108:JFET注入區域 109:本體區 110:源極區 111:源極觸點 112:溝道部分 113:閘極觸點 114:汲極金屬 115:汲極觸點 203:溝道 207:平面部分 208:區域 209:本體區 210:源極區 302:外延層 309:本體區 320:柱 401:襯底 402:外延層 403:溝道 404:光罩圖案 405:氧化矽層 406:氮化物層 407:氧化矽層 408:溝道間隙 409:JFET植入區 411:厚底部絕緣層 412:平面部分 413:溝道部分 415:平面部分 416:溝道部分 417:本體區 418:離子注入 419:光罩光罩 420:源極光罩 421:離子 422:源極區 423:覆蓋 424:隔離層 425:金屬 426:金屬
閱讀以下詳細說明並參照以下附圖之後，本發明的其他特徵和優勢將顯而易見： 第1圖表示依據本發明的各個方面，一種集成的平面-溝道閘極電晶體器件的側面剖視圖。 第2圖顯示依據本發明的各個方面，集成的平面-溝道閘極電晶體器件的一種可選配置的側面剖視圖。 第3圖表示依據本發明的各個方面，具有集成的平面-溝道閘極的超級結電晶體器件的側面剖視圖。 第4A圖顯示依據本發明的各個方面，一個重摻雜第一導電類型離子的襯底和一個較輕摻雜的外延層。 第4B圖表示依據本發明的各個方面，在外延層中製備一個溝道用於集成的平面-溝道閘極電晶體器件的側面剖視圖。 第4C圖表示依據本發明的各個方面，製備一個局域化的JFET注入區的側面剖面圖。 第4D圖表示依據本發明的各個方面，在溝道底部製備一個厚的底部絕緣層的剖面圖。 第4E圖顯示依據本發明的各個方面，製備具有一個平面部分和一個溝道部分的閘極絕緣層的剖面側視圖。 第4F圖表示依據本發明的各個方面，具有連續平面部分和溝道部分的導電層的集成平面-溝道閘極的形成的剖面側視圖。 第4G圖表示依據本發明的各個方面，具有相連平面閘極部分和溝道閘極部分的閘極的圖案化導電層，製備集成平面-溝道閘極的形成的剖面側視圖。 第4H圖顯示依據本發明的各個方面，製備本體區，用於具有集成的平面-溝道閘極的電晶體器件的剖面側視圖。 第4I圖表示依據本發明的各個方面，製備源極區，用於具有集成的平面-溝道閘極的電晶體器件的剖面側視圖。 第4J圖顯示依據本發明的各個方面，在集成的平面-溝道閘極電晶體器件上製備其他結構的剖面側視圖。
101:襯底
102:外延層
103:溝道
104:底部
105:側壁
106:介電層
107:平面閘極部分
108:JFET注入區域
109:本體區
110:源極區
111:源極觸點
112:溝道部分
113:閘極觸點
114:汲極金屬
115:汲極觸點

Claims (9)

  1. 一種電晶體器件，包括： 一個重摻雜第一導電類型的襯底； 一個輕摻雜第一導電類型的外延層，形成在該襯底上； 一個摻雜第二導電類型的本體區，形成在該外延層中，其中第二導電類型與第一導電類型相反； 一個摻雜第一導電類型的源極區，形成在該外延層的本體區中； 一個集成平面-溝道閘極，其具有一平面閘極部分形成在該外延層的表面上，與在該外延層中的溝道中形成的該溝道閘極部分相連，其中該襯底中的該溝道閘極部分底部的深度，小於本體區的最低摻雜深度。
  2. 如請求項1所述之電晶體器件，其中 該溝道閘極部分形成在該外延層的本體區中。
  3. 如請求項1所述之電晶體器件，還包括一個局域化的JFET注入區，重摻雜第一導電類型，形成在該溝道閘極部分的底部和邊緣周圍。
  4. 如請求項3所述之電晶體器件，其中該外延層的輕摻雜第一導電類型的區域，分隔局域化的JFET注入和本體區。
  5. 如請求項1所述之電晶體器件，還包括一個在溝道的底部的厚絕緣層，其中該溝道的底部的厚絕緣層，比該溝道至少一邊的絕緣層更厚。
  6. 如請求項1所述之電晶體器件，其中該外延層還包括可選的摻雜第二導電類型的本體區立柱，以及輕摻雜第一導電類型的外延層立柱。
  7. 如請求項1所述之電晶體器件，其中該溝道閘極部分的該溝道的一側壁與該溝道閘極部分的該溝道的一底面以大於90度的角度相交。
  8. 如請求項1所述之電晶體器件，其中該溝道閘極部分具有0.3至0.8微米之間的溝道深度。
  9. 如請求項1所述之電晶體器件，其中在該溝道閘極部分的溝道的底部的絕緣層厚度，是在該溝道的邊緣的絕緣層厚度的1.5至2倍。
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