TWI739662B - 具有增大的附接角度的導電線之半導體裝置及方法 - Google Patents
具有增大的附接角度的導電線之半導體裝置及方法 Download PDFInfo
- Publication number
- TWI739662B TWI739662B TW109139733A TW109139733A TWI739662B TW I739662 B TWI739662 B TW I739662B TW 109139733 A TW109139733 A TW 109139733A TW 109139733 A TW109139733 A TW 109139733A TW I739662 B TWI739662 B TW I739662B
- Authority
- TW
- Taiwan
- Prior art keywords
- wire
- auxiliary
- substrate
- line
- conductive
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 214
- 238000000034 method Methods 0.000 title claims description 31
- 239000000758 substrate Substances 0.000 claims abstract description 117
- 239000011810 insulating material Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims 4
- 239000010949 copper Substances 0.000 description 14
- 239000010931 gold Substances 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- -1 polypropylene Polymers 0.000 description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000004698 Polyethylene Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 239000004743 Polypropylene Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 229920000515 polycarbonate Polymers 0.000 description 4
- 239000004417 polycarbonate Substances 0.000 description 4
- 229920000573 polyethylene Polymers 0.000 description 4
- 229920001155 polypropylene Polymers 0.000 description 4
- 238000007906 compression Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
- H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/4848—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48499—Material of the auxiliary connecting means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
- H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/48998—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/14335—Digital signal processor [DSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
一種半導體裝置包含橫跨半導體晶粒形成的屏蔽線和支撐所述屏蔽線的輔助線,由此減小封裝的大小同時屏蔽從所述半導體晶粒產生的電磁干擾。在一個實施例中,所述半導體裝置包含:基板,在其上安裝有至少一個電路裝置;半導體晶粒,其與所述電路裝置間隔開且安裝到所述基板上;屏蔽線,其與所述半導體晶粒間隔開且橫跨所述半導體晶粒形成;和輔助線,其在所述屏蔽線下支撐所述屏蔽線且形成為垂直於所述屏蔽線。在另一實施例中,凸塊結構用以支撐所述屏蔽線。在又一實施例中,輔助線包含凸塊結構部分和線部分,且所述凸塊結構部分和所述線部分兩者用以支撐所述屏蔽線。
Description
本發明的某些實施例涉及半導體裝置和製作半導體裝置的方法。
<相關申請案的交叉引用>
本申請案主張2016年12月3日申請的第15/368,583號美國專利申請案和2016年3月10日申請的第10-2016-0028899號韓國專利申請案的優先權,所述兩個申請案的全部內容在此以引用的方式併入本文中。
因為製造為具有各種配置的多種半導體裝置和用於交換各種信號的電子裝置整合到各種電子裝置中,所以眾所周知半導體裝置和電子裝置在半導體裝置和電子裝置的電操作期間發射電磁干擾。
電磁干擾可從按窄間隔安裝於主機板上的半導體裝置和電子裝置發射,且相鄰半導體裝置可受到電磁干擾的直接或間接影響。
因此,為了部分地屏蔽半導體裝置,可使用線或屏蔽層。然而,在這種情況下,使用線或屏蔽層可能增大半導體裝置的大小。
本發明提供一種半導體裝置,其包含橫跨半導體晶粒形成的屏蔽
線和支撐所述屏蔽線的輔助結構,由此減小半導體封裝的大小同時屏蔽從所述半導體晶粒產生的電磁干擾。
本發明的以上和其它目標將在若干實施例的以下描述中進行闡述或從所述以下描述中顯而易見。
根據本發明的實施例的一態樣,提供一種半導體裝置,其包含:基板,在其上安裝有至少一個電路裝置;半導體晶粒,其與所述電路裝置間隔開且安裝到所述基板上;屏蔽線,其與所述半導體晶粒間隔開且橫跨所述半導體晶粒形成;及輔助結構,其在所述屏蔽線下支撐所述屏蔽線。在一些實施例中,所述輔助結構包括形成為大體上垂直於所述屏蔽線的輔助線。
根據本發明的實施例的另一態樣,提供基板;半導體晶粒,其鄰近於所述基板而安裝;輔助結構,其連接到所述基板;及導電線,其在第一端處連接到所述基板的第一部分,且以物理方式接觸所述輔助結構來增大所述導電線連接到所述基板的角度。根據另一實施例,一種方法包含提供基板,所述基板具有連接到所述基板的表面的半導體晶粒。所述方法包含形成耦合到所述基板的輔助結構和將導電線連接到所述基板,其中所述導電線以物理方式接觸所述輔助結構來增大所述導電線連接到所述基板的角度。
如上文所描述,根據本發明的實施例,因為所述半導體裝置包含與所述半導體晶粒間隔開且橫跨所述半導體晶粒形成的屏蔽線和在所述屏蔽線下支撐所述屏蔽線的輔助結構,所以可減小所述半導體晶粒與所述電路裝置之間的距離,且可屏蔽從所述半導體晶粒產生的電磁干擾,由此減小根據本發明的所述半導體裝置的大小。
另外,根據另一實施例,因為所述半導體裝置包含電連接所述半導體晶粒與所述基板的導電線和在所述導電線下支撐所述導電線的輔助結構,所以可減小所述半導體裝置的大小。
此外,根據另一實施例,所述輔助結構包括鄰近於所述導電線所設置的凸塊結構,以促進具有更陡的傾斜角的所述導電線。在又一實施例中,所述輔助結構包括凸塊結構部分和線部分,且所述凸塊結構部分和所述線部分兩者被用來促進具有甚至更陡的傾斜角的接合線。
100:半導體裝置
110:基板
111:接合墊/第一接合墊
112:接合墊/第二接合墊
120:半導體晶粒
130:電路裝置
140:屏蔽線/屏蔽線結構
150:輔助線
160:凸塊結構
250:輔助線
260:凸塊結構部分
261:線部分
300:半導體裝置
340:屏蔽線
341:第一屏蔽線
342:第二屏蔽線
350:輔助線
450:輔助線/第一輔助線
451:第一支撐部分
452:第二支撐部分
453:平面部分
460:第二輔助線
461:第一支撐部分
462:第二支撐部分
463:平面部分
500:半導體裝置
510:基板
511:接合墊
520:半導體晶粒
521:接合墊
540:導電線
550:輔助線
600:半導體裝置
650:輔助線
700:半導體裝置
710:基板
800:半導體裝置
810:基板
900:半導體裝置
1000:半導體裝置
[圖1]為根據本發明的一實施例的半導體裝置的橫截面圖;[圖2]為圖1中所說明的半導體裝置的平面圖;[圖3A和3B]為圖2的部分“A”的照片;[圖4]為根據本發明的另一實施例的半導體裝置的平面圖;[圖5]為根據本發明的一實施例的半導體裝置的平面圖;[圖6A]為應用根據本發明的一實施例的輔助線的半導體裝置的橫截面圖;[圖6B和6C]為圖6A中所說明的半導體裝置的平面圖;[圖7A]為根據本發明的一實施例的輔助線的正視圖;[圖7B]為應用圖7A中所說明的輔助線的半導體裝置的透視圖;[圖8A]為根據本發明的一實施例的輔助線的正視圖;[圖8B]為應用圖8A中所說明的輔助線的半導體裝置的透視圖;[圖9]為根據本發明的一實施例的半導體裝置的橫截面圖;[圖10]為根據本發明的實施例的半導體裝置的部分橫截面圖;[圖11]為圖10的部分“B”的照片;[圖12]為根據本發明的實施例的半導體裝置的部分橫截面圖;且[圖13]為圖12的部分“C”的照片。
在下文中,將參考隨附圖式詳細地描述各種實施例的範例,使得其可由所屬領域的技術人員製作並使用。
本發明的各個態樣可以許多不同形式具體實現且不應理解為受限於在本文中所闡述的範例實施例。實際上,提供本發明的這些範例實施例是為了使本發明變為充分且完整的,並且向所屬領域的技術人員傳達本發明的各種態樣。
在圖式中,可為了清楚起見而放大層和區域的厚度。此處,類似元件符號通篇指代類似元件。如本文中所使用,術語“和/或”包含相關聯的所列項目中的一或多項的任何和所有組合。另外,應理解,當元件A被稱作“連接到”元件B時,元件A可以直接連接到元件B或者可在元件A與元件B之間存在***元件C以使得元件A可間接地連接到元件B。
另外,本文中所使用的術語僅僅是出於描述特定實施例的目的而並不意圖限制本發明。如本文中所使用,除非上下文另外明確指示,否則單數形式還意圖包含複數形式。將進一步理解,術語包括(comprises/comprising)和/或包含(includes/including)在用於本說明書時規定所陳述特徵、數目、步驟、操作、元件和/或構件的存在,但並不排除一或多個其它特徵、數目、步驟、操作、元件、構件和/或其群組的存在或添加。
應理解,雖然術語第一、第二等可以在本文中使用來描述各個部件、元件、區域、層和/或區段,但是這些部件、元件、區域、層和/或區段應不受這些術語限制。這些術語僅用於區分一個部件、元件、區域、層和/或區段與另一部件、元件、區域、層和/或區段。因此,舉例來說,下文論述的第一部件、第一元件、第一區域、第一層和/或第一區段可被稱為第二部件、第二元件、第二區域、第二層和/或第二區段而不脫離本發明的教示。除非另外規定,否則如
本文所使用的詞語“在......上面”或“在......上”包含所指定元件可以直接或間接物理接觸的定向、放置或關係。除非另外規定,否則如本文所使用的詞語“與......重疊”包含所指定元件可在相同或不同平面中至少部分或完全重合或對準的定向、放置或關係。應進一步理解,下文中所說明並描述的實施例適當地可具有實施例和/或可在無本文中確切地揭示的任何元件的情況下實踐。
圖1為根據一個實施例的半導體裝置100的橫截面圖,圖2為圖1中所說明的半導體裝置的平面圖,圖3A和3B為拍攝圖2的部分“A”的照片,且圖4為根據另一實施例的半導體裝置100的平面圖,該另一實施例為半導體裝置200。
參考圖1和2,根據一實施例的半導體裝置100包含基板110、半導體晶粒120、電路裝置130、屏蔽線140或屏蔽線結構140和例如輔助線150的輔助結構。
在一個實施例中,半導體晶粒120鄰近於基板110安裝或安裝於基板110上。基板110可為(例如)印刷電路板(PCB),PCB包含絕緣層和形成於絕緣層的表面上和/或絕緣層內的多個電路圖案。另外,基板110可為選自由以下各者組成的群組中的一者:剛性印刷電路板、柔性印刷電路板、陶瓷電路板、中介層、和如所屬領域的技術人員已知的類似結構。剛性印刷電路板通常包含作為基底材料的酚醛樹脂或環氧樹脂,且可具有形成於剛性印刷電路板的表面上和/或其內或鄰近於剛性印刷電路板的表面上和/或其內的多個電路圖案。柔性印刷電路板通常包含作為基底材料的聚醯亞胺樹脂,且可具有形成於柔性印刷電路板的表面上和/或其內的多個電路圖案。陶瓷電路板通常包含作為基底材料的陶瓷,且可具有形成於陶瓷電路板的表面和/或其內或鄰近於陶瓷電路板的表面上和/或其內的多個電路圖案。中介層可為矽類中介層或介電類中介層。另外,可在本發明的實施例中使用各種種類的基板,但本發明不特別地限制基板110的種類。
在一些實施例中,半導體晶粒120安裝於基板110上或鄰近於基板
110而安裝。半導體晶粒120可通過導電凸塊(未繪示)或如所屬領域的技術人員已知的其它連接結構電連接到基板110。半導體晶粒120可通過(例如)大規模回焊工藝、熱壓縮工藝或雷射接合工藝電連接到基板110的電路圖案。半導體晶粒120可具有不同類型半導體晶粒的的特徵。半導體晶粒120可包含(例如)處理器晶粒、記憶體晶粒、特殊應用積體電路晶粒、通用邏輯晶粒、主動半導體元件和如所屬領域的技術人員已知的其它電子裝置。在一些實施例中,半導體晶粒120的導電凸塊可包含(例如)導電球(例如焊球)、導電柱(例如銅柱)和/或具有形成於銅柱上的焊料頂蓋的導電樁。
在一些實施例中,電路裝置130安裝於基板110上或鄰近於基板110而安裝,且在半導體晶粒120附近或接近於半導體晶粒120而定位。電路裝置130可為(例如)被動裝置、主動裝置和/或半導體晶粒。電路裝置130可包含在半導體晶粒120附近形成的多個電路裝置。電路裝置130可通過(例如)大規模回焊工藝、熱壓縮工藝或雷射接合工藝電連接到基板110的電路圖案。
根據本發明的實施例,屏蔽線140與半導體晶粒120間隔開且形成為圍繞半導體晶粒120。屏蔽線140可經配置以屏蔽從半導體晶粒120產生的電磁干擾以免發射到外部,或可防止外部電磁干擾穿透到半導體晶粒120中。另外,屏蔽線140用來防止電磁干擾在半導體裝置100的半導體晶粒120與電路裝置130之間發生。因此,屏蔽線140可包含多個屏蔽線且可圍繞半導體晶粒120。在此處,隨著屏蔽線140的數目增大,可提高EMI屏蔽性能。
根據本發明的實施例,屏蔽線140的一端接合到定位在半導體晶粒120的一側處的基板110,且屏蔽線140的另一或相對端接合到定位在半導體晶粒120的另一側處的基板110。更確切地說,屏蔽線140與半導體晶粒120間隔開且屏蔽線140橫跨半導體晶粒120形成以便與半導體晶粒120重疊。在一些實施例中,屏蔽線140可接合或附接到形成於基板110上的接合墊111和112。定位在半導
體晶粒120的一側處的接合墊可稱作第一接合墊111,且定位在半導體晶粒120的另一側處的接合墊可稱作第二接合墊112。更確切地說,在一些實施例中,屏蔽線140的一端接合到第一接合墊111,然後屏蔽線140的另一端橫跨半導體晶粒120接合到第二接合墊112。根據本發明的實施例,屏蔽線140可接合到第二接合墊112,同時與輔助線150成銳利或陡峭角度,此稍後將在描述輔助線150的過程中更詳細地加以描述。
第二接合墊112定位於半導體晶粒120與電路裝置130之間。在一個實施例中,第一接合墊111和第二接合墊112可電連接到基板110的接地。因此,接合到第一接合墊111和第二接合墊112的屏蔽線140也可電連接到基板110的接地(ground)。雖然在圖2中說明形成為單一單元的第一接合墊111,但是其可由形成為彼此間隔開或側向地分離的多個單元構成以便分別對應於多個屏蔽線140。同樣地,雖然在圖2中說明形成為單一單元的第二接合墊112,但是其可由形成為彼此間隔開或側向地分離的多個單元構成以便分別對應於多個屏蔽線140。然而,因為第一接合墊111和第二接合墊112連接到接地,所以第一接合墊111和第二接合墊112中的每一者更優選地形成為單一單元。屏蔽線140可由金(Au)、銀(Ag)、銅(Cu)和/或如所屬領域的技術人員已知的其它材料製成。另外,在一些實施例中,可通過另外將絕緣材料塗佈於形成屏蔽線140的前述金屬上來形成屏蔽線140。因此,可防止屏蔽線140短接(short)到半導體裝置100中所設置的元件。在此處,塗佈於屏蔽線140上的絕緣材料可由(例如)選自由以下各者組成的群組的一者製成:聚丙烯、聚乙烯、聚醯亞胺、聚碳酸酯和/或其等效物,但本發明的各態樣並不限於此。
根據本發明的實施例,輔助線150定位於屏蔽線140下且形成為與屏蔽線140相交。在一些實施例中,輔助線150定位為大體上垂直於屏蔽線140且在第二接合墊112附近形成。更確切地說,輔助線150定位於半導體晶粒120與第
二接合墊112之間。另外,因為輔助線150形成於多個屏蔽線140中的每一者中,所以輔助線150可排列成線以大體上彼此平行。在一些實施例中,輔助線150具有比屏蔽線140小的寬度且以弓形形成。另外,在其它實施例中,輔助線150的厚度可等於或大於屏蔽線140的厚度。然而,因為輔助線150需要支撐屏蔽線140,所以輔助線150更優選地比屏蔽線140厚。
根據本發明的實施例,輔助線150支撐屏蔽線140且增大屏蔽線140接合到第二接合墊112的角度。更確切地說,如圖1中所說明,屏蔽線140的一端接合到第一接合墊111,且屏蔽線140的另一端橫跨半導體晶粒120接合到第二接合墊112。當無輔助線存在時,屏蔽線140需要接合到圖1的虛線結束處的部分。舉例來說,當無輔助線存在時,屏蔽線可以約45度的角度接合到第二接合墊。根據本發明的實施例,輔助線150形成於屏蔽線140下,以使得屏蔽線140與輔助線150接觸。因此,屏蔽線140接合到第二接合墊112的角度(a)快速地增大或更陡峭地傾斜。根據本發明的實施例,屏蔽線可以大於45度的角度接合或附接到第二接合墊112。根據本發明的實施例,屏蔽線140可以約70度到約90度範圍內的角度接合到第二接合墊112。此外,根據本發明的實施例,隨著輔助線150以增大的力支撐屏蔽線140,也就是說,隨著輔助線150的厚度變得大於屏蔽線140的厚度,屏蔽線140可以約90度的角度接合到第二接合墊112。因此,根據本發明的實施例,可減小半導體晶粒120與電路裝置130之間的距離,由此減小半導體裝置100的大小。舉例來說,半導體晶粒120與電路裝置130之間的距離(t)可為約100微米或更小。另外,輔助線150可由金(Au)、銀(Ag)、銅(Cu)和/或如所屬領域的技術人員已知的其它材料製成。另外,可通過另外將絕緣材料塗佈於形成輔助線150的前述金屬上來形成輔助線150。因此,可防止輔助線150短接到半導體裝置100中所設置的元件。在此處,塗佈於輔助線150上的絕緣材料可由(例如)選自由以下各者組成的群組的一者製成:聚丙烯、聚乙烯、聚醯亞胺、聚碳酸酯
和/或如所屬領域的技術人員已知的其它材料。
如圖4中所說明,在半導體裝置200中,輔助線250和其鄰近的輔助線可交替地排列。更確切地說,第一組(例如,奇數編號)輔助線250可經排列以接近於半導體晶粒120,且第二組(例如,偶數編號)輔助線250可經排列以接近於第二接合墊112。根據本發明的實施例,可更密集地排列屏蔽線140,由此提高半導體晶粒120的EMI屏蔽性能。
如上文所描述,根據本發明的實施例的半導體裝置100包含與半導體晶粒120間隔開且圍繞半導體晶粒120的屏蔽線140;及在屏蔽線140下支撐屏蔽線140的輔助線150(或在半導體裝置200中的輔助線250),由此減小半導體晶粒120與電路裝置130之間的距離同時屏蔽從半導體晶粒120產生的電磁干擾。因此,根據本發明的實施例的半導體裝置100或半導體裝置200的大小可相比於相關裝置減小。
圖5為根據再一實施例的半導體裝置300的平面圖。參考圖5,在一些實施例中,半導體裝置300包含基板110、半導體晶粒120、電路裝置130、屏蔽線340和例如輔助線150的輔助結構。圖5中所說明的半導體裝置300與圖2中所說明的半導體裝置100大體上相同,且以下描述將集中在半導體裝置100與半導體裝置300之間的差異。
根據本發明的實施例,屏蔽線340配置與半導體晶粒120間隔開且被設置為圍繞半導體晶粒120。屏蔽線340包含橫跨半導體晶粒120從半導體晶粒120的一側形成到另一側的第一屏蔽線341和形成為大體上垂直於第一屏蔽線341的第二屏蔽線342。更確切地說,相比於圖2中所說明的半導體裝置100,圖5中所說明的半導體裝置300進一步包含形成為大體上垂直於第一屏蔽線341的第二屏蔽線342,第一屏蔽線341對應於圖2中所說明的半導體裝置100的屏蔽線140。因此,相比於圖2中所說明的半導體裝置100,圖5中所說明的半導體裝置300
的半導體晶粒120可表明提高的EMI屏蔽性能。根據本發明的實施例,第一屏蔽線341和第二屏蔽線342分別包含多個第一屏蔽線和多個第二屏蔽線。在一些實施例中,當在形成第一屏蔽線341之後形成第二屏蔽線342時,第二屏蔽線342可與第一屏蔽線341接觸。另外,第一屏蔽線341和第二屏蔽線342可電連接到基板110的接地(ground)。在一些實施例中,屏蔽線340可鑒於配置而與圖2中所說明的屏蔽線140大體上相同,除了其包含第一屏蔽線341和形成為大體上垂直於第一屏蔽線341的第二屏蔽線342以外,且將不重複其詳細描述。
圖6A為應用根據一實施例的輔助結構(例如輔助線350)的半導體裝置600的橫截面圖,且圖6B和6C為圖6A中所說明的半導體裝置600的平面圖。
參考圖6A,輔助線350可包含一或多個輔助線。舉例來說,如圖6A中所說明,兩個輔助線350可支撐一個單一屏蔽線140。因此,輔助線350可相比於使用一個單一輔助線的情況更牢固地支撐屏蔽線140。根據一個實施例,輔助線350可形成為大體上彼此平行,如圖6B中所說明。替代地,如圖6C中所說明,輔助線350可形成為跨越彼此或彼此重疊。另外,雖然在圖6A到6C中說明包含兩個輔助線的輔助線350,但是其可包含大於兩個輔助線。
圖7A為根據一個實施例的輔助結構(例如輔助線450)的正視圖,且圖7B為應用圖7A中所說明的輔助線450的半導體裝置700的透視圖。
參考圖7A和7B,輔助線450包含第一支撐部分451、形成為與第一支撐部分451間隔開的第二支撐部分452和連接第一支撐部分451與第二支撐部分452且形成為平面的平面部分453。根據本發明的實施例,平面部分453經配置以支撐一或多個屏蔽線140。因此,一或多個屏蔽線140可以平面方式與平面部分453接觸。第一支撐部分451可形成為大體上垂直於基板710,且第二支撐部分452可形成為相對於基板710傾斜。
圖8A為根據另一實施例的輔助線450的正視圖,且圖8B為應用圖8A中所說明的輔助線450的半導體裝置800的透視圖。
參考圖8A和8B,根據本發明的再一實施例的輔助線包含第一輔助線450和第二輔助線460。第一輔助線450與第二輔助線460彼此連接,且形成為彼此對稱。在此處,第一輔助線450類似於圖7A中所說明的輔助線450。
第一輔助線450包含第一支撐部分451、與第一支撐部分451間隔開的第二支撐部分452和連接第一支撐部分451與第二支撐部分452且形成為平面的平面部分453。另外,第二輔助線460包含第一支撐部分461、與第一支撐部分461間隔開的第二支撐部分462和連接第一支撐部分461與第二支撐部分462且形成為平面的平面部分463。第一支撐部分451、461可形成為大體上垂直於基板810,且第二支撐部分452、462可形成為相對於基板810傾斜。另外,第一輔助線450與第二輔助線460可彼此耦合,使得第一輔助線450的第二支撐部分452與第二輔助線460的第二支撐部分462彼此連接或接觸。另外,第一輔助線450的平面部分453和第二輔助線460的平面部分463中的每一者支撐一或多個屏蔽線140。因此,一或多個屏蔽線140可以平面方式與第一輔助線450的平面部分453和第二輔助線460的平面部分463接觸。另外,雖然在圖8A和8B中說明彼此相交的兩個輔助線450與460,但是可設置兩個或兩個以上輔助線。更確切地說,輔助線可包含多個輔助線,其可彼此相交且可(例如)排列成線。
圖9為根據另一實施例的半導體裝置500的橫截面圖。參考圖9,半導體裝置500包含基板510、半導體晶粒520、導電線540和例如輔助線550的輔助結構。
在一些實施例中,半導體晶粒520安裝於基板510上或鄰近於基板510而安裝。舉例來說,基板510可為印刷電路板(PCB),其包含絕緣層和形成於絕緣層的表面上和/或絕緣層內的多個電路圖案。另外,基板510可為選自由以
下各者組成的群組中的一者:剛性印刷電路板、柔性印刷電路板、陶瓷電路板、中介層和如所屬領域的技術人員已知的其它結構。另外,可在本發明的實施例中使用各種類型的基板。在本發明的實施例中,多個接合墊511形成於基板510上或鄰近於基板510而形成。
半導體晶粒520安裝於基板510上或鄰近於基板510而安裝。在一個實施例中,可使用黏著構件將半導體晶粒520安裝於基板510上。半導體晶粒520可具有不同類型半導體晶粒的的特徵。舉例來說,半導體晶粒520可包含處理器晶粒、記憶體晶粒、特殊應用積體電路晶粒、通用邏輯晶粒、主動半導體元件和如所屬領域的技術人員已知的其它電子裝置。另外,多個接合墊521形成於半導體晶粒520的頂部表面上或鄰近於所述頂部表面而形成。
在本發明的實施例中,導電線540將半導體晶粒520電連接到基板510。更確切地說,導電線540的一端接合到半導體晶粒520的接合墊521,且導電線540的另一且相對端接合到基板510的接合墊511。在此處,導電線540可接合到基板510的接合墊511,同時與輔助線550成更銳利或陡峭角度,此稍後將在下文中更詳細地加以描述。在一些實施例中,導電線540可包含多個導電線。導電線540可由金(Au)、銀(Ag)、銅(Cu)和/或如所屬領域的技術人員已知的其它材料製成。
根據本發明的實施例,輔助線550定位於導電線540下且形成為與導電線540相交。輔助線550形成為大體上垂直於導電線540且定位於半導體晶粒520與基板510的接合墊511之間。另外,因為輔助線550形成於多個導電線540中的每一者下,所以輔助線550可排列成線以大體上彼此平行。在一些實施例中,輔助線550具有比導電線540小的寬度且以弓形形成。另外,輔助線550的厚度可等於或大於導電線540的厚度。在其它實施例中,輔助線550可比導電線540厚。
根據本發明的實施例,輔助線550支撐導電線540且增大導電線
540接合到基板510的接合墊511的角度。更確切地說,如圖9中所說明,導電線540的一端接合到半導體晶粒520的接合墊521,然後導電線540的另一端接合到基板510的接合墊511。當無輔助線存在時,導電線540需要接合到圖9的虛線結束處的部分。舉例來說,當無輔助線存在時,導電線可以約45度的角度接合到基板的接合墊。然而在本發明中,輔助線550形成於導電線540下,以使得導電線540與輔助線550接觸。因此,更快速或急劇地增大導電線540接合到基板510的接合墊511的角度(a)。更確切地說,導電線540可以約70度到約90度範圍內的角度接合到基板510的接合墊511。另外,根據本發明的實施例,隨著輔助線550以增大的力支撐導電線540,也就是說,隨著輔助線550的厚度變得大於導電線540的厚度,導電線540可以約90度的角度接合到基板510的接合墊511。因此,根據本發明的實施例,可減小將半導體晶粒520連接到基板510的導電線540的寬度,由此減小半導體裝置500的大小。輔助線550可由金(Au)、銀(Ag)、銅(Cu)和/或如所屬領域的技術人員已知的其它材料製成。另外,可通過另外將絕緣材料塗佈於形成輔助線550的前述金屬上來形成輔助線550。因此,可防止輔助線550短接到半導體裝置500中所設置的元件。在此處,塗佈於輔助線550上的絕緣材料可由(例如)選自由以下各者組成的群組的一者製成:聚丙烯、聚乙烯、聚醯亞胺、聚碳酸酯和/或如所屬領域的技術人員已知的其它材料。
替代地,輔助線550還可形成為具有各種形狀,包含(例如)圖6A到8B中所說明的形狀。
圖10說明根據又一實施例的半導體裝置900的部分橫截面圖,且圖11為拍攝圖10的部分“B”的照片。參考圖10,半導體裝置900包含基板110、半導體晶粒120、導電線(例如屏蔽線140)和包括凸塊結構160的輔助結構。
根據本發明的實施例,凸塊結構160鄰近於基板110形成,使得屏蔽線140在屏蔽線140附接到第二接合墊112之處鄰接或接近於基板110而抵靠著
凸塊結構160定位。在一個優選實施例中,屏蔽線140的一部分直接接觸凸塊結構160以使得凸塊結構160支撐、設置或促進快速增大或相比於相關裝置更陡峭傾斜的屏蔽線140接合到第二接合墊112的角度。根據本發明的實施例,屏蔽線140可按大於約50度的角度接合到第二接合墊112。舉例來說,當無凸塊結構存在時,屏蔽線可以小於約45度的角度接合到第二接合墊。
在一些實施例中,凸塊結構160可為在設置屏蔽線140之前形成於第二接合墊112上的凸塊球。凸塊結構160可由金(Au)、銀(Ag)、銅(Cu)和/或如所屬領域的技術人員已知的其它材料製成,且可使用(例如)球接合和線尾移除技術形成。在一些實施例中,第二接合墊112具有約100微米的寬度來容納凸塊結構160。應理解,凸塊結構160可與在本文中所說明的實施例中的任一者組合使用。舉例來說,屏蔽線140可替代地為導電互連線,例如作為圖10中所進一步說明的具有在半導體晶粒120上附接到接合墊521的一相對端的導電線540。
如上文所描述,根據本發明的實施例的半導體裝置900包含與半導體晶粒120間隔開的屏蔽線140,且屏蔽線可圍繞半導體晶粒120,如(例如)圖2、4和5中所進一步說明。凸塊結構160抵靠著屏蔽線140的一部分而定位,由此減小半導體晶粒120與其它電路裝置(例如,圖1中所說明的電路裝置130)之間的距離,同時屏蔽從半導體晶粒120產生的電磁干擾。在一個實施例中,此距離可為100微米或更小。因此,可減小根據本發明的實施例的半導體裝置900的大小。
圖12說明根據又一實施例的半導體裝置1000的部分橫截面圖,且圖13為拍攝圖12的部分“C”的照片。參考圖12,半導體裝置1000包含基板110、半導體晶粒120、導電線(例如屏蔽線140)和輔助結構(例如輔助線650),輔助線650具有凸塊結構部分260和連接到凸塊結構部分260的線部分261。
根據本發明的實施例,輔助線650的凸塊結構部分260和線部分
261一起支撐屏蔽線140,且增大屏蔽線140接合到第二接合墊112的角度。當無輔助線和凸塊結構存在時,屏蔽線可以小於約45度的角度接合到第二接合墊。根據本發明的實施例,輔助線650的線部分261形成於屏蔽線140下,且輔助線650的凸塊結構部分260與屏蔽線140的基底形成為鄰近第二接合墊112而彼此鄰接,以使得屏蔽線140與線部分261和凸塊結構部分260兩者皆接觸。因此,屏蔽線140接合到第二接合墊112的角度快速增大或更陡峭地傾斜。根據本發明的實施例,屏蔽線140可按大於約80度的角度接合到第二接合墊112。在其它實施例中,屏蔽線140可以約70度到約90度的範圍內的角度接合到第二接合墊。
此外,根據本發明的實施例,隨著輔助線150的線部分261以增大的力支撐屏蔽線140,也就是說,隨著輔助線150的線部分261的厚度變得大於屏蔽線140的厚度,屏蔽線140可以約90度的角度接合到第二接合墊112。因此,根據本發明的實施例,可減小半導體晶粒120與鄰近電路裝置(例如,圖1中所說明的電路裝置130)之間的距離,由此減小半導體裝置1000的大小。在一個實施例中,此距離為100微米或更小。
在一些實施例中,輔助線650包含凸塊結構部分260,且線部分261可由金(Au)、銀(Ag)、銅(Cu)和/或如所屬領域的技術人員已知的其它材料製成。另外,在一些實施例中,可通過另外將絕緣材料塗佈於形成輔助線650的前述金屬上來形成輔助線650。因此,可防止輔助線650短接到半導體裝置1000中所設置的元件。在此處,塗佈於輔助線650上的絕緣材料可由(例如)選自由以下各者組成的群組的一者製成:聚丙烯、聚乙烯、聚醯亞胺、聚碳酸酯和/或如所屬領域的技術人員已知的其它材料。應理解,具有凸塊結構部分260和線部分261的輔助線650可與在本文中所說明的實施例中的任一者組合使用。舉例來說,屏蔽線140可替代地為導電互連線,例如作為圖12中所進一步說明的具有在半導體晶粒120上附接到接合墊521的一相對端的導電線540。在一些實施例中,凸塊
結構260附接到第二接合墊112,且線部分261在一端處連接到凸塊結構260且在另一端處連接到第二接合墊112。
在形成本文中所描述的實施例的過程中,已發現優選地在按更陡峭角度形成導電線(例如導電線140、340、540)時使用具有伸展的瓶頸高度的毛細管線接合工具。此外,此將避免線上接合過程期間觸摸到線自身或觸摸到鄰近電路裝置。在一個實施例中,已發現大於約450微米的毛細管瓶頸高度相比於約250微米的常規瓶頸高度是優選的。
從所有前述內容中,所屬領域的技術人員可確定根據半導體裝置的一個實施例,輔助線形成於半導體晶粒與第二接合墊之間。在另一實施例中,屏蔽線以約70度到約90度的範圍內的角度連接到第二接合墊。在又一實施例中,第二接合墊定位於半導體晶粒與電路裝置之間。在再一實施例中,其間定位第二接合墊的半導體晶粒與電路裝置之間的距離小於約100微米。
在另一實施例中,輔助結構包括輔助線;屏蔽線以物理方式接觸輔助線;屏蔽線電連接到基板的接地;輔助線比屏蔽線厚;屏蔽線和輔助線由金屬製成;且輔助線進一步包含塗佈於金屬上的絕緣材料。
在又一實施例中,輔助結構包括一或多個輔助線且以弓形形成;且一或多個輔助線形成為彼此平行或彼此相交。在再一實施例中,輔助結構包含輔助線,其包括垂直於基板的第一支撐部分;與第一支撐部分間隔開且形成為相對於基板傾斜的第二支撐部分;和連接第一支撐部分與第二支撐部分且形成為平面的平面部分。
在另一實施例中,平面部分支撐一或多個屏蔽線。在又一實施例中,輔助線包含多個輔助線,且多個輔助線中的第二支撐部分形成為彼此相交。在再一實施例中,輔助結構包括凸塊結構。
雖然已參考某些支援性實施例描述根據本發明的各種態樣的半
導體裝置,但是所屬領域的技術人員應理解本發明不限於所揭示特定實施例,而是本發明應包含屬於所附申請專利範圍的範疇內的所有實施例。
100:半導體裝置
110:基板
111:接合墊/第一接合墊
112:接合墊/第二接合墊
120:半導體晶粒
130:電路裝置
140:屏蔽線/屏蔽線結構
150:輔助線
Claims (23)
- 一種製造半導體裝置的方法,其包括:提供基板;安裝半導體構件到所述基板;僅沿著所述半導體構件的一側附接輔助結構至所述基板;以及附接第一屏蔽線的相對端至所述基板,其中:所述第一屏蔽線與所述半導體構件的主要表面間隔開且跨越所述半導體構件的主要表面延伸;以及所述第一屏蔽線在所述相對端中的任一端之外的位置處與所述輔助結構以物理方式接觸;以及所述輔助結構在從所述屏蔽線的最大抬升高度橫向偏離的點處與所述第一屏蔽線接觸。
- 根據請求項1所述的方法,其進一步包括:安裝電路裝置在所述基板上且與所述半導體構件間隔開,以提供在所述半導體構件和所述電路裝置之間的空間,其中:提供所述基板包括提供包含第一接合墊和第二接合墊的所述基板,所述第一接合墊在所述半導體構件的所述一側處以及所述第二接合墊在所述半導體構件的相對側處;附接所述輔助結構包括附接輔助線的第一端和所述輔助線的相對的第二端至所述空間內的所述基板;以及附接所述第一屏蔽線的所述相對端包括附接所述第一屏蔽線的的一端到所述第一接合墊且附接所述第一屏蔽線的另一端到所述第二接合墊。
- 根據請求項1所述的方法,其中:附接所述輔助結構包括: 沿著所述半導體構件的所述一側附接第一輔助線的相對端至所述基板的第一部分;以及附接第二輔助線的相對端至所述基板的第二部分;所述第一屏蔽線與所述第一輔助線以物理方式接觸;所述方法進一步包括:附接第二屏蔽線至所述基板,使得所述第二屏蔽線延伸跨越所述半導體構件的所述主要表面且與所述第一屏蔽線垂直,並且所述第二屏蔽線與所述第二輔助線以物理方式接觸;以及所述第一輔助線和所述第二輔助線中至少一個具有弓形形狀。
- 根據請求項1所述的方法,其中附接所述輔助結構包含附接輔助線包括凸塊結構部分以及連接到所述凸塊結構部分的線部分;以及附接所述第一屏蔽線的所述相對端包括附接所述第一屏蔽線的所述相對端中的一端,使得所述第一屏蔽線以物理方式接觸所述凸塊結構部分。
- 一種製造半導體裝置的方法,其包括:提供基板;提供安裝於所述基板之上的半導體構件;附接輔助線至所述基板,所述輔助線包括凸塊結構部分以及線部分,所述線部分具有連接到所述凸塊結構部分的第一端;以及附接屏蔽線至所述基板,使得所述屏蔽線與所述半導體構件間隔開且跨越所述半導體構件延伸,以及所述屏蔽線以物理方式接觸所述凸塊結構部分和所述線部分兩者並且相對於所述基板的主要表面形成一角度。
- 根據請求項5所述的方法,其中:附接所述輔助線包括附接所述線部分的第二端到所述基板。
- 根據請求項5所述的方法,其中:附接所述屏蔽線包括進行附接使得所述角度處於約70度到約90度的範圍中。
- 根據請求項5所述的方法,其中:附接所述輔助線包括附接以絕緣材料塗覆的所述輔助線。
- 一種用於形成半導體裝置的方法,其包括:提供基板,所述基板具有耦合到所述基板的表面的半導體構件;形成耦合到所述基板的輔助線;以及將導電線連接到所述基板,其中所述導電線以物理方式接觸所述輔助線來增大所述導電線連接到所述基板的角度,並且所述導電線與所述輔助線大致上垂直,其中:所述導電線在從所述導電線的最大抬升高度橫向偏離的點處與所述輔助線接觸。
- 根據請求項9所述的方法,其中:提供所述基板包括提供包含半導體晶粒的所述半導體構件。
- 根據請求項9所述的方法,其中:形成所述輔助線包括附接所述輔助線的相對端至所述基板,使得所述輔助線的一部分包括弓形形狀。
- 根據請求項9所述的方法,其中:形成所述輔助線包括形成凸塊結構部分和連接到所述凸塊結構部分的線部分。
- 一種形成半導體裝置的方法,其包括:提供基板,所述基板包括安裝成與所述基板的主要表面相鄰的半導體構件;形成輔助結構,所述輔助結構包括具有第一端和相對的第二端的第一輔助 線,其中:所述第一端附接到所述基板的第一部分;所述第二端附接到所述基板的第二部分;所述第一部分和所述第二部分是在所述半導體構件的同一側上並且與所述半導體構件橫向地相間隔;以及形成導電線,其藉由將所述導電線的第一端沿著所述半導體構件的所述第一側連接到所述基板的第三部分並且與所述輔助結構以物理方式接觸,延伸所述導電線跨越所述半導體構件的所述主要表面,以及附接所述導電線的第二端,以沿著與所述半導體構件的所述第一側不同的所述半導體構件的第二側來附接到所述基板的第四部分,其中:靠近所述第一端的所述導電線相對於所述基板的表面形成一角度;以及所述導電線在從所述導電線的最大抬升高度橫向偏離的點處與所述輔助結構接觸。
- 根據請求項13所述的方法,其中:形成所述導電線包括形成大於70度且小於90度的範圍中的所述角度。
- 根據請求項13所述的方法,其中:形成所述輔助結構進一步包括形成第二輔助線,所述第二輔助線沿著所述半導體構件的所述第一側附接在相對端處;以及形成所述導電線包括形成在所述第二輔助線之上延伸的所述導電線。
- 根據請求項13所述的方法,其中,其中:形成所述輔助結構進一步包括形成第二輔助線,所述第二輔助線沿著所述半導體構件的所述第一側附接在相對端處,使得所述第二輔助線和所述第一輔 助線彼此重疊。
- 一種製造半導體裝置的方法,其包括:提供具有接合墊的基板;附接半導體構件至所述基板;沿著所述半導體構件的第一側將輔助結構連接到所述基板,其中:所述輔助結構包括線部分,所述線部分具有沿著所述半導體構件的所述第一側附接到所述基板的兩相對端;以及所述線部分的一部分在所述基板和所述接合墊之上延伸;以及導電線的第一端連接到所述接合墊;在所述第一端以外的位置處以物理方式接觸所述導電線和所述輔助結構來增大所述導電線連接到所述接合墊的角度;延伸所述導電線以跨越所述半導體構件的主要表面;以及沿著與所述半導體構件的所述第一側不同的所述半導體構件的第二側將所述導電線的第二端連接至所述基板的第二部分,其中:所述導電線在所述導電線的從所述導電線的最大抬升高度橫向偏離的位置處與所述輔助結構接觸。
- 根據請求項17所述的方法,其中:連接所述導電線的所述第一端的步驟發生在連接所述導電線的所述第二端的步驟之前;以及連接所述輔助結構包括將所述線部分的所述兩相對端附接至比所述導電線的所述第一端更靠近所述半導體構件的所述第一側之所述基板。
- 根據請求項17所述的方法,其中:連接所述輔助結構包括:附接形成為弓形形狀的所述線部分;以及 提供包括凸塊結構的所述相對端中的一端;以及連接所述導電線包括將所述導電線以物理方式接觸到所述凸塊結構且以物理方式接觸所述線部分的另一部分。
- 一種製造半導體裝置的方法,其包括:提供基板,所述基板具有安裝至所述基板的第一表面的半導體構件;連接第一輔助線以與所述基板的所述第一表面相鄰;以及連接第一屏蔽線的相對端以與所述基板的所述第一表面相鄰,同時使用所述第一輔助線以支撐所述第一屏蔽線,其中:所述第一屏蔽線與所述半導體構件的主要表面相間隔並且跨越所述半導體構件的所述主要表面而形成;所述第一屏蔽線在除了所述第一屏蔽線的相對端中的任一端之外的位置處以物理方式接觸所述第一輔助線;以及所述第一屏蔽線在從所述第一屏蔽線的最大抬升高度橫向偏離的點處與所述第一輔助線以物理方式接觸。
- 根據請求項20所述的方法,其中:連接所述第一輔助線包括連接所述第一輔助線包含:第一支撐部分,其與所述基板的所述第一表面垂直;第二支撐部分,其與所述第一支撐部分相間隔並且形成為相對於所述基板的所述第一表面傾斜;以及第三支撐部分,其連接所述第一支撐部分和所述第二支撐部分並且形成為平坦的。
- 根據請求項20所述的方法,其進一步包括:連接第二輔助線以與所述基板的所述第一表面相鄰且靠近所述第一輔助線,使得所述第一輔助線和所述第二輔助線在平面圖中彼此交錯,其中: 所述位置靠近所述第一輔助線和所述第二輔助線彼此交錯之處。
- 根據請求項20所述的方法,其進一步包括:連接第二輔助線以與所述基板的所述第一表面相鄰;以及連接第二屏蔽線的相對端以與所述基板的所述第一表面相鄰且與所述第二輔助線以物理方式接觸,使得所述第二輔助線支撐所述第二屏蔽線,其中:所述第一輔助線和所述第二輔助線交替地連接到所述基板的所述第一表面且所述第一輔助線和所述第二輔助線在所述半導體構件的同一側上,使得所述第一輔助線或所述第二輔助線中的一者配置成橫向地更靠近所述半導體構件的所述同一側。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020160028899A KR101815754B1 (ko) | 2016-03-10 | 2016-03-10 | 반도체 디바이스 |
KR10-2016-0028899 | 2016-03-10 | ||
US15/368,583 US10141269B2 (en) | 2016-03-10 | 2016-12-03 | Semiconductor device having conductive wire with increased attachment angle and method |
US15/368,583 | 2016-12-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202111909A TW202111909A (zh) | 2021-03-16 |
TWI739662B true TWI739662B (zh) | 2021-09-11 |
Family
ID=59787031
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW109139733A TWI739662B (zh) | 2016-03-10 | 2017-01-19 | 具有增大的附接角度的導電線之半導體裝置及方法 |
TW106101845A TWI713187B (zh) | 2016-03-10 | 2017-01-19 | 具有增大的附接角度的導電線之半導體裝置及方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106101845A TWI713187B (zh) | 2016-03-10 | 2017-01-19 | 具有增大的附接角度的導電線之半導體裝置及方法 |
Country Status (4)
Country | Link |
---|---|
US (3) | US10141269B2 (zh) |
KR (1) | KR101815754B1 (zh) |
CN (3) | CN206685370U (zh) |
TW (2) | TWI739662B (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101815754B1 (ko) * | 2016-03-10 | 2018-01-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 |
EP3440698A4 (en) * | 2016-04-01 | 2020-02-12 | INTEL Corporation | SEMICONDUCTOR HOUSING WITH STRUCTURES FOR SHIELDING ELECTROMAGNETIC INTERFERENCES |
US10271421B2 (en) * | 2016-09-30 | 2019-04-23 | Avago Technologies International Sales Pte. Limited | Systems and methods for providing electromagnetic interference (EMI) shielding between inductors of a radio frequency (RF) module |
US10204842B2 (en) * | 2017-02-15 | 2019-02-12 | Texas Instruments Incorporated | Semiconductor package with a wire bond mesh |
DE102017209413A1 (de) * | 2017-06-02 | 2018-12-06 | Robert Bosch Gmbh | Sensorvorrichtung zum Überwachen zumindest einer Batteriezelle |
US20180374798A1 (en) | 2017-06-24 | 2018-12-27 | Amkor Technology, Inc. | Semiconductor device having emi shielding structure and related methods |
CN111699552B (zh) * | 2018-02-08 | 2023-08-15 | 株式会社村田制作所 | 高频模块 |
WO2019230705A1 (ja) * | 2018-06-01 | 2019-12-05 | 株式会社村田製作所 | 高周波モジュール |
US20200043864A1 (en) * | 2018-08-03 | 2020-02-06 | Murata Manufacturing Co., Ltd. | Module |
US11227840B2 (en) | 2018-08-03 | 2022-01-18 | Murata Manufacturing Co., Ltd. | Electronic module having improved shield performance |
JP6900947B2 (ja) * | 2018-12-28 | 2021-07-14 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
WO2021020331A1 (ja) * | 2019-08-01 | 2021-02-04 | 株式会社村田製作所 | モジュール |
WO2021039325A1 (ja) * | 2019-08-23 | 2021-03-04 | 株式会社村田製作所 | モジュール |
CN114521290A (zh) * | 2019-09-27 | 2022-05-20 | 株式会社村田制作所 | 模块 |
CN112992881A (zh) * | 2019-12-17 | 2021-06-18 | 江苏长电科技股份有限公司 | 电磁屏蔽封装结构 |
TWI718838B (zh) * | 2020-01-06 | 2021-02-11 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
US11450618B2 (en) | 2020-01-17 | 2022-09-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of compartment shielding using bond wires |
TWI767243B (zh) * | 2020-05-29 | 2022-06-11 | 矽品精密工業股份有限公司 | 電子封裝件 |
JP7333120B2 (ja) * | 2020-12-21 | 2023-08-24 | 株式会社新川 | ワイヤ構造及びワイヤ構造形成方法 |
US11935844B2 (en) * | 2020-12-31 | 2024-03-19 | Texas Instruments Incorporated | Semiconductor device and method of the same |
CN112992707B (zh) * | 2021-04-29 | 2021-08-06 | 甬矽电子(宁波)股份有限公司 | 电磁屏蔽结构制作工艺和电磁屏蔽结构 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040166763A1 (en) * | 2002-08-14 | 2004-08-26 | Kenji Hanada | Manufacturing method of solid-state image sensing device |
US20060091523A1 (en) * | 2004-10-29 | 2006-05-04 | Yoshihiko Shimanuki | Semiconductor device and a method for manufacturing of the same |
TWI466262B (zh) * | 2012-10-17 | 2014-12-21 | Powertech Technology Inc | 電磁干擾遮蔽層連接至接地訊號之導線架型半導體封裝構造 |
TWI489610B (zh) * | 2010-01-18 | 2015-06-21 | 矽品精密工業股份有限公司 | 具電磁遮蔽之封裝結構之製法 |
TWM509429U (zh) * | 2013-07-03 | 2015-09-21 | Rosenberger Hochfrequenztech | 具低電磁干擾互連結構的晶粒封裝 |
Family Cites Families (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2796343B2 (ja) * | 1989-04-07 | 1998-09-10 | 株式会社日立製作所 | 半導体装置又は半導体集積回路装置及びその製造方法 |
US5043534A (en) | 1990-07-02 | 1991-08-27 | Olin Corporation | Metal electronic package having improved resistance to electromagnetic interference |
JPH04165655A (ja) * | 1990-10-29 | 1992-06-11 | Sanyo Electric Co Ltd | 高周波半導体装置 |
US5557142A (en) | 1991-02-04 | 1996-09-17 | Motorola, Inc. | Shielded semiconductor device package |
US5444303A (en) * | 1994-08-10 | 1995-08-22 | Motorola, Inc. | Wire bond pad arrangement having improved pad density |
US5614694A (en) | 1995-03-31 | 1997-03-25 | Motorola, Inc. | One piece open and closable metal RF shield |
JP3741184B2 (ja) * | 1998-07-27 | 2006-02-01 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置 |
JP3745156B2 (ja) * | 1999-04-02 | 2006-02-15 | シャープ株式会社 | 光通信用半導体受光デバイス |
US6538336B1 (en) * | 2000-11-14 | 2003-03-25 | Rambus Inc. | Wirebond assembly for high-speed integrated circuits |
US6518600B1 (en) * | 2000-11-17 | 2003-02-11 | General Electric Company | Dual encapsulation for an LED |
JP2002252491A (ja) * | 2000-12-21 | 2002-09-06 | Toshiba Corp | シールドケース、その製造方法、及び電子機器 |
US6686649B1 (en) | 2001-05-14 | 2004-02-03 | Amkor Technology, Inc. | Multi-chip semiconductor package with integral shield and antenna |
US8258616B1 (en) * | 2002-01-16 | 2012-09-04 | Marvell International Ltd. | Semiconductor dice having a shielded area created under bond wires connecting pairs of bonding pads |
KR100476925B1 (ko) * | 2002-06-26 | 2005-03-17 | 삼성전자주식회사 | 본딩 불량과 신호 스큐를 방지하는 패드 배치를 갖는 반도체 칩 |
US7164192B2 (en) * | 2003-02-10 | 2007-01-16 | Skyworks Solutions, Inc. | Semiconductor die package with reduced inductance and reduced die attach flow out |
US7002763B2 (en) | 2003-08-08 | 2006-02-21 | International Business Machines Corporation | Identification of laterally positioned servo bands employing differentiating characteristics of servo patterns |
US7030469B2 (en) | 2003-09-25 | 2006-04-18 | Freescale Semiconductor, Inc. | Method of forming a semiconductor package and structure thereof |
US6853055B1 (en) | 2003-11-26 | 2005-02-08 | Actel Corporation | Radiation shielding die carrier package |
JP2007035729A (ja) * | 2005-07-22 | 2007-02-08 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
US7451539B2 (en) | 2005-08-08 | 2008-11-18 | Rf Micro Devices, Inc. | Method of making a conformal electromagnetic interference shield |
US20070257348A1 (en) * | 2006-05-08 | 2007-11-08 | Advanced Semiconductor Engineering, Inc. | Multiple chip package module and method of fabricating the same |
US20080286959A1 (en) * | 2007-05-14 | 2008-11-20 | Texas Instruments Incorporated | Downhill Wire Bonding for QFN L - Lead |
JP2008010636A (ja) * | 2006-06-29 | 2008-01-17 | Rohm Co Ltd | 受光モジュール |
US20080014678A1 (en) | 2006-07-14 | 2008-01-17 | Texas Instruments Incorporated | System and method of attenuating electromagnetic interference with a grounded top film |
US20080170379A1 (en) * | 2007-01-12 | 2008-07-17 | Suresh Basoor | Optical Receiver Having Improved Shielding |
CN101652844B (zh) * | 2007-04-02 | 2015-08-26 | 库利克和索夫工业公司 | 在引线环中形成弯曲的方法 |
US20080310114A1 (en) | 2007-06-18 | 2008-12-18 | Lucent Technologies Inc. | Heat-transfer device for an electromagnetic interference (emi) shield using conductive bristles |
US7902644B2 (en) | 2007-12-07 | 2011-03-08 | Stats Chippac Ltd. | Integrated circuit package system for electromagnetic isolation |
US7786600B2 (en) * | 2008-06-30 | 2010-08-31 | Hynix Semiconductor Inc. | Circuit substrate having circuit wire formed of conductive polarization particles, method of manufacturing the circuit substrate and semiconductor package having the circuit wire |
US8012868B1 (en) | 2008-12-15 | 2011-09-06 | Amkor Technology Inc | Semiconductor device having EMI shielding and method therefor |
US8058715B1 (en) | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US7960818B1 (en) | 2009-03-04 | 2011-06-14 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
JP2011049243A (ja) * | 2009-08-25 | 2011-03-10 | Elpida Memory Inc | 半導体装置 |
US8362598B2 (en) | 2009-08-26 | 2013-01-29 | Amkor Technology Inc | Semiconductor device with electromagnetic interference shielding |
JP2012109455A (ja) * | 2010-11-18 | 2012-06-07 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
JP5796289B2 (ja) * | 2010-11-26 | 2015-10-21 | ソニー株式会社 | 二次電池セル、電池パック及び電力消費機器 |
CN102074517B (zh) * | 2010-12-03 | 2013-01-02 | 日月光封装测试(上海)有限公司 | 球栅阵列封装构造 |
US9627230B2 (en) | 2011-02-28 | 2017-04-18 | Qorvo Us, Inc. | Methods of forming a microshield on standard QFN package |
US9362209B1 (en) | 2012-01-23 | 2016-06-07 | Amkor Technology, Inc. | Shielding technique for semiconductor package including metal lid |
US9153543B1 (en) | 2012-01-23 | 2015-10-06 | Amkor Technology, Inc. | Shielding technique for semiconductor package including metal lid and metalized contact area |
US9179548B2 (en) * | 2012-05-31 | 2015-11-03 | Corning Cable Systems Llc | Controlled-impedance out-of-substrate package structures employing electrical devices, and related assemblies, components, and methods |
JP6059074B2 (ja) * | 2013-04-26 | 2017-01-11 | アオイ電子株式会社 | 半導体装置の製造方法 |
US9736925B2 (en) * | 2014-01-31 | 2017-08-15 | Stmicroelectronics S.R.L. | Packaged semiconductor device having a shielding against electromagnetic interference and manufacturing process thereof |
US9713255B2 (en) * | 2014-02-19 | 2017-07-18 | Intel Corporation | Electro-magnetic interference (EMI) shielding techniques and configurations |
US9568313B2 (en) * | 2014-10-28 | 2017-02-14 | Seiko Epson Corporation | Electronic device, electronic apparatus, and moving object |
US20160379953A1 (en) * | 2015-06-24 | 2016-12-29 | Texas Instruments Incorporated | Semiconductor wire bonding and method |
KR101815754B1 (ko) * | 2016-03-10 | 2018-01-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 |
EP3440698A4 (en) * | 2016-04-01 | 2020-02-12 | INTEL Corporation | SEMICONDUCTOR HOUSING WITH STRUCTURES FOR SHIELDING ELECTROMAGNETIC INTERFERENCES |
JP7036436B2 (ja) * | 2016-05-23 | 2022-03-15 | アダマンド並木精密宝石株式会社 | 光伝搬装置、その光伝搬装置を用いた光表示装置及び照明装置 |
-
2016
- 2016-03-10 KR KR1020160028899A patent/KR101815754B1/ko not_active Application Discontinuation
- 2016-12-03 US US15/368,583 patent/US10141269B2/en active Active
-
2017
- 2017-01-19 TW TW109139733A patent/TWI739662B/zh active
- 2017-01-19 TW TW106101845A patent/TWI713187B/zh active
- 2017-03-06 CN CN201720208944.7U patent/CN206685370U/zh active Active
- 2017-03-06 CN CN201710128412.7A patent/CN107180810B/zh active Active
- 2017-03-06 CN CN202310409668.0A patent/CN116364701A/zh active Pending
-
2018
- 2018-10-18 US US16/164,733 patent/US10943871B2/en active Active
-
2021
- 2021-01-22 US US17/155,397 patent/US11804447B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040166763A1 (en) * | 2002-08-14 | 2004-08-26 | Kenji Hanada | Manufacturing method of solid-state image sensing device |
US20060091523A1 (en) * | 2004-10-29 | 2006-05-04 | Yoshihiko Shimanuki | Semiconductor device and a method for manufacturing of the same |
TWI489610B (zh) * | 2010-01-18 | 2015-06-21 | 矽品精密工業股份有限公司 | 具電磁遮蔽之封裝結構之製法 |
TWI466262B (zh) * | 2012-10-17 | 2014-12-21 | Powertech Technology Inc | 電磁干擾遮蔽層連接至接地訊號之導線架型半導體封裝構造 |
TWM509429U (zh) * | 2013-07-03 | 2015-09-21 | Rosenberger Hochfrequenztech | 具低電磁干擾互連結構的晶粒封裝 |
Also Published As
Publication number | Publication date |
---|---|
US20190051616A1 (en) | 2019-02-14 |
US10943871B2 (en) | 2021-03-09 |
CN107180810B (zh) | 2023-05-02 |
US11804447B2 (en) | 2023-10-31 |
KR20170106548A (ko) | 2017-09-21 |
US20170263568A1 (en) | 2017-09-14 |
CN206685370U (zh) | 2017-11-28 |
KR101815754B1 (ko) | 2018-01-08 |
TWI713187B (zh) | 2020-12-11 |
US20210143105A1 (en) | 2021-05-13 |
US10141269B2 (en) | 2018-11-27 |
CN107180810A (zh) | 2017-09-19 |
TW202111909A (zh) | 2021-03-16 |
CN116364701A (zh) | 2023-06-30 |
TW201803076A (zh) | 2018-01-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI739662B (zh) | 具有增大的附接角度的導電線之半導體裝置及方法 | |
KR100655218B1 (ko) | 다각기둥 형상의 접지 블록을 갖는 3차원 반도체 모듈 | |
US7880290B2 (en) | Flip-chip packages allowing reduced size without electrical shorts and methods of manufacturing the same | |
JP5500870B2 (ja) | 接続端子付き基板及び電子部品のソケット等 | |
US20080119061A1 (en) | Semiconductor chip having bumps of different heights and semiconductor package including the same | |
US11569190B2 (en) | Semiconductor structure and manufacturing method thereof | |
US9818709B2 (en) | Semiconductor device and manufacturing method thereof | |
US7097462B2 (en) | Patch substrate for external connection | |
KR20130089473A (ko) | 반도체 패키지 | |
US9271388B2 (en) | Interposer and package on package structure | |
TWI378546B (en) | Substrate and package for micro bga | |
KR100533763B1 (ko) | 반도체패키지 | |
TWI495052B (zh) | 基板結構與使用該基板結構之半導體封裝件 | |
JPH10233401A (ja) | 半導体装置 | |
US9392696B2 (en) | Semiconductor package | |
US11569155B2 (en) | Substrate bonding pad having a multi-surface trace interface | |
US11670574B2 (en) | Semiconductor device | |
US11189597B2 (en) | Chip on film package | |
WO2016166810A1 (ja) | 撮像モジュール | |
JP2021027079A (ja) | 基板及び電子装置 | |
JP2006196615A (ja) | 半導体素子搭載用基板 |