CN107180810B - 具有增大的附接角度的导电线的半导体装置和方法 - Google Patents

具有增大的附接角度的导电线的半导体装置和方法 Download PDF

Info

Publication number
CN107180810B
CN107180810B CN201710128412.7A CN201710128412A CN107180810B CN 107180810 B CN107180810 B CN 107180810B CN 201710128412 A CN201710128412 A CN 201710128412A CN 107180810 B CN107180810 B CN 107180810B
Authority
CN
China
Prior art keywords
line
substrate
auxiliary
semiconductor die
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710128412.7A
Other languages
English (en)
Other versions
CN107180810A (zh
Inventor
江俊河
山坤书
纳锡河
金真烨
金阳奎
江森河
林德英
洪森门
金森竣
柳森汉
姜坤南
俞雄赫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amkor Technology Inc
Original Assignee
Amkor Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amkor Technology Inc filed Critical Amkor Technology Inc
Priority to CN202310409668.0A priority Critical patent/CN116364701A/zh
Publication of CN107180810A publication Critical patent/CN107180810A/zh
Application granted granted Critical
Publication of CN107180810B publication Critical patent/CN107180810B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4885Wire-like parts or pins
    • H01L21/4889Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48111Disposition the wire connector extending above another semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4845Details of ball bonds
    • H01L2224/48451Shape
    • H01L2224/48453Shape of the interface with the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/4848Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48499Material of the auxiliary connecting means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48996Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/48998Alignment aids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/4917Crossed wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1433Application-specific integrated circuit [ASIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/14335Digital signal processor [DSP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1434Memory
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

具有增大的附接角度的导电线的半导体装置和方法。一种半导体装置包含横跨半导体裸片形成的屏蔽线和支撑所述屏蔽线的辅助线,由此减小封装的大小同时屏蔽从所述半导体裸片产生的电磁干扰。在一个实施例中,所述半导体装置包含:衬底,在其上安装有至少一个电路装置;半导体裸片,其与所述电路装置间隔开且安装到所述衬底上;屏蔽线,其与所述半导体裸片间隔开且横跨所述半导体裸片形成;和辅助线,其在所述屏蔽线下支撑所述屏蔽线且形成为垂直于所述屏蔽线。在另一实施例中,凸块结构用以支撑所述屏蔽线。在又一实施例中,辅助线包含凸块结构部分和线部分,且所述凸块结构部分和所述线部分两者用以支撑所述屏蔽线。

Description

具有增大的附接角度的导电线的半导体装置和方法
技术领域
本发明的某些实施例涉及半导体装置和制作半导体装置的方法。
背景技术
因为制造为具有各种配置的多种半导体装置和用于交换各种信号的电子装置整合到各种电子装置中,所以众所周知半导体装置和电子装置在半导体装置和电子装置的电操作期间发射电磁干扰。
电磁干扰可从按窄间隔安装于主机板上的半导体装置和电子装置发射,且相邻半导体装置可受到电磁干扰的直接或间接影响。
因此,为了部分地屏蔽半导体装置,可使用线或屏蔽层。然而,在这种情况下,使用线或屏蔽层可能增大半导体装置的大小。
发明内容
本发明提供一种半导体装置,其包含横跨半导体裸片形成的屏蔽线和支撑所述屏蔽线的辅助结构,由此减小半导体封装的大小同时屏蔽从所述半导体裸片产生的电磁干扰。
本发明的以上和其它目标将在若干实施例的以下描述中进行阐述或从所述以下描述中显而易见。
根据本发明的实施例的一方面,提供一种半导体装置,其包含:衬底,在其上安装有至少一个电路装置;半导体裸片,其与所述电路装置间隔开且安装到所述衬底上;屏蔽线,其与所述半导体裸片间隔开且横跨所述半导体裸片形成;及辅助结构,其在所述屏蔽线下支撑所述屏蔽线。在一些实施例中,所述辅助结构包括形成为大体上垂直于所述屏蔽线的辅助线。
根据本发明的实施例的另一方面,提供衬底;半导体裸片,其邻近于所述衬底而安装;辅助结构,其连接到所述衬底;及导电线,其在第一端处连接到所述衬底的第一部分,且以物理方式接触所述辅助结构来增大所述导电线连接到所述衬底的角度。根据另一实施例,一种方法包含提供衬底,所述衬底具有连接到所述衬底的表面的半导体裸片。所述方法包含形成耦合到所述衬底的辅助结构和将导电线连接到所述衬底,其中所述导电线以物理方式接触所述辅助结构来增大所述导电线连接到所述衬底的角度。
如上文所描述,根据本发明的实施例,因为所述半导体装置包含与所述半导体裸片间隔开且横跨所述半导体裸片形成的屏蔽线和在所述屏蔽线下支撑所述屏蔽线的辅助结构,所以可减小所述半导体裸片与所述电路装置之间的距离,且可屏蔽从所述半导体裸片产生的电磁干扰,由此减小根据本发明的所述半导体装置的大小。
另外,根据另一实施例,因为所述半导体装置包含电连接所述半导体裸片与所述衬底的导电线和在所述导电线下支撑所述导电线的辅助结构,所以可减小所述半导体装置的大小。
此外,根据另一实施例,所述辅助结构包括邻近于所述导电线设置的凸块结构,以促进具有更陡的倾斜角的所述导电线。在又一实施例中,所述辅助结构包括凸块结构部分和线部分,且所述凸块结构部分和所述线部分两者被用来促进具有甚至更陡的倾斜角的接合线。
附图说明
图1为根据本发明的一实施例的半导体装置的横截面图;
图2为图1中所说明的半导体装置的平面图;
图3A和3B为图2的部分“A”的照片;
图4为根据本发明的另一实施例的半导体装置的平面图;
图5为根据本发明的一实施例的半导体装置的平面图;
图6A为应用根据本发明的一实施例的辅助线的半导体装置的横截面图;
图6B和6C为图6A中所说明的半导体装置的平面图;
图7A为根据本发明的一实施例的辅助线的正视图;
图7B为应用图7A中所说明的辅助线的半导体装置的透视图;
图8A为根据本发明的一实施例的辅助线的正视图;
图8B为应用图8A中所说明的辅助线的半导体装置的透视图;
图9为根据本发明的一实施例的半导体装置的横截面图;
图10为根据本发明的实施例的半导体装置的部分横截面图;
图11为图10的部分“B”的照片;
图12为根据本发明的实施例的半导体装置的部分横截面图;且
图13为图12的部分“C”的照片。
具体实施方式
本申请案主张2016年12月3日申请的第15/368,583号美国专利申请案和2016年3月10日申请的第10-2016-0028899号韩国专利申请案的优先权,所述两个申请案的全部内容在此以引用的方式并入本文中。
在下文中,将参考随附图式详细地描述各种实施例的实例,使得其可由所属领域的技术人员制作并使用。
本发明的各个方面可以许多不同形式体现且不应理解为受限于在本文中所阐述的实例实施例。实际上,提供本发明的这些实例实施例是为了使本发明将为充分且完整的,并且将向所属领域的技术人员传达本发明的各种方面。
在图式中,可为了清楚起见而放大层和区域的厚度。此处,类似参考标号通篇指代类似元件。如本文中所使用,术语“和/或”包含相关联的所列项目中的一或多项的任何和所有组合。另外,应理解,当元件A被称作“连接到”元件B时,元件A可以直接连接到元件B或者可在元件A与元件B之间存在***元件C以使得元件A可间接地连接到元件B。
另外,本文中所使用的术语仅仅是出于描述特定实施例的目的而并不意图限制本发明。如本文中所使用,除非上下文另外明确指示,否则单数形式还意图包含复数形式。将进一步理解,术语包括(comprises/comprising)和/或包含(includes/including)在用于本说明书时规定所陈述特征、数目、步骤、操作、元件和/或组件的存在,但并不排除一或多个其它特征、数目、步骤、操作、元件、组件和/或其群组的存在或添加。
应理解,虽然术语第一、第二等可以在本文中使用来描述各个部件、元件、区域、层和/或区段,但是这些部件、元件、区域、层和/或区段应不受这些术语限制。这些术语仅用于区分一个部件、元件、区域、层和/或区段与另一部件、元件、区域、层和/或区段。因此,举例来说,下文论述的第一部件、第一元件、第一区域、第一层和/或第一区段可被称为第二部件、第二元件、第二区域、第二层和/或第二区段而不脱离本发明的教示。除非另外规定,否则如本文所使用的词语“在……上面”或“在……上”包含所规定元件可以直接或间接物理接触的定向、放置或关系。除非另外规定,否则如本文所使用的词语“与……重叠”包含所指定元件可在相同或不同平面中至少部分或完全重合或对准的定向、放置或关系。应进一步理解,下文中所说明并描述的实施例适当地可具有实施例和/或可在无本文中确切地揭示的任何元件的情况下实践。
图1为根据一个实施例的半导体装置100的横截面图,图2为图1中所说明的半导体装置的平面图,图3A和3B为拍摄图2的部分“A”的照片,且图4为根据另一实施例的半导体装置100的平面图。
参考图1和2,根据一实施例的半导体装置100包含衬底110、半导体裸片120、电路装置130、屏蔽线140或屏蔽线结构140和例如辅助线150的辅助结构。
在一个实施例中,半导体裸片120邻近于衬底110安装或安装于衬底110上。衬底110可为(例如)印刷电路板(PCB),PCB包含绝缘层和形成于绝缘层的表面上和/或绝缘层内的多个电路图案。另外,衬底110可为选自由以下各者组成的群组中的一者:刚性印刷电路板、柔性印刷电路板、陶瓷电路板、内插件和如所属领域的技术人员已知的类似结构。刚性印刷电路板通常包含作为基底材料的酚醛树脂或环氧树脂,且可具有形成于刚性印刷电路板的表面上和/或其内或邻近于刚性印刷电路板的表面和/或其内的多个电路图案。柔性印刷电路板通常包含作为基底材料的聚酰亚胺树脂,且可具有形成于柔性印刷电路板的表面上和/或其内的多个电路图案。陶瓷电路板通常包含作为基底材料的陶瓷,且可具有形成于陶瓷电路板的表面上和/或其内或邻近于陶瓷电路板的表面和/或其内的多个电路图案。内插件可为硅类内插件或介电类内插件。另外,可在本发明的实施例中使用各种种类的衬底,但本发明不特别地限制衬底110的种类。
在一些实施例中,半导体裸片120安装于衬底110上或邻近于衬底110而安装。半导体裸片120可通过导电凸块(未绘示)或如所属领域的技术人员已知的其它连接结构电连接到衬底110。半导体裸片120可通过(例如)大规模回焊工艺、热压缩工艺或激光接合工艺电连接到衬底110的电路图案。半导体裸片120可具有不同类型半导体裸片的的特征。半导体裸片120可包含(例如)处理器裸片、存储器裸片、特殊应用集成电路裸片、通用逻辑裸片、有源半导体组件和如所属领域的技术人员已知的其它电子装置。在一些实施例中,半导体裸片120的导电凸块可包含(例如)导电球(例如焊球)、导电柱(例如铜柱)和/或具有形成于铜柱上的焊料顶盖的导电桩。
在一些实施例中,电路装置130安装于衬底110上或邻近于衬底110而安装,且在半导体裸片120附近或接近于半导体裸片120而定位。电路装置130可为(例如)无源装置、有源装置和/或半导体裸片。电路装置130可包含在半导体裸片120附近形成的多个电路装置。电路装置130可通过(例如)大规模回焊工艺、热压缩工艺或激光接合工艺电连接到衬底110的电路图案。
根据本发明的实施例,屏蔽线140与半导体裸片120间隔开且形成为围绕半导体裸片120。屏蔽线140可经配置以屏蔽从半导体裸片120产生的电磁干扰以免发射到外部,或可防止外部电磁干扰穿透到半导体裸片120中。另外,屏蔽线140用来防止电磁干扰在半导体装置100的半导体裸片120与电路装置130之间发生。因此,屏蔽线140可包含多个屏蔽线且可围绕半导体裸片120。在此处,随着屏蔽线140的数目增大,可提高EMI屏蔽性能。
根据本发明的实施例,屏蔽线140的一端接合到定位在半导体裸片120的一侧处的衬底110,且屏蔽线140的另一或相对端接合到定位在半导体裸片120的另一侧处的衬底110。更确切地说,屏蔽线140与半导体裸片120间隔开且屏蔽线140横跨半导体裸片120形成以便与半导体裸片120重叠。在一些实施例中,屏蔽线140可接合或附接到形成于衬底110上的接合垫111和112。定位在半导体裸片120的一侧处的接合垫可称作第一接合垫111,且定位在半导体裸片120的另一侧处的接合垫可称作第二接合垫112。更确切地说,在一些实施例中,屏蔽线140的一端接合到第一接合垫111,然后屏蔽线140的另一端横跨半导体裸片120接合到第二接合垫112。根据本发明的实施例,屏蔽线140可接合到第二接合垫112,同时与辅助线150成锐利或陡峭角度,此稍后将在描述辅助线150的过程中更详细地加以描述。
第二接合垫112定位于半导体裸片120与电路装置130之间。在一个实施例中,第一接合垫111和第二接合垫112可电连接到衬底110的接地(ground)。因此,接合到第一接合垫111和第二接合垫112的屏蔽线140也可电连接到衬底110的接地。虽然在图2中说明形成为单一单元的第一接合垫111,但是其可由形成为彼此间隔开或侧向地分离的多个单元构成以便分别对应于多个屏蔽线140。同样地,虽然在图2中说明形成为单一单元的第二接合垫112,但是其可由形成为彼此间隔开或侧向地分离的多个单元构成以便分别对应于多个屏蔽线140。然而,因为第一接合垫111和第二接合垫112连接到接地,所以第一接合垫111和第二接合垫112中的每一者更优选地形成为单一单元。屏蔽线140可由金(Au)、银(Ag)、铜(Cu)和/或如所属领域的技术人员已知的其它材料制成。另外,在一些实施例中,可通过另外将绝缘材料涂布于形成屏蔽线140的前述金属上来形成屏蔽线140。因此,可防止屏蔽线140短接到半导体装置100中所设置的元件。在此处,涂布于屏蔽线140上的绝缘材料可由(例如)选自由以下各者组成的群组的一者制成:聚丙烯、聚乙烯、聚酰亚胺、聚碳酸酯和/或其等效物,但本发明的各方面并不限于此。
根据本发明的实施例,辅助线150定位于屏蔽线140下且形成为与屏蔽线140相交。在一些实施例中,辅助线150定位为大体上垂直于屏蔽线140且在第二接合垫112附近形成。更确切地说,辅助线150定位于半导体裸片120与第二接合垫112之间。另外,因为辅助线150形成于多个屏蔽线140中的每一者中,所以辅助线150可排列成线以大体上彼此平行。在一些实施例中,辅助线150具有比屏蔽线140小的宽度且以弓形形成。另外,在其它实施例中,辅助线150的厚度可等于或大于屏蔽线140的厚度。然而,因为辅助线150需要支撑屏蔽线140,所以辅助线150更优选地比屏蔽线140厚。
根据本发明的实施例,辅助线150支撑屏蔽线140且增大屏蔽线140接合到第二接合垫112的角度。更确切地说,如图1中所说明,屏蔽线140的一端接合到第一接合垫111,且屏蔽线140的另一端横跨半导体裸片120接合到第二接合垫112。当无辅助线存在时,屏蔽线140需要接合到图1的虚线结束处的部分。举例来说,当无辅助线存在时,屏蔽线可以约45度的角度接合到第二接合垫。根据本发明的实施例,辅助线150形成于屏蔽线140下,以使得屏蔽线140与辅助线150接触。因此,屏蔽线140接合到第二接合垫112的角度(a)快速地增大或更陡峭地倾斜。根据本发明的实施例,屏蔽线可以大于45度的角度接合或附接到第二接合垫112。根据本发明的实施例,屏蔽线140可以约70度到约90度范围内的角度接合到第二接合垫112。此外,根据本发明的实施例,随着辅助线150以增大的力支撑屏蔽线140,也就是说,随着辅助线150的厚度变得大于屏蔽线140的厚度,屏蔽线140可以约90度的角度接合到第二接合垫112。因此,根据本发明的实施例,可减小半导体裸片120与电路装置130之间的距离,由此减小半导体装置100的大小。举例来说,半导体裸片120与电路装置130之间的距离(t)可为约100微米或更小。另外,辅助线150可由金(Au)、银(Ag)、铜(Cu)和/或如所属领域的技术人员已知的其它材料制成。另外,可通过另外将绝缘材料涂布于形成辅助线150的前述金属上来形成辅助线150。因此,可防止辅助线150短接到半导体装置100中所设置的元件。在此处,涂布于辅助线150上的绝缘材料可由(例如)选自由以下各者组成的群组的一者制成:聚丙烯、聚乙烯、聚酰亚胺、聚碳酸酯和/或如所属领域的技术人员已知的其它材料。
如图4中所说明,辅助线250和其邻近的辅助线可交替地排列。更确切地说,第一组(例如,奇数编号)辅助线250可经排列以接近于半导体裸片120,且第二组(例如,偶数编号)辅助线250可经排列以接近于第二接合垫112。根据本发明的实施例,可更密集地排列屏蔽线140,由此提高半导体裸片120的EMI屏蔽性能。
如上文所描述,根据本发明的实施例的半导体装置100包含与半导体裸片120间隔开且围绕半导体裸片120的屏蔽线140;及在屏蔽线140下支撑屏蔽线140的辅助线150,由此减小半导体裸片120与电路装置130之间的距离同时屏蔽从半导体裸片120产生的电磁干扰。因此,根据本发明的实施例的半导体装置100的大小可相比于相关装置经减小。
图5为根据再一实施例的半导体装置300的平面图。参考图5,在一些实施例中,半导体装置300包含衬底110、半导体裸片120、电路装置130、屏蔽线340和例如辅助线150的辅助结构。图5中所说明的半导体装置300与图2中所说明的半导体装置100大体上相同,且以下描述将集中在半导体装置100与半导体装置300之间的差异。
根据本发明的实施例,屏蔽线340配置与半导体裸片120间隔开且被设置为围绕半导体裸片120。屏蔽线340包含横跨半导体裸片120从半导体裸片120的一侧形成到另一侧的第一屏蔽线341和形成为大体上垂直于第一屏蔽线341的第二屏蔽线342。更确切地说,相比于图2中所说明的半导体装置100,图5中所说明的半导体装置300进一步包含形成为大体上垂直于第一屏蔽线341的第二屏蔽线342,第一屏蔽线341对应于图2中所说明的半导体装置100的屏蔽线140。因此,相比于图2中所说明的半导体装置100,图5中所说明的半导体装置300的半导体裸片120可表明提高的EMI屏蔽性能。根据本发明的实施例,第一屏蔽线341和第二屏蔽线342分别包含多个第一屏蔽线和多个第二屏蔽线。在一些实施例中,当在形成第一屏蔽线341之后形成第二屏蔽线342时,第二屏蔽线342可与第一屏蔽线341接触。另外,第一屏蔽线341和第二屏蔽线342可电连接到衬底110的接地。在一些实施例中,屏蔽线340可鉴于配置而与图2中所说明的屏蔽线140大体上相同,除了其包含第一屏蔽线341和形成为大体上垂直于第一屏蔽线341的第二屏蔽线342以外,且将不重复其详细描述。
图6A为根据再一实施例的应用辅助结构(例如辅助线350)的半导体装置600的横截面图,且图6B和6C为图6A中所说明的半导体装置600的平面图。
参考图6A,辅助线350可包含一或多个辅助线。举例来说,如图6A中所说明,两个辅助线350可支撑一个单一屏蔽线140。因此,辅助线350可相比于使用一个单一辅助线的情况更牢固地支撑屏蔽线140。根据一个实施例,辅助线350可形成为大体上彼此平行,如图6B中所说明。替代地,如图6C中所说明,辅助线350可形成为跨越彼此或彼此重叠。另外,虽然在图6A到6C中说明包含两个辅助线的辅助线350,但是其可包含大于两个辅助线。
图7A为根据一个实施例的辅助结构(例如辅助线450)的正视图,且图7B为应用图7A中所说明的辅助线450的半导体装置700的透视图。
参考图7A和7B,辅助线450包含第一支撑部分451、形成为与第一支撑部分451间隔开的第二支撑部分452,和连接第一支撑部分451与第二支撑部分452且形成为平面的平面部分453。根据本发明的实施例,平面部分453经配置以支撑一或多个屏蔽线140。因此,一或多个屏蔽线140可以平面方式与平面部分453接触。第一支撑部分451可形成为大体上垂直于衬底710,且第二支撑部分452可形成为相对于衬底710倾斜。
图8A为根据另一实施例的辅助线450的正视图,且图8B为应用图8A中所说明的辅助线450的半导体装置800的透视图。
参考图8A和8B,根据本发明的再一实施例的辅助线包含第一辅助线450和第二辅助线460。第一辅助线450与第二辅助线460彼此连接,且形成为彼此对称。在此处,第一辅助线450类似于图7A中所说明的辅助线450。
第一辅助线450包含第一支撑部分451、与第一支撑部分451间隔开的第二支撑部分452,和连接第一支撑部分451与第二支撑部分452且形成为平面的平面部分453。另外,第二辅助线460包含第一支撑部分461、与第一支撑部分461间隔开的第二支撑部分462,和连接第一支撑部分461与第二支撑部分462且形成为平面的平面部分463。第一支撑部分451、461可形成为大体上垂直于衬底810,且第二支撑部分452、462可形成为相对于衬底810倾斜。另外,第一辅助线450与第二辅助线460可彼此耦合,使得第一辅助线450的第二支撑部分452与第二辅助线460的第二支撑部分462彼此连接或接触。另外,第一辅助线450的平面部分453和第二辅助线460的平面部分463中的每一者支撑一或多个屏蔽线140。因此,一或多个屏蔽线140可以平面方式与第一辅助线450的平面部分453和第二辅助线460的平面部分463接触。另外,虽然在图8A和8B中说明彼此相交的两个辅助线450与460,但是可设置两个或两个以上辅助线。更确切地说,辅助线可包含多个辅助线,其可彼此相交且可(例如)排列成线。
图9为根据另一实施例的半导体装置500的横截面图。参考图9,半导体装置500包含衬底510、半导体裸片520、导电线540和例如辅助线550的辅助结构。
在一些实施例中,半导体裸片520安装于衬底510上或邻近于衬底510而安装。举例来说,衬底510可为印刷电路板(PCB),其包含绝缘层和形成于绝缘层的表面上和/或绝缘层内的多个电路图案。另外,衬底510可为选自由以下各者组成的群组中的一者:刚性印刷电路板、柔性印刷电路板、陶瓷电路板、内插件和如所属领域的技术人员已知的其它结构。另外,可在本发明的实施例中使用各种类型的衬底。在本发明的实施例中,多个接合垫511形成于衬底510上或邻近于衬底510而形成。
半导体裸片520安装于衬底510上或邻近于衬底510而安装。在一个实施例中,可使用粘着构件将半导体裸片520安装于衬底510上。半导体裸片520可具有不同类型半导体裸片的的特征。举例来说,半导体裸片520可包含处理器裸片、存储器裸片、特殊应用集成电路裸片、通用逻辑裸片、有源半导体组件和如所属领域的技术人员已知的其它电子装置。另外,多个接合垫521形成于半导体裸片520的顶部表面上或邻近于所述顶部表面而形成。
在本发明的实施例中,导电线540将半导体裸片520电连接到衬底510。更确切地说,导电线540的一端接合到半导体裸片520的接合垫521,且导电线540的另一且相对端接合到衬底510的接合垫511。在此处,导电线540可接合到衬底510的接合垫511,同时与辅助线550成更锐利或陡峭角度,此稍后将在下文中更详细地加以描述。在一些实施例中,导电线540可包含多个导电线。导电线540可由金(Au)、银(Ag)、铜(Cu)和/或如所属领域的技术人员已知的其它材料制成。
根据本发明的实施例,辅助线550定位于导电线540下且形成为与导电线540相交。辅助线550形成为大体上垂直于导电线540且定位于半导体裸片520与衬底510的接合垫511之间。另外,因为辅助线550形成于多个导电线540中的每一者下,所以辅助线550可排列成线以大体上彼此平行。在一些实施例中,辅助线550具有比导电线540小的宽度且以弓形形成。另外,辅助线550的厚度可等于或大于导电线540的厚度。在其它实施例中,辅助线550可比导电线540厚。
根据本发明的实施例,辅助线550支撑导电线540且增大导电线540接合到衬底510的接合垫511的角度。更确切地说,如图9中所说明,导电线540的一端接合到半导体裸片520的接合垫521,然后导电线540的另一端接合到衬底510的接合垫511。当无辅助线存在时,导电线540需要接合到图9的虚线结束处的部分。举例来说,当无辅助线存在时,导电线可以约45度的角度接合到衬底的接合垫。然而在本发明中,辅助线550形成于导电线540下,以使得导电线540与辅助线550接触。因此,更快速或急剧地增大导电线540接合到衬底510的接合垫511的角度(a)。更确切地说,导电线540可以约70度到约90度范围内的角度接合到衬底510的接合垫511。另外,根据本发明的实施例,随着辅助线550以增大的力支撑导电线540,也就是说,随着辅助线550的厚度变得大于导电线540的厚度,导电线540可以约90度的角度接合到衬底510的接合垫511。因此,根据本发明的实施例,可减小将半导体裸片520连接到衬底510的导电线540的宽度,由此减小半导体装置500的大小。辅助线550可由金(Au)、银(Ag)、铜(Cu)和/或如所属领域的技术人员已知的其它材料制成。另外,可通过另外将绝缘材料涂布于形成辅助线550的前述金属上来形成辅助线550。因此,可防止辅助线550短接到半导体装置500中所设置的元件。在此处,涂布于辅助线550上的绝缘材料可由(例如)选自由以下各者组成的群组的一者制成:聚丙烯、聚乙烯、聚酰亚胺、聚碳酸酯和/或如所属领域的技术人员已知的其它材料。
替代地,辅助线550还可形成为具有各种形状,包含(例如)图6A到8B中所说明的形状。
图10说明根据又一实施例的半导体装置900的部分横截面图,且图11为拍摄图10的部分“B”的照片。参考图10,半导体装置900包含衬底110、半导体裸片120、导电线(例如屏蔽线140)和包括凸块结构160的辅助结构。
根据本发明的实施例,凸块结构160邻近于衬底110形成,使得屏蔽线140在屏蔽线140附接到第二接合垫112之处邻接或接近于衬底110而抵靠着凸块结构160定位。在一个优选实施例中,屏蔽线140的一部分直接接触凸块结构160以使得凸块结构160支撑、设置或促进快速增大或相比于相关装置更陡峭倾斜的屏蔽线140接合到第二接合垫112的角度。根据本发明的实施例,屏蔽线140可按大于约50度的角度接合到第二接合垫112。举例来说,当无凸块结构存在时,屏蔽线可以小于约45度的角度接合到第二接合垫。
在一些实施例中,凸块结构160可为在设置屏蔽线140之前形成于第二接合垫112上的凸块球。凸块结构160可由金(Au)、银(Ag)、铜(Cu)和/或如所属领域的技术人员已知的其它材料制成,且可使用(例如)球接合和线尾移除技术形成。在一些实施例中,第二接合垫112具有约100微米的宽度来容纳凸块结构160。应理解,凸块结构160可与在本文中所说明的实施例中的任一者组合使用。举例来说,屏蔽线140可替代地为导电互连线,例如作为图10中所进一步说明的具有在半导体裸片120上附接到接合垫521的一相对端的导电线540。
如上文所描述,根据本发明的实施例的半导体装置900包含与半导体裸片120间隔开的屏蔽线140,且屏蔽线可围绕半导体裸片120,如(例如)图2、4和5中所进一步说明。凸块结构160抵靠着屏蔽线140的一部分而定位,由此减小半导体裸片120与其它电路装置(例如,图1中所说明的电路装置130)之间的距离,同时屏蔽从半导体裸片120产生的电磁干扰。在一个实施例中,此距离可为100微米或更小。因此,可减小根据本发明的实施例的半导体装置900的大小。
图12说明根据又一实施例的半导体装置1000的部分横截面图,且图13为拍摄图12的部分“C”的照片。参考图12,半导体装置1000包含衬底110、半导体裸片120、导电线(例如屏蔽线140)和辅助结构(例如辅助线650),辅助线650具有凸块结构部分260和连接到凸块结构部分260的线部分261。
根据本发明的实施例,辅助线650的凸块结构部分260和线部分261一起支撑屏蔽线140,且增大屏蔽线140接合到第二接合垫112的角度。当无辅助线和凸块结构存在时,屏蔽线可以小于约45度的角度接合到第二接合垫。根据本发明的实施例,辅助线650的线部分261形成于屏蔽线140下,且辅助线650的凸块结构部分260与屏蔽线140的基底形成为邻近第二接合垫112而彼此邻接,以使得屏蔽线140与线部分261和凸块结构部分260两者皆接触。因此,屏蔽线140接合到第二接合垫112的角度快速增大或更陡峭地倾斜。根据本发明的实施例,屏蔽线140可按大于约80度的角度接合到第二接合垫112。在其它实施例中,屏蔽线140可以约70度到约90度的范围内的角度接合到第二接合垫。
此外,根据本发明的实施例,随着辅助线150的线部分261以增大的力支撑屏蔽线140,也就是说,随着辅助线150的线部分261的厚度变得大于屏蔽线140的厚度,屏蔽线140可以约90度的角度接合到第二接合垫112。因此,根据本发明的实施例,可减小半导体裸片120与邻近电路装置(例如,图1中所说明的电路装置130)之间的距离,由此减小半导体装置1000的大小。在一个实施例中,此距离为100微米或更小。
在一些实施例中,辅助线650包含凸块结构部分260,且线部分261可由金(Au)、银(Ag)、铜(Cu)和/或如所属领域的技术人员已知的其它材料制成。另外,在一些实施例中,可通过另外将绝缘材料涂布于形成辅助线650的前述金属上来形成辅助线650。因此,可防止辅助线650短接到半导体装置1000中所设置的元件。在此处,涂布于辅助线650上的绝缘材料可由(例如)选自由以下各者组成的群组的一者制成:聚丙烯、聚乙烯、聚酰亚胺、聚碳酸酯和/或如所属领域的技术人员已知的其它材料。应理解,具有凸块结构部分260和线部分261的辅助线650可与在本文中所说明的实施例中的任一者组合使用。举例来说,屏蔽线140可替代地为导电互连线,例如作为图12中所进一步说明的具有在半导体裸片120上附接到接合垫521的一相对端的导电线540。在一些实施例中,凸块结构260附接到第二接合垫112,且线部分261在一端处连接到凸块结构260且在另一端处连接到第二接合垫112。
在形成本文中所描述的实施例的过程中,已发现优选地在按更陡峭角度形成导电线(例如导电线140、340、540)时使用具有伸展的瓶颈高度的毛细管线接合工具。此外,此将避免在线接合过程期间触摸到线自身或触摸到邻近电路装置。在一个实施例中,已发现大于约450微米的毛细管瓶颈高度相比于约250微米的常规瓶颈高度是优选的。
从所有前述内容中,所属领域的技术人员可确定根据半导体装置的一个实施例,辅助线形成于半导体裸片与第二接合垫之间。在另一实施例中,屏蔽线以约70度到约90度的范围内的角度连接到第二接合垫。在又一实施例中,第二接合垫定位于半导体裸片与电路装置之间。在再一实施例中,其间定位第二接合垫的半导体裸片与电路装置之间的距离小于约100微米。
在另一实施例中,辅助结构包括辅助线;屏蔽线以物理方式接触辅助线;屏蔽线电连接到衬底的接地;辅助线比屏蔽线厚;屏蔽线和辅助线由金属制成;且辅助线进一步包含涂布于金属上的绝缘材料。
在又一实施例中,辅助结构包括一或多个辅助线且以弓形形成;且一或多个辅助线形成为彼此平行或彼此相交。在再一实施例中,辅助结构包含辅助线,其包括垂直于衬底的第一支撑部分;与第一支撑部分间隔开且形成为相对于衬底倾斜的第二支撑部分;和连接第一支撑部分与第二支撑部分且形成为平面的平面部分。
在另一实施例中,平面部分支撑一或多个屏蔽线。在又一实施例中,辅助线包含多个辅助线,且多个辅助线中的第二支撑部分形成为彼此相交。在再一实施例中,辅助结构包括凸块结构。
虽然已参考某些支持性实施例描述根据本发明的各种方面的半导体装置,但是所属领域的技术人员应理解本发明不限于所揭示特定实施例,而是本发明应包含属于所附权利要求书的范围内的所有实施例。

Claims (10)

1.一种半导体装置,其包括:
衬底;
半导体裸片,其安装到所述衬底且包括远离所述衬底的主表面;
屏蔽线,其与所述半导体裸片的所述主表面间隔开且横跨所述半导体裸片的所述主表面形成;以及
辅助结构,其在所述屏蔽线下支撑所述屏蔽线,其中:
所述屏蔽线包括附接到所述衬底的相对端;
所述辅助结构仅沿着所述半导体裸片的一侧附接至所述衬底;
所述辅助结构附接至靠近所述屏蔽线的所述衬底,以增加所述屏蔽线与所述衬底连接的角度;以及
所述辅助结构在从所述屏蔽线的最大高度横向偏移的点处接触所述屏蔽线。
2.根据权利要求1所述的半导体装置,其中:
所述衬底包括安装在所述衬底上的电路装置;
所述半导体裸片与所述电路装置间隔开,以在所述半导体裸片和所述电路装置之间提供空间;
所述空间小于100微米;
所述辅助结构包括辅助线,所述辅助线包括第一端和相对的第二端;
所述辅助线的所述第一端与所述第二端附接到所述空间中的所述衬底;
所述衬底包含在所述空间中的所述半导体裸片的一侧处形成的第一接合垫和在所述半导体裸片的相对侧处形成的第二接合垫;
所述屏蔽线的一端连接到所述第一接合垫,且所述屏蔽线的相对端横跨所述半导体裸片连接到所述第二接合垫;且
所述辅助线形成为垂直于所述屏蔽线。
3.根据权利要求1所述的半导体装置,其中所述屏蔽线包括:
所述角度处于70度到90度的范围中。
4.根据权利要求1所述的半导体装置,其中所述辅助结构包含包括以下各者的辅助线:
凸块结构部分;以及
线部分,其连接到所述凸块结构部分,其中所述屏蔽线以物理方式接触所述凸块结构部分和所述线部分两者。
5.一种半导体装置,其包括:
衬底;
半导体裸片,其邻近于所述衬底安装且包括主表面;
辅助结构,包括具有第一端和相对的第二端的第一辅助线,其中:
所述第一端附接到所述衬底的第一部分;
所述第二端附接到所述衬底的第二部分;
所述第一部分和所述第二部分位于所述半导体裸片的第一侧,且与所述半导体裸片横向间隔开;以及
导电线,其在第一端处沿所述半导体裸片的第一侧连接到所述衬底的第三部分,且以物理方式接触所述辅助结构来增大所述导电线连接到所述衬底的角度,其中:
所述导电线延伸横跨所述半导体裸片的所述主表面并且还包括第二端,所述第二端附接到所述衬底的第四部分,所述第四部分为沿着所述半导体裸片的与所述第一侧不同侧的第二侧;以及
所述第一辅助线在横向偏离所述导电线的最大高度的位置以物理方式接触所述导电线。
6.根据权利要求5所述的半导体装置,其中:
所述第一辅助线包括:
第一支撑部分,包括所述第一端;
第二支撑部分,其与所述第一支撑部分横向间隔开且包括所述第二端;以及
平面部分,其连接所述第一支撑部分与所述第二支撑部分;
所述导电线接触所述平面部分;且
所述角度处于70度到90度的范围中。
7.根据权利要求5所述的半导体装置,其中:
所述第一辅助线包括:
凸块结构部分,位于所述第一端处;以及
线部分,连接至所述凸块结构部分,并且包括附接至所述衬底的所述第二部分的所述第一辅助线的所述第二端;且
所述导电线以物理方式接触所述凸块结构部分和所述线部分两者。
8.根据权利要求5所述的半导体装置,其中:
所述第一端包括凸块结构。
9.一种用于形成半导体装置的方法,其包括:
提供衬底,所述衬底包括耦合到所述衬底的表面的半导体裸片,其中所述半导体裸片包括第一侧和与所述第一侧相对的第二侧;
在所述半导体裸片的所述第一侧处形成耦合到所述衬底的辅助结构;以及
在与所述半导体裸片的所述第二侧相邻的第一位置处,然后在与所述半导体裸片的所述第一侧相邻的第二位置处将导电线连接到所述衬底,其中所述导电线延伸横跨所述半导体裸片,以及其中所述导电线以物理方式接触所述辅助结构来增大所述导电线在所述第二位置处连接的角度,并且其中所述导电线在从所述导电线的最大高度横向偏移的位置处以物理方式接触所述辅助结构。
10.根据权利要求9所述的方法,其中:
形成所述辅助结构包括:
形成与所述衬底连接的凸块结构部分和连接到所述凸块结构部分的线部分;以及
连接所述导电线包括将所述导电线以物理方式接触到所述凸块结构部分和所述线部分。
CN201710128412.7A 2016-03-10 2017-03-06 具有增大的附接角度的导电线的半导体装置和方法 Active CN107180810B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310409668.0A CN116364701A (zh) 2016-03-10 2017-03-06 具有增大的附接角度的导电线的半导体装置和方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020160028899A KR101815754B1 (ko) 2016-03-10 2016-03-10 반도체 디바이스
KR1020160028899 2016-03-10
US15/368,583 US10141269B2 (en) 2016-03-10 2016-12-03 Semiconductor device having conductive wire with increased attachment angle and method
US15/368,583 2016-12-03

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202310409668.0A Division CN116364701A (zh) 2016-03-10 2017-03-06 具有增大的附接角度的导电线的半导体装置和方法

Publications (2)

Publication Number Publication Date
CN107180810A CN107180810A (zh) 2017-09-19
CN107180810B true CN107180810B (zh) 2023-05-02

Family

ID=59787031

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201720208944.7U Active CN206685370U (zh) 2016-03-10 2017-03-06 具有增大的附接角度的导电线的半导体装置
CN202310409668.0A Pending CN116364701A (zh) 2016-03-10 2017-03-06 具有增大的附接角度的导电线的半导体装置和方法
CN201710128412.7A Active CN107180810B (zh) 2016-03-10 2017-03-06 具有增大的附接角度的导电线的半导体装置和方法

Family Applications Before (2)

Application Number Title Priority Date Filing Date
CN201720208944.7U Active CN206685370U (zh) 2016-03-10 2017-03-06 具有增大的附接角度的导电线的半导体装置
CN202310409668.0A Pending CN116364701A (zh) 2016-03-10 2017-03-06 具有增大的附接角度的导电线的半导体装置和方法

Country Status (4)

Country Link
US (3) US10141269B2 (zh)
KR (1) KR101815754B1 (zh)
CN (3) CN206685370U (zh)
TW (2) TWI739662B (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101815754B1 (ko) * 2016-03-10 2018-01-08 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
US11024559B2 (en) * 2016-04-01 2021-06-01 Intel Corporation Semiconductor package with electromagnetic interference shielding structures
US10271421B2 (en) * 2016-09-30 2019-04-23 Avago Technologies International Sales Pte. Limited Systems and methods for providing electromagnetic interference (EMI) shielding between inductors of a radio frequency (RF) module
US10204842B2 (en) * 2017-02-15 2019-02-12 Texas Instruments Incorporated Semiconductor package with a wire bond mesh
DE102017209413A1 (de) * 2017-06-02 2018-12-06 Robert Bosch Gmbh Sensorvorrichtung zum Überwachen zumindest einer Batteriezelle
US20180374798A1 (en) 2017-06-24 2018-12-27 Amkor Technology, Inc. Semiconductor device having emi shielding structure and related methods
JP6950757B2 (ja) * 2018-02-08 2021-10-13 株式会社村田製作所 高周波モジュール
JP7010372B2 (ja) * 2018-06-01 2022-01-26 株式会社村田製作所 高周波モジュール
US20200043864A1 (en) * 2018-08-03 2020-02-06 Murata Manufacturing Co., Ltd. Module
US11227840B2 (en) 2018-08-03 2022-01-18 Murata Manufacturing Co., Ltd. Electronic module having improved shield performance
JP6900947B2 (ja) * 2018-12-28 2021-07-14 株式会社村田製作所 高周波モジュールおよび通信装置
CN114175239A (zh) * 2019-08-01 2022-03-11 株式会社村田制作所 模块
WO2021039325A1 (ja) * 2019-08-23 2021-03-04 株式会社村田製作所 モジュール
CN114521290A (zh) * 2019-09-27 2022-05-20 株式会社村田制作所 模块
CN112992881A (zh) * 2019-12-17 2021-06-18 江苏长电科技股份有限公司 电磁屏蔽封装结构
TWI718838B (zh) * 2020-01-06 2021-02-11 矽品精密工業股份有限公司 電子封裝件及其製法
US11450618B2 (en) 2020-01-17 2022-09-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of compartment shielding using bond wires
TWI767243B (zh) * 2020-05-29 2022-06-11 矽品精密工業股份有限公司 電子封裝件
JP7333120B2 (ja) * 2020-12-21 2023-08-24 株式会社新川 ワイヤ構造及びワイヤ構造形成方法
US11935844B2 (en) * 2020-12-31 2024-03-19 Texas Instruments Incorporated Semiconductor device and method of the same
CN112992707B (zh) * 2021-04-29 2021-08-06 甬矽电子(宁波)股份有限公司 电磁屏蔽结构制作工艺和电磁屏蔽结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294979A (ja) * 1999-04-02 2000-10-20 Sharp Corp 光通信用半導体デバイス
US20080014678A1 (en) * 2006-07-14 2008-01-17 Texas Instruments Incorporated System and method of attenuating electromagnetic interference with a grounded top film
CN102074517A (zh) * 2010-12-03 2011-05-25 日月光封装测试(上海)有限公司 球栅阵列封装构造
CN206685370U (zh) * 2016-03-10 2017-11-28 艾马克科技公司 具有增大的附接角度的导电线的半导体装置

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2796343B2 (ja) * 1989-04-07 1998-09-10 株式会社日立製作所 半導体装置又は半導体集積回路装置及びその製造方法
US5043534A (en) 1990-07-02 1991-08-27 Olin Corporation Metal electronic package having improved resistance to electromagnetic interference
JPH04165655A (ja) * 1990-10-29 1992-06-11 Sanyo Electric Co Ltd 高周波半導体装置
US5557142A (en) 1991-02-04 1996-09-17 Motorola, Inc. Shielded semiconductor device package
US5444303A (en) * 1994-08-10 1995-08-22 Motorola, Inc. Wire bond pad arrangement having improved pad density
US5614694A (en) 1995-03-31 1997-03-25 Motorola, Inc. One piece open and closable metal RF shield
JP3741184B2 (ja) * 1998-07-27 2006-02-01 日本テキサス・インスツルメンツ株式会社 半導体装置
US6538336B1 (en) * 2000-11-14 2003-03-25 Rambus Inc. Wirebond assembly for high-speed integrated circuits
US6518600B1 (en) * 2000-11-17 2003-02-11 General Electric Company Dual encapsulation for an LED
JP2002252491A (ja) * 2000-12-21 2002-09-06 Toshiba Corp シールドケース、その製造方法、及び電子機器
US6686649B1 (en) 2001-05-14 2004-02-03 Amkor Technology, Inc. Multi-chip semiconductor package with integral shield and antenna
US8258616B1 (en) * 2002-01-16 2012-09-04 Marvell International Ltd. Semiconductor dice having a shielded area created under bond wires connecting pairs of bonding pads
KR100476925B1 (ko) * 2002-06-26 2005-03-17 삼성전자주식회사 본딩 불량과 신호 스큐를 방지하는 패드 배치를 갖는 반도체 칩
US7005310B2 (en) * 2002-08-14 2006-02-28 Renesas Technology Corporation Manufacturing method of solid-state image sensing device
US7164192B2 (en) * 2003-02-10 2007-01-16 Skyworks Solutions, Inc. Semiconductor die package with reduced inductance and reduced die attach flow out
US7002763B2 (en) 2003-08-08 2006-02-21 International Business Machines Corporation Identification of laterally positioned servo bands employing differentiating characteristics of servo patterns
US7030469B2 (en) 2003-09-25 2006-04-18 Freescale Semiconductor, Inc. Method of forming a semiconductor package and structure thereof
US6853055B1 (en) 2003-11-26 2005-02-08 Actel Corporation Radiation shielding die carrier package
JP4651359B2 (ja) * 2004-10-29 2011-03-16 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2007035729A (ja) * 2005-07-22 2007-02-08 Matsushita Electric Ind Co Ltd 半導体集積回路装置
US7451539B2 (en) 2005-08-08 2008-11-18 Rf Micro Devices, Inc. Method of making a conformal electromagnetic interference shield
US20070257348A1 (en) * 2006-05-08 2007-11-08 Advanced Semiconductor Engineering, Inc. Multiple chip package module and method of fabricating the same
US20080286959A1 (en) * 2007-05-14 2008-11-20 Texas Instruments Incorporated Downhill Wire Bonding for QFN L - Lead
JP2008010636A (ja) * 2006-06-29 2008-01-17 Rohm Co Ltd 受光モジュール
US20080170379A1 (en) * 2007-01-12 2008-07-17 Suresh Basoor Optical Receiver Having Improved Shielding
CN101652844B (zh) * 2007-04-02 2015-08-26 库利克和索夫工业公司 在引线环中形成弯曲的方法
US20080310114A1 (en) 2007-06-18 2008-12-18 Lucent Technologies Inc. Heat-transfer device for an electromagnetic interference (emi) shield using conductive bristles
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
US7786600B2 (en) * 2008-06-30 2010-08-31 Hynix Semiconductor Inc. Circuit substrate having circuit wire formed of conductive polarization particles, method of manufacturing the circuit substrate and semiconductor package having the circuit wire
US8012868B1 (en) 2008-12-15 2011-09-06 Amkor Technology Inc Semiconductor device having EMI shielding and method therefor
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
JP2011049243A (ja) * 2009-08-25 2011-03-10 Elpida Memory Inc 半導体装置
US8362598B2 (en) 2009-08-26 2013-01-29 Amkor Technology Inc Semiconductor device with electromagnetic interference shielding
TWI489610B (zh) * 2010-01-18 2015-06-21 矽品精密工業股份有限公司 具電磁遮蔽之封裝結構之製法
JP2012109455A (ja) * 2010-11-18 2012-06-07 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
JP5796289B2 (ja) * 2010-11-26 2015-10-21 ソニー株式会社 二次電池セル、電池パック及び電力消費機器
US9627230B2 (en) 2011-02-28 2017-04-18 Qorvo Us, Inc. Methods of forming a microshield on standard QFN package
US9153543B1 (en) 2012-01-23 2015-10-06 Amkor Technology, Inc. Shielding technique for semiconductor package including metal lid and metalized contact area
US9362209B1 (en) 2012-01-23 2016-06-07 Amkor Technology, Inc. Shielding technique for semiconductor package including metal lid
US9179548B2 (en) * 2012-05-31 2015-11-03 Corning Cable Systems Llc Controlled-impedance out-of-substrate package structures employing electrical devices, and related assemblies, components, and methods
TWI466262B (zh) * 2012-10-17 2014-12-21 Powertech Technology Inc 電磁干擾遮蔽層連接至接地訊號之導線架型半導體封裝構造
JP6059074B2 (ja) * 2013-04-26 2017-01-11 アオイ電子株式会社 半導体装置の製造方法
KR101812594B1 (ko) * 2013-07-03 2018-01-30 로젠버거 호흐프리쿠벤츠테흐닉 게엠베하 운트 코. 카게 낮은 전자기 간섭을 갖는 다이 패키지
US9736925B2 (en) * 2014-01-31 2017-08-15 Stmicroelectronics S.R.L. Packaged semiconductor device having a shielding against electromagnetic interference and manufacturing process thereof
US9713255B2 (en) * 2014-02-19 2017-07-18 Intel Corporation Electro-magnetic interference (EMI) shielding techniques and configurations
US9568313B2 (en) * 2014-10-28 2017-02-14 Seiko Epson Corporation Electronic device, electronic apparatus, and moving object
US20160379953A1 (en) * 2015-06-24 2016-12-29 Texas Instruments Incorporated Semiconductor wire bonding and method
US11024559B2 (en) * 2016-04-01 2021-06-01 Intel Corporation Semiconductor package with electromagnetic interference shielding structures
WO2017204041A1 (ja) * 2016-05-23 2017-11-30 アダマンド株式会社 光伝搬装置、その光伝搬装置を用いた光表示装置及び照明装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294979A (ja) * 1999-04-02 2000-10-20 Sharp Corp 光通信用半導体デバイス
US20080014678A1 (en) * 2006-07-14 2008-01-17 Texas Instruments Incorporated System and method of attenuating electromagnetic interference with a grounded top film
CN102074517A (zh) * 2010-12-03 2011-05-25 日月光封装测试(上海)有限公司 球栅阵列封装构造
CN206685370U (zh) * 2016-03-10 2017-11-28 艾马克科技公司 具有增大的附接角度的导电线的半导体装置

Also Published As

Publication number Publication date
US20210143105A1 (en) 2021-05-13
CN206685370U (zh) 2017-11-28
KR101815754B1 (ko) 2018-01-08
TW202111909A (zh) 2021-03-16
US20170263568A1 (en) 2017-09-14
CN107180810A (zh) 2017-09-19
KR20170106548A (ko) 2017-09-21
TWI713187B (zh) 2020-12-11
CN116364701A (zh) 2023-06-30
US10943871B2 (en) 2021-03-09
US10141269B2 (en) 2018-11-27
US20190051616A1 (en) 2019-02-14
US11804447B2 (en) 2023-10-31
TW201803076A (zh) 2018-01-16
TWI739662B (zh) 2021-09-11

Similar Documents

Publication Publication Date Title
CN107180810B (zh) 具有增大的附接角度的导电线的半导体装置和方法
US7880290B2 (en) Flip-chip packages allowing reduced size without electrical shorts and methods of manufacturing the same
US7656031B2 (en) Stackable semiconductor package having metal pin within through hole of package
JP5500870B2 (ja) 接続端子付き基板及び電子部品のソケット等
US20080119061A1 (en) Semiconductor chip having bumps of different heights and semiconductor package including the same
KR20150041029A (ko) Bva 인터포저
US11569190B2 (en) Semiconductor structure and manufacturing method thereof
KR20130089473A (ko) 반도체 패키지
JP2010130004A (ja) 集積回路基板及びマルチチップ集積回路素子パッケージ
US10043725B2 (en) Flip chip ball grid array with low impedence and grounded lid
WO2003034491A2 (en) Semiconductor component
US8674503B2 (en) Circuit board, fabricating method thereof and package structure
US8354744B2 (en) Stacked semiconductor package having reduced height
EP1041618A1 (en) Semiconductor device and manufacturing method thereof, circuit board and electronic equipment
JPH10233401A (ja) 半導体装置
US11569155B2 (en) Substrate bonding pad having a multi-surface trace interface
US20150262957A1 (en) Semiconductor package
EP1235273A2 (en) Semiconductor device formed by mounting semiconductor chip on support substrate, and the support substrate
US7750450B2 (en) Stacked die package with stud spacers
CN118173517A (zh) 具改良接合结构的线路基板
KR19990056765A (ko) 칩 크기 패키지

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant