TWI726370B - 具有縮減臨界尺寸的半導體元件及其製備方法 - Google Patents
具有縮減臨界尺寸的半導體元件及其製備方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 238000000034 method Methods 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 description 17
- 239000000463 material Substances 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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Abstract
本揭露提供一種半導體元件及其製備方法。該半導體元件具有一基層,該基層具有一頂表面以及複數個處理區。一主要圖案配置在該基層的該頂表面上,其中該主要圖案具有一圖案頂表面、位在該圖案頂表面上的複數個處理區,以及一側壁,該主要圖案具有一第一臨界尺寸,該等處理區位在該基底之該頂表面藉由該主要圖案而暴露的該部分上。一次要圖案配置在該主要圖案的該側壁上,其中該次要圖案具有一第二臨界尺寸,該第二臨界尺寸小於該第一臨界尺寸。
Description
本申請案主張2019/06/13申請之美國正式申請案第16/440,354號的優先權及益處,該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體元件及其製備方法。特別是關於一種具有縮減臨界尺寸的半導體元件及其製備方法。
縮減積體電路(ICs)的尺寸係導致改善性能、增加容量及/或降低成本。然而,對IC製造而言,縮減尺寸需要更精密的技術。微影(photolithography)通常被用來圖案化積體電路(ICs),並在一基底上形成一些部件/特徵(features)。為了繼續縮減積體電路(ICs)的規格(scale),在最近幾年中係已針對未來技術世代的發展提出許多技術。如此的製程包括使用一相移遮罩(phase shift mask)、一遞減型光罩(attenuated mask)、一高數值孔徑(high numerical aperture,NA)單色微影工具(monochromatic lithography tool)、一極紫外光(extreme ultraviolet),以及其他等等。
然而,由於例如光學(optics)及光線(light)或是輻射(radiation)波長之參數,微影技術具有一最小間距(minimum pitch),而一
特定顯影技術不能在其下可靠地形成部件/特徵(features)。因此,當多個元件縮減到較小尺寸時,目前的微影製程質疑產生具有所需臨界尺寸(required critical dimensions,CD)的多個圖案。為了避免重新設計目前的顯影工具,則需要新方法來縮減蝕刻進入一基底之IC線路(lines)與通孔(via)的臨界尺寸。
上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體元件。在本揭露的一實施例中,該半導體元件包括一基層,具有一頂表面;一主要圖案,具有一圖案頂表面以及一側壁,並配置在該基層的該頂表面上,其中該主要圖案具有一第一臨界尺寸;複數個處理區,位在該圖案頂表面上,並位在該基層之該頂表面藉由該主要圖案而暴露的一部份上;以及一次要圖案,配置在該主要圖案的該側壁上,其中該次要圖案具有一第二臨界尺寸,且該第二臨界尺寸小於該第一臨界尺寸。
在本揭露之一些實施例中,該基層與該主要圖案包含矽。
在本揭露之一些實施例中,該次要圖案包含二氧化矽。
在本揭露之一些實施例中,該基層包括一矽基底。
在本揭露之一些實施例中,該主要圖案包含多晶矽。
在本揭露之一些實施例中,該等處理區包含離子植入損傷(ion implantation damage)。
本揭露之另一實施例提供一種半導體元件。該半導體元件
包括一基層,具有一頂表面;複數個處理區,位在該頂表面上,其中該等處理區具有一第一臨界尺寸,且每一處理區具有一邊緣;以及一次要圖案,沿著位在該基層之該頂表面上的該等處理區之該等邊緣設置,其中該次要圖案具有一第二臨界尺寸,且該第二臨界尺寸小於該第一臨界尺寸。
本揭露之另一實施例提供一種半導體元件的製備方法。該製備方法的步驟包括形成一基層,該基層具有一頂表面;在該基層的該頂表面上形成一主要圖案,該主要圖案具有一第一臨界尺寸,其中該主要圖案具有一圖案頂表面以及一側壁;在該主要圖案的該圖案頂表面上以及在該基層之該頂表面藉由該主要圖案而暴露的一部分上,形成複數個處理區;以及在該主要圖案的側壁上,形成一次要圖案。
在本揭露之一些實施例中,該半導體元件的製備方法還包括:移除該基層藉由該主要圖案以及該次要圖案而暴露的一部份之步驟。
在本揭露之一些實施例中,該半導體元件的製備方法還包括:移除該主要圖案的步驟。
在本揭露之一些實施例中,該半導體元件的製備方法還包括:移除該基層藉由該次要圖案而暴露之一部分的步驟。
在本揭露之一些實施例中,形成該主要圖案的步驟包括化學氣相沉積(chemical vapor deposition)。
在本揭露之一些實施例中,形成複數個的步驟包括離子植入(ion implantation),其中離子植入係損傷該主要圖案的該圖案頂表面以及該基層之該頂表面藉由該主要圖案而暴露的該部分。
在本揭露之一些實施例中,該基層與該主要圖案包含矽,形成該次要圖案的步驟包括熱氧化(thermal oxidation)。
在本揭露之一些實施例中,該基層包括一矽基底。
在本揭露之一些實施例中,該主要圖案包含多晶矽。
本揭露之另一實施例提供一種半導體元件的製備方法,其藉由該主要圖案而暴露的該圖案頂表面以及該頂表面係進行處理(意即被離子植入所損傷),所以次要圖案係選擇地僅形成在該主要圖案的該側壁上,而不是在該等處理區。因此,次要圖案縮減在該主要圖案之該等部件/特徵(features)之間的間隙(gaps)。意即,主要圖案與次要圖案係結合來形成具有一較小間隙的一新圖案。因此,相較於原始主要圖案,結合半導體元件之圖案的結果具有一較小臨界尺寸。
再者,本揭露的另一實施例係移除該主要圖案,所以僅在該基層留下該次要圖案並取代該主要圖案。該次要圖案可由非顯影技術所形成,也因此具有小於該主要圖案之該第一臨界尺寸的一第二臨界尺寸,其係受限於所使用的顯影技術之限制。
由於次要圖案可由所屬技術領域中所熟知的製程所形成,例如熱氧化,因此本揭露所揭露的製備方法與半導體元件也因此可戲劇性地縮減一圖案的臨界尺寸,而無須新技術或工具,而新的技術或工具會非常昂貴且可能有問題。因此,積體電路(ICs)可以縮減尺寸之部件/特徵(features)製造,而不用大大地增加成本。
上文已相當廣泛地概述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解,可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域
中具有通常知識者亦應瞭解,這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
100:半導體元件
100a:半導體元件
100b:半導體元件
100c:半導體元件
110:主要圖案
112:圖案頂表面
114:側壁
120:次要圖案
122:間隙
130:處理區
132:邊緣
140:基層
140b:部分移除的基層
140c:部分移除的基層
142:頂表面
150:下層
200:製備方法
210:步驟
220:步驟
230:步驟
240:步驟
CD1:第一臨界尺寸
CD2:第二臨界尺寸
參閱實施方式與申請專利範圍合併考量圖式時,可得以更全面了解本申請案之揭示內容,圖式中相同的元件符號係指相同的元件。
圖1為依據本揭露一些實施例的一種半導體元件之剖視示意圖。
圖2為依據本揭露一些實施例的一種半導體元件的製備方法之流程圖。
圖3到圖5為依據本揭露一些實施例的製備一種半導體元件之一流程的剖視示意圖。
圖6到圖8為依據本揭露一些實施例的各半導體元件之剖視示意圖。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式,說明本揭露之實施例,然而本揭露並不受限於該實施例。此外,以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性,然而並非每一實施例必須包含該特定特徵、結構或是特性。再者,重複使用「在實施例中」一語並非必須指相同實施例,然而可為相同實施例。
為了使得本揭露可被完全理解,以下說明提供詳細的步驟與結構。顯然,本揭露的實施不會限制該技藝中的技術人士已知的特定細
節。此外,已知的結構與步驟不再詳述,以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而,除了詳細說明之外,本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容,而是由申請專利範圍定義。
此外,為易於說明,本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
圖1為依據本揭露一些實施例的一種半導體元件之剖視示意圖。請參考圖1,本揭露所提供的半導體元件100具有一基層(base layer)140,基層140具有一頂表面142。基層140在頂表面142上具有許多處理區(processed areas)130。一主要圖案(primary pattern)110配置在基層140的頂表面142上。主要圖案110具有一圖案頂表面112以及一側壁114。許多處理區130形成在主要圖案110的圖案頂表面112上。主要圖案110具有一第一臨界尺寸(first critical dimension)CD1,其係界定在主要圖案110之多個部件/特徵(features)之間的最小距離。
一次要圖案(secondary pattern)120配置在主要圖案110的側壁114上。次要圖案120具有一第二臨界尺寸CD2,其係小於主要圖案110的第一臨界尺寸CD1。次要圖案120配置在主要圖案110的側壁114上,並縮減主要圖案110之部件/特徵(features)之間的該等間隙,導致較小的第
二臨界尺寸CD2。本揭露一些實施例中所提供的半導體100的製備方法係將於後詳細介紹。
圖2為依據本揭露一些實施例的一種半導體元件的製備方法之流程圖。圖3到圖5為依據本揭露一些實施例的製備一種半導體元件之一流程的剖視示意圖。
請參考圖2到圖5,本揭露一些實施例的一種半導體元件的製備方法200之第一步驟210,包括形成具有頂表面142的基層140。在一實施例中,基層140可為配置在一基底(圖未示)上的一多晶矽層或非晶矽層,或者是其他材料的一層,例如一導體層(conductor layer)。更特別地是,基層140可由如噴濺(sputtering)的物理氣相沉積(physical vapor deposition,PVD)製程,或是化學氣相沉積(chemical vapor deposition,CVD)製程所形成。舉例來說,在一實施例中,低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)係被使用來形成基層140。矽烷(silane,SiH4)係被加熱分解,並從矽形成基層140。當溫度低於575℃時,係可沉積非晶矽,同時,當溫度在525℃到575℃之間時,係可獲得多晶矽。在一些其他實施例中,基層140係可為一矽基底本身,其係取決於所應用的產品,其係將於後詳述。
下一步驟220係在基層140的頂表面142上形成具有圖案頂表面112與側壁114的主要圖案110。在一實施例中,主要圖案110的材料可為矽,更特別地是為非晶矽或多晶矽。此步驟係可以傳統顯影技術實施,且主要圖案110的第一臨界尺寸CD1係由所使用的顯影技術所限制。
接下來,在步驟230中,多個處理區130形成在主要圖案110的圖案頂表面112上,以及在基層140之頂表面142藉由主要圖案110而暴
露的該部分上。在本揭露的一實施例中,該等處理區130的形成係包括離子植入(ion implantation)製程。與使用在摻雜之傳統離子植入相比,在本揭露中離子植入的目的係在於損傷前述形成的半導體結構之該等水平表面,即藉由主要圖案110所暴露的圖案頂表面112與頂表面142,以形成該等處理區130,以使接下來次要圖案120的形成可在該等處理區130以外。
接下來,在步驟240中,次要圖案120形成在主要圖案110的該等側壁114上。如前述,係損傷具有所有暴露的水平表面之該等處理區130,以使次要圖案120不能形成在其上。因此,次要圖案120僅形成在主要圖案110的該等側壁114上。在一實施例中,次要圖案120的形成可包括熱氧化,而主要圖案110可包含矽。熱氧化係氧化主要圖案110的側壁114,並形成一二氧化矽層,其係包括次要圖案120;同時,係處利例如藉由主要圖案110而暴露的圖案頂表面112與頂表面142之其他表面,以使沒有二氧化矽形成在其上。前述的離子植入係可被使用在如此的一實施例,以損傷該等處理區130,進而限制主要圖案110之側壁114的氧化。
由於次要圖案120並未藉由顯影技術所形成,因此第二臨界尺寸CD2不會受限於所使用的技術之限制。舉例來說,在前述的實施例中,由於熱氧化對於所屬技術領域中具有通常知識者所熟練的,因此次要圖案120係由熱氧化所形成,以便易於控制主要圖案110之側壁114的氧化層,進而將主要圖案110的第一臨界尺寸CD1縮減到次要圖案120的第二臨界尺寸CD2。因此,係可達到較小的臨界尺寸,而不用應用新的但有可能不完善(faulty)且昂貴的顯影技術。
在一實施例中,基層140為一矽基底,在次要圖案120的線路(lines)之間的該等間隙122形成多個接觸點(contact holes),其係可填滿
有例如鎢的導電材料,以形成插塞(plugs)(圖未示),插塞係連接基層140與接下來形成在主要圖案110與次要圖案120上的其他層。舉例來說,在一實施例中,鎢可沉積在半導體元件100上以及在次要圖案120的該等線路之間的間隙122上。之後,前述形成的結構係可被蝕刻,以從主要圖案110與次要圖案120移除鎢,以便僅餘留在該等接觸孔中的鎢,進而形成該等插塞。形成該等插塞將具有一較小第二臨界尺寸CD2,以取代第一臨界尺寸CD1,其係由所使用的顯應技術所決定。
依據本揭露的另一半導體元件的製備方法,該製備方法還包括移除主要圖案110的步驟。圖6為依據本揭露一些實施例的一半導體元件之剖視示意圖。
請參考圖5及圖6,依據本揭露的半導體元件100a包括具有一頂表面142的一基層140、一次要圖案120,以及多個處理區130。次要圖案120沿著處理區130的邊緣(edge)132配置。圖5中的半導體元件100與圖6中的半導體元件100a之間的差異,係在於移除主要圖案110。由於該等處理區130形成在藉由主要圖案110而暴露的頂表面142上,因此次要圖案120留在存在有主要圖案110之側壁114的位置上,其係為該等處理區130的邊緣132。
在此實施例中,第一臨界尺寸CD1在尺寸上係相等於該等處理區130之間的間隙,其係與形成在前述圖5中之實施例的主要圖案110之該線路寬度相同,且第二臨界尺寸CD2在尺寸上相等於次要圖案120的線路寬度,若是使用如本揭露一實施例中之熱氧化的製程的話,其係可明顯地小於第一臨界尺寸CD1。
在本揭露的一些實施例中,半導體元件100及100a可被使用
來當作半導體元件的一部分,或者是當作一蝕刻製程的一遮罩。舉例來說,在圖6中的半導體元件100,基層140係可為一矽基底,且次要圖案120可被使用當作閘極氧化物(gate oxides),其係通常為氧化矽(silicon oxides)。
當使用半導體元件100與100a當作一遮罩時,請參考圖5及圖7。圖7為依據本揭露一些實施例的一半導體元件100b之剖視示意圖。在此實施例中,半導體元件100b還具有一下層(under layer)150,其係可為在一實施例中例如一鋁層的一導電層,且部分移除的基層140係配置在其上。基層140藉由主要圖案110與次要圖案120所暴露的該部分係被移除,以顯露出其下的導電層150。主要圖案110與次要圖案120可被用來和部分移除的基層140b當做一遮罩。之後,下層150可被蝕刻以形成具有一第二臨界尺寸CD2的一圖案。
在另一實施例中,在次要圖案120的該等線路之間的該等間隙122與部分移除的基層140b的部分之間的間隙,係可形成用於下層150的多個接觸孔。
在一些實施例中,移除基層140的該部分係可包含蝕刻製程。由於次要圖案120與基層140係由不同材所製,所以若是小心地選擇化學蝕刻劑(chemical etchant)的話,濕式蝕刻可被用來將基層140藉由次要圖案120與主要圖案110而暴露的該部分蝕刻掉。
圖8為依據本揭露一些實施例的一半導體元件之剖視示意圖。請參考圖6及圖8,在圖8中的半導體元件100c中,係移除基層140藉由次要圖案120而暴露的該部分,以便僅餘留被次要圖案120所覆蓋的部分移除的基層140c。次要圖案120與部分移除的基層140c可被用來當作用
於進一步圖案化下層150之一蝕刻製程的一遮罩。圖案化下層150可具有第二臨界尺寸CD2的一線寬。
綜上所述,本揭露所提供的半導體元件中,其係包括藉由主要圖案110而暴露的圖案頂表面112與頂表面142,其係被損傷,所以次要圖案120可僅形成在主要圖案110的側壁114上。次要圖案120可縮減主要圖案110的該等線路之間的間隙,或是可藉由移除主要圖案110以形成其本身的一取代圖案。組合的圖案(主要圖案110與次要圖案120的組合,或僅有次要圖案120)具有一第二臨界尺寸CD2,其係小於第一臨界尺寸CD1,其係由用來形成主要圖案110之顯影技術所決定。用來形成次要圖案120的技術,可為所屬技術領域中所熟知的製程,例如熱氧化,以便可以達到較小的第二臨界尺寸CD2,而不需新的及戲劇性地更昂貴以及可能不可靠的顯影技術。然後,係可更節省地達到縮減尺寸之積體電路(ICs)與更多部件/特徵的生產。
本揭露之一實施例提供一種在一半導體元件。在本揭露的一實施例中,該半導體元件包括一基層,具有一頂表面;一主要圖案,具有一圖案頂表面以及一側壁,並配置在該基層的該頂表面上,其中該主要圖案具有一第一臨界尺寸;複數個處理區,位在該圖案頂表面上,並位在該基層之該頂表面藉由該主要圖案而暴露的一部份上;以及一次要圖案,配置在該主要圖案的該側壁上,其中該次要圖案具有一第二臨界尺寸,且該第二臨界尺寸小於該第一臨界尺寸。
在本揭露之另一實施例中提供一種半導體元件。該半導體元件包括一基層,具有一頂表面;複數個處理區,位在該頂表面上,其中該等處理區具有一第一臨界尺寸,且每一處理區具有一邊緣;以及一次要
圖案,沿著位在該基層之該頂表面上的該等處理區之該等邊緣設置,其中該次要圖案具有一第二臨界尺寸,且該第二臨界尺寸小於該第一臨界尺寸。
在本揭露之另一實施例中提供一種半導體元件的製備方法。該製備方法的步驟包括形成一基層,該基層具有一頂表面;在該基層的該頂表面上形成一主要圖案,該主要圖案具有一第一臨界尺寸,其中該主要圖案具有一圖案頂表面以及一側壁;在該主要圖案的該圖案頂表面上以及在該基層之該頂表面藉由該主要圖案而暴露的一部分上,形成複數個處理區;以及在該主要圖案的側壁上,形成一次要圖案。
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。
再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
100:半導體元件
110:主要圖案
112:圖案頂表面
114:側壁
120:次要圖案
122:間隙
130:處理區
140:基層
142:頂表面
CD1:第一臨界尺寸
CD2:第二臨界尺寸
Claims (17)
- 一種半導體元件,包括:一基層,具有一頂表面;一主要圖案,具有一圖案頂表面以及一側壁,並配置在該基層的該頂表面上,其中該主要圖案具有一第一臨界尺寸;複數個處理區,位在該圖案頂表面上,並位在該基層之該頂表面藉由該主要圖案而暴露的一部份上;以及一次要圖案,配置在該主要圖案的該側壁上,其中該次要圖案具有一第二臨界尺寸,且該第二臨界尺寸小於該第一臨界尺寸;其中該等處理區包含離子植入損傷。
- 如請求項1所述之半導體元件,其中該基層與該主要圖案包含矽。
- 如請求項2所述之半導體元件,其中該次要圖案包含二氧化矽。
- 如請求項2所述之半導體元件,其中該基層包括一矽基底。
- 如請求項2所述之半導體元件,其中該主要圖案包含多晶矽。
- 一種半導體元件,包括:一基層,具有一頂表面;複數個處理區,位在該頂表面上,其中該等處理區具有一第一臨 界尺寸,且每一處理區具有一邊緣;以及一次要圖案,沿著位在該基層之該頂表面上的該等處理區之該等邊緣設置,其中該次要圖案具有一第二臨界尺寸,且該第二臨界尺寸小於該第一臨界尺寸;其中該等處理區包含離子植入損傷。
- 如請求項6所述之半導體元件,其中該基層包含矽。
- 如請求項7所述之半導體元件,其中該基層包括一矽基底。
- 如請求項7所述之半導體元件,其中該次要圖案包含二氧化矽。
- 一種半導體元件的製備方法,其步驟包括:形成一基層,該基層具有一頂表面;在該基層的該頂表面上形成一主要圖案,該主要圖案具有一第一臨界尺寸,其中該主要圖案具有一圖案頂表面以及一側壁;在該主要圖案的該圖案頂表面上以及在該基層之該頂表面藉由該主要圖案而暴露的一部分上,形成複數個處理區;在該主要圖案的側壁上,形成一次要圖案;移除該基層藉由該主要圖案以及該次要圖案而暴露的一部份。
- 如請求項10所述之半導體元件的製備方法,還包括移除該主要圖案的步驟。
- 如請求項11所述之半導體元件的製備方法,還包括移除該基層藉由該次要圖案而暴露之一部分的步驟。
- 如請求項10所述之半導體元件的製備方法,其中形成該主要圖案的步驟包括化學氣相沉積。
- 如請求項10所述之半導體元件的製備方法,其中形成複數個處理區的步驟包括離子植入,其中離子植入係損傷該主要圖案的該圖案頂表面以及該基層之該頂表面藉由該主要圖案而暴露的該部分。
- 如請求項10所述之半導體元件的製備方法,其中該基層與該主要圖案包含矽,形成該次要圖案的步驟包括熱氧化。
- 如請求項15所述之半導體元件的製備方法,其中該基層包括一矽基底。
- 如請求項15所述之半導體元件的製備方法,其中該主要圖案包含多晶矽。
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US11355342B2 (en) | 2022-06-07 |
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