TWI693766B - 靜電放電防護裝置 - Google Patents

靜電放電防護裝置 Download PDF

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TWI693766B
TWI693766B TW108101557A TW108101557A TWI693766B TW I693766 B TWI693766 B TW I693766B TW 108101557 A TW108101557 A TW 108101557A TW 108101557 A TW108101557 A TW 108101557A TW I693766 B TWI693766 B TW I693766B
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circuit
coupled
voltage
electrostatic discharge
conductive path
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丁韻仁
賴致瑋
吳易翰
林坤信
許信坤
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力旺電子股份有限公司
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Abstract

一種靜電放電防護裝置。電壓選擇電路自參考電壓與導電路徑上的電壓中選擇具有較高電壓值的電壓提供至電阻電容栓鎖自回授電路，以使電阻電容栓鎖自回授電路在非靜電放電防護模式下栓制電阻電容控制電路的輸入端的電壓，進而斷開傳導靜電流的開關。

Description

靜電放電防護裝置
本發明是有關於一種電子裝置，且特別是有關於一種靜電放電防護裝置。
電子產品於實際使用環境中可能會遭受靜電放電(electrostatic discharge，ESD)的影響而導致損壞。由於靜電放電電壓較一般所提供的電源電壓大出甚多，而當靜電放電發生時，靜電流便很有可能將元件燒毀。因此必須在電路中作一些靜電放電防護措施以有效隔離靜電流，以避免元件損毀。
最常見的作法是在核心電路(Core Circuit)與焊墊(PAD)間，設計一靜電放電防護裝置，以保護其內部電路。在習知的靜電放電防護裝置中，焊墊於靜電放電模式下可做為靜電放電的測試輸入端使用，而在正常模式下做為電源焊墊使用。然而在節省成本、減小電路面積等等的考量下，亦有使焊墊做為輸入輸出焊墊的需求，因此如何能使焊墊可做為電源焊墊以及輸入輸出焊墊使用，而不會使資料信號的傳輸品質受到電路設計的影響為待解決的課題。
本發明提供一種靜電放電防護裝置，可使焊墊在非靜電放電防護模式下做為電源焊墊或輸入輸出焊墊使用，而可具有節省成本、滿足減小電路面積的需求的優點，且不會有資料信號的傳輸品質不佳的問題。
本發明的靜電放電防護裝置包括靜電放電開關電路、電壓選擇電路、電阻電容控制電路以及電阻電容栓鎖自回授電路。靜電放電開關電路耦接於第一導電路徑與第二導電路徑之間，第一導電路徑耦接至焊墊，在靜電放電防護模式下傳導靜電流於第一導電路徑與第二導電路徑之間。電壓選擇電路的輸入端耦接第一導電路徑，自參考電壓與第一導電路徑上的電壓中選擇具有較高電壓值的電壓做為選擇輸出電壓。電阻電容控制電路耦接電壓選擇電路的輸出端、第二導電路徑以及靜電放電開關電路，在靜電放電防護模式下反應第一導電路徑上的靜電放電電流而提供偏壓至靜電放電開關電路的控制端，以導通靜電放電開關電路的放電路徑。電阻電容栓鎖自回授電路耦接電壓選擇電路的輸出端與電阻電容控制電路，在非靜電放電防護模式下依據選擇輸出電壓以及電阻電容控制電路的輸出端提供的回授信號產生控制信號給電阻電容控制電路，以栓制電阻電容控制電路的輸入端的電壓，而斷開靜電放電開關電路的放電路徑。
在本發明的一實施例中，上述的電阻電容栓鎖自回授電路包括開關，其耦接於電壓選擇電路與電阻電容控制電路之間，開關的控制端耦接電阻電容控制電路的輸出端，以接收回授信號。
在本發明的一實施例中，上述的靜電放電開關電路包括NMOS電晶體，開關包括PMOS電晶體。
在本發明的一實施例中，上述的NMOS電晶體的源極端與基底端相耦接。
在本發明的一實施例中，上述的靜電放電開關電路包括PMOS電晶體，開關包括PMOS電晶體。
在本發明的一實施例中，上述的靜電放電開關電路所包括的PMOS電晶體的源極端與基底端相耦接。
在本發明的一實施例中，上述的電壓選擇電路包括第一PMOS電晶體與第二PMOS電晶體。第一PMOS電晶體的源極端耦接參考電壓，第一PMOS電晶體的閘極端耦接第一導電路徑，第一PMOS電晶體的汲極端與基底端相耦接。第二PMOS電晶體的源極端和閘極端分別耦接第一PMOS電晶體的閘極端和源極端，而第二PMOS電晶體的汲極端則與第一PMOS電晶體的汲極端共同耦接至電壓選擇電路的輸出端。
在本發明的一實施例中，上述的電阻電容控制電路包括反相器電路、電阻以及電容。反相器電路的輸入端與輸出端分別耦接電阻電容栓鎖自回授電路的輸出端與輸入端，提供回授信號。電阻的第一端耦接電壓選擇電路的輸出端，電阻的第二端耦接反相器電路的輸入端。電容的第一端耦接電阻的第二端，電容的第二端耦接第二導電路徑。
在本發明的一實施例中，上述的靜電放電防護裝置還包括靜電放電迴避電路，其耦接於第一導電路徑與核心電路之間，並耦接電阻電容控制電路的輸出端，受控於偏壓而於靜電放電防護模式下斷開第一導電路徑與核心電路間的連接。
在本發明的一實施例中，上述的第一導電路徑為系統電壓軌線。
在本發明的一實施例中，上述的第二導電路徑為接地電壓軌線。
基於上述，本發明的實施例藉由電壓選擇電路自參考電壓與第一導電路徑上的電壓中選擇具有較高電壓值的電壓提供至電阻電容栓鎖自回授電路，以使電阻電容栓鎖自回授電路在非靜電放電防護模式下栓制電阻電容控制電路的輸入端的電壓，而斷開靜電放電開關電路，以降低功率損耗並避免信號丟失。因此，可使靜電放電防護裝置的焊墊在非靜電放電防護模式下做為電源焊墊或輸入輸出焊墊使用，而可具有節省成本、滿足減小電路面積的需求的優點，且不會有功率損耗過高以及資料信號的傳輸品質不佳的問題。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下提出多個實施例來說明本發明，然而本發明不僅限於所例示的多個實施例。又實施例之間也允許有適當的結合。在本申請說明書全文(包括申請專利範圍)中所使用的「耦接」一詞可指任何直接或間接的連接手段。舉例而言，若文中描述第一裝置耦接於第二裝置，則應該被解釋成該第一裝置可以直接連接於該第二裝置，或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。此外，「信號」一詞可指至少一電流、電壓、電荷、溫度、資料、電磁波或任何其他一或多個訊號。
圖1是依照本發明一實施例之靜電放電防護裝置的概要示意圖。本實施例之靜電放電防護裝置包括靜電放電開關電路102、電壓選擇電路110、電阻電容栓鎖自回授電路112、以及電阻電容控制電路114，其中靜電放電開關電路102耦接於導電路徑106與導電路徑108之間，導電路徑106、108可例如分別為系統電壓軌線與接地電壓軌線。靜電放電開關電路102用以在靜電放電防護模式下傳導靜電流於導電路徑106與導電路徑108之間，另外電阻電容控制電路114可在靜電放電防護模式下提供偏壓至靜電放電開關電路102的控制端，以導通靜電放電開關電路102進行靜電流的傳導。
本實施例的導電路徑106耦接於焊墊116以及核心電路118之間，焊墊116可例如做為電源焊墊或輸入輸出焊墊使用。此外，電壓選擇電路110耦接導電路徑106、電阻電容栓鎖自回授電路112以及電阻電容控制電路114，電阻電容控制電路114還耦接電阻電容栓鎖自回授電路112、導電路徑108以及靜電放電開關電路102的控制端。電壓選擇電路110的輸入端可接收來自導電路徑106的電壓，並自參考電壓與來自導電路徑106的電壓中選擇具有較高電壓值的電壓做為選擇輸出電壓提供至電阻電容栓鎖自回授電路112以及電阻電容控制電路114，以使電阻電容栓鎖自回授電路112在非靜電放電防護模式下依據選擇輸出電壓以及電阻電容控制電路114的輸出端提供的回授信號SB1產生控制信號給電阻電容控制電路114，以栓制電阻電容控制電路114的輸入端的電壓，進而斷開靜電放電開關電路102的放電路徑。如此一來，可確保靜電放電開關電路102的放電路徑在非靜電放電防護模式下可保持斷開的狀態，不會因焊墊116的輸入輸出信號波動使靜電放電開關電路102產生漏電流，進而影響到資料信號的傳輸品質，並可降低功率損耗。此外將靜電放電防護裝置的焊墊在非靜電放電防護模式下做為電源焊墊或輸入輸出焊墊使用，還可具有節省成本以及減小電路面積等需求等優點。此外，在靜電放電防護模式下，電阻電容控制電路114可直接反應導電路徑106上的靜電放電電流而提供偏壓至靜電放電開關電路102的控制端，以導通靜電放電開關電路102的放電路徑，達到靜電放電保護的目的。
圖2是依照本發明一實施例之靜電放電防護裝置的概要示意圖。詳細來說，靜電放電防護裝置的實施方式可例如圖2所示。靜電放電開關電路102可例如以NMOS電晶體M2來實施，NMOS電晶體M2的基底端與源極端相耦接，且NMOS電晶體M2的基底端與汲極端間形成一寄生二極體D1。電壓選擇電路110可例如包括PMOS電晶體Q1、Q2，其中PMOS電晶體Q1的源極端耦接參考電壓Vr，PMOS電晶體Q1的閘極端耦接導電路徑106，PMOS電晶體的汲極端與基底端相耦接，PMOS電晶體Q2的源極端和閘極端分別耦接PMOS電晶體Q1的閘極端和源極端，而PMOS電晶體Q2的汲極端則與PMOS電晶體Q1的汲極端共同耦接至電壓選擇電路110的輸出端。電阻電容栓鎖自回授電路112可例如包括開關(在本實施例中以PMOS電晶體Q3來實施，然不以此為限)。
電阻電容控制電路114可包括電阻R1、電容C1以及由PMOS電晶體Q4以及NMOS電晶體M1構成的反相器電路。PMOS電晶體Q3耦接於電壓選擇電路110與電阻電容控制電路114的輸入端之間，PMOS電晶體Q3的閘極耦接電阻電容控制電路114的輸出端。電阻R1的第一端耦接電壓選擇電路110的輸出端，電阻R1的第二端耦接電阻電容控制電路114的輸入端，電容C1的第一端耦接電阻R1的第二端，電容C1的第二端耦接導電路徑108。PMOS電晶體Q4以及NMOS電晶體M1耦接於電壓選擇電路110的輸出端與導電路徑108之間，PMOS電晶體Q4以及NMOS電晶體M1的閘極耦接PMOS電晶體Q3的汲極，PMOS電晶體Q4的汲極以及NMOS電晶體M1的汲極耦接電阻電容控制電路114的輸出端，電阻電容控制電路114的輸出端耦接NMOS電晶體M2以及PMOS電晶體Q3的的閘極，而可控制NMOS電晶體M2的導通狀態，並可提供回授信號SB1至PMOS電晶體Q3的的閘極。
當靜電放電防護裝置在靜電放電防護模式時，PMOS電晶體Q1以及焊墊116為浮接狀態，此時若焊墊116出現正脈衝的靜電放電，PMOS電晶體Q1、Q2構成的電壓選擇電路110選擇將導電路徑106上的電壓反應至其輸出端，電壓選擇電路110的輸出端的瞬時電壓將使得電阻R1與電容C1的共同接點的電壓處於低電壓，此低電壓經由電阻電容控制電路114中由PMOS電晶體Q4以及NMOS電晶體M1構成的反相器電路反相後被提供至NMOS電晶體M2，而使NMOS電晶體M2導通，進而將靜電流導引至導電路徑108，以避免損壞核心電路118。此外，在經過一段時間後，電阻R1與電容C1的共同接點的電壓會因正胍衝的靜電對電容C1充電而從低電壓轉為高電壓，此高電壓再經過MOS電晶體Q4以及NMOS電晶體M1構成的反相器電路反相後將被轉為低電壓而導致NMOS電晶體M2進入斷開的狀態。另外，若焊墊116出現負脈衝的靜電放電，靜電流可經由在NMOS電晶體M2的基底端與汲極間的寄生二極體D1被導引流向焊墊116，而可避免損壞核心電路118。
另外，當靜電放電防護裝置在非靜電放電防護模式(例如輸入輸出模式)時，電壓選擇電路110可自參考電壓Vr以及導電路徑106上的電壓中選擇出較高的電壓輸出，也就是說，電壓選擇電路110所輸出的電壓至少等於參考電壓Vr的電壓值。其中當電壓選擇電路110一開始輸出電壓時，電阻R1與電容C1的共同接點上的電壓將由低電壓準位轉為高電壓準位，電阻電容控制電路114的輸出端電壓(亦即NMOS電晶體M2的閘極電壓)則對應地由高電壓準位轉為低電壓準位，而使得NMOS電晶體M2處於關閉的狀態。此外，NMOS電晶體M2的閘極電壓(回授信號SB1)將被回授給PMOS電晶體Q3的閘極，也就是說，PMOS電晶體Q3的閘極電壓將對應地由高電壓準位轉為低電壓準位而進入導通狀態，進而將電壓選擇電路110的輸出端的電壓(其至少等於參考電壓Vr的電壓值)提供給電阻電容栓鎖自回授電路112，如此將使得電阻電容控制電路114的輸入端的電壓被栓制在高電壓準位，進而確保電阻電容控制電路114提供的偏壓使NMOS電晶體M2維持在關閉狀態。由於電壓選擇電路110可自參考電壓Vr以及導電路徑106上的電壓中選擇出較高的電壓提供給電阻電容栓鎖自回授電路112，因此無論焊墊116的輸入輸出信號如何波動，電壓選擇電路110皆可提供足以使NMOS電晶體M2維持在關閉狀態的電壓(至少等於參考電壓Vr的電壓值)給電阻電容栓鎖自回授電路112，如此可避免NMOS電晶體M2導通而影響到焊墊116的輸入輸出信號的傳輸，並可降低功率損耗。
圖3是依照本發明一實施例之靜電放電防護裝置的概要示意圖。本實施例的靜電放電防護裝置與圖2實施例的靜電放電防護裝置的不同之處在於，本實施例的靜電放電防護裝置還包括靜電放電迴避電路302，其耦接於導電路徑106與核心電路118之間，並耦接電阻電容控制電路114的輸出端。靜電放電迴避電路302可受控於電阻電容控制電路114提供的偏壓，以於靜電放電防護模式下斷開導電路徑106與核心電路118間的連接，進一步避免靜電流損壞核心電路118。此靜電放電迴避電路302可例如包括一PMOS電晶體開關，且其閘極接到靜電放電開關電路102的控制端。
圖4是依照本發明一實施例之靜電放電防護裝置的概要示意圖。本實施例的靜電放電防護裝置與圖2實施例的靜電放電防護裝置的不同之處在於，本實施例的電阻電容控制電路114可包括更多個反相器電路。例如圖4所示，電阻電容控制電路114更包括由PMOS電晶體Q5以及NMOS電晶體M3構成的反相器電路，PMOS電晶體Q5以及NMOS電晶體M3構成的反相器電路可用以控制靜電放電開關電路102的放電路徑的導通狀態。需注意的是，在電阻電容控制電路114包括偶數個反相器電路的情形下，靜電放電開關電路102的實施方式也需對應地改變，例如圖4的靜電放電開關電路102為以PMOS電晶體Q6來實施，其控制端耦接PMOS電晶體Q5以及NMOS電晶體M3的共同接點。PMOS電晶體Q6的基底端與源極端相耦接，且PMOS電晶體Q6的基底端與汲極端間形成一寄生二極體D2。寄生二極體D2可用於導引負脈衝的靜電放電，以避免損壞核心電路118。
此外，回授信號SB1仍由PMOS電晶體Q4以及NMOS電晶體M1構成的反相器電路提供，因此電壓選擇電路110、電阻電容栓鎖自回授電路112以及電阻電容控制電路114的作動將類似於上述實施例。另外，本案實施例中由PMOS電晶體Q5以及NMOS電晶體M3構成的反相器電路將使得電阻電容控制電路114提供給靜電放電開關電路102的信號與圖2實施例反相，然本實施例的靜電放電開關電路102已對應此情形改已PMOS電晶體Q6來實施，因此本實施例的電阻電容控制電路114與靜電放電開關電路102間的作動也將類似於上述實施例。因此，本領域具通常知識者應可由上述實施例推知本案靜電放電防護裝置的作動方式，在此不再贅述其作動細節。
圖5是依照本發明一實施例之靜電放電防護裝置的概要示意圖。本實施例的靜電放電防護裝置與圖4實施例的靜電放電防護裝置的不同之處在於，本實施例的靜電放電防護裝置還包括靜電放電迴避電路302。類似地，本實施例靜電放電迴避電路302可受控於電阻電容控制電路114提供的偏壓，而於靜電放電防護模式下斷開導電路徑106與核心電路118間的連接，進一步避免靜電流損壞核心電路118。需注意的是，由於本實施例的電阻電容控制電路114提供給靜電放電開關電路102的信號與圖2實施例反相，因此本實施例的靜電放電迴避電路302可例如改以一NMOS電晶體開關來實施，其閘極耦接到靜電放電開關電路102的控制端。
綜上所述，本發明的實施例藉由電壓選擇電路自參考電壓與導電路徑上的電壓中選擇具有較高電壓值的電壓提供至電阻電容栓鎖自回授電路，以使電阻電容栓鎖自回授電路在非靜電放電防護模式下栓制電阻電容控制電路的輸入端的電壓，而斷開傳導靜電流的開關，以降低功率損耗並避免信號丟失。因此，可使靜電放電防護裝置的焊墊在非靜電放電防護模式下做為電源焊墊或輸入輸出焊墊使用，而可具有節省成本、滿足減小電路面積的需求的優點，且不會有功率損耗過高以及資料信號的傳輸品質不佳的問題。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
102‧‧‧靜電放電開關電路 106、108‧‧‧導電路徑 110‧‧‧電壓選擇電路 112‧‧‧電阻電容栓鎖自回授電路 114‧‧‧電阻電容控制電路 116‧‧‧焊墊 118‧‧‧核心電路 302‧‧‧靜電放電迴避電路 M1~M3‧‧‧NMOS電晶體 Q1~Q6‧‧‧PMOS電晶體 Vr‧‧‧參考電壓 R1‧‧‧電阻 C1‧‧‧電容 D1、D2‧‧‧寄生二極體 SB1‧‧‧回授信號
圖1是依照本發明實施例的一種靜電放電防護裝置的示意圖。 圖2是依照本發明另一實施例的一種靜電放電防護裝置的示意圖。 圖3是依照本發明另一實施例的一種靜電放電防護裝置的示意圖。 圖4是依照本發明另一實施例的一種靜電放電防護裝置的示意圖。 圖5是依照本發明另一實施例的一種靜電放電防護裝置的示意圖。
102‧‧‧靜電放電開關電路
106、108‧‧‧導電路徑
110‧‧‧電壓選擇電路
112‧‧‧電阻電容栓鎖自回授電路
114‧‧‧電阻電容控制電路
116‧‧‧焊墊
118‧‧‧核心電路
SB1‧‧‧回授信號

Claims (10)

  1. 一種靜電放電防護裝置，包括：一靜電放電開關電路，耦接於一第一導電路徑與一第二導電路徑之間，該第一導電路徑耦接至一焊墊，在靜電放電防護模式下傳導靜電流於該第一導電路徑與該第二導電路徑之間；一電壓選擇電路，其輸入端耦接該第一導電路徑，自一參考電壓與該第一導電路徑上的電壓中選擇具有較高電壓值的電壓做為選擇輸出電壓；一電阻電容控制電路，耦接該電壓選擇電路的輸出端、該第二導電路徑以及該靜電放電開關電路，在該靜電放電防護模式下反應該第一導電路徑上的靜電放電電流而提供一偏壓至該靜電放電開關電路的控制端，以導通該靜電放電開關電路的放電路徑；以及一電阻電容栓鎖自回授電路，耦接該電壓選擇電路的輸出端與該電阻電容控制電路，在該非靜電放電防護模式下依據該選擇輸出電壓以及該電阻電容控制電路的輸出端提供的一回授信號產生一控制信號給該電阻電容控制電路，以栓制該電阻電容控制電路的輸入端的電壓，而斷開該靜電放電開關電路的放電路徑，其中該電阻電容控制電路包括：一反相器電路，耦接於該電壓選擇電路的輸出端與該第二導電路徑之間，其中該反相器電路的輸入端與該反相器電路的輸出端還分別耦接該電阻電容栓鎖自回授電路的輸出端與該電阻 電容栓鎖自回授電路的輸入端，以提供該回授信號；一電阻，其第一端耦接該電壓選擇電路的輸出端，該電阻的第二端耦接該反相器電路的輸入端；以及一電容，其第一端耦接該電阻的第二端，該電容的第二端耦接該第二導電路徑。
  2. 如申請專利範圍第1項所述的靜電放電防護裝置，其中該電阻電容栓鎖自回授電路包括：一開關，耦接於該電壓選擇電路與該電阻電容控制電路之間，該開關的控制端耦接該電阻電容控制電路的輸出端，以接收該回授信號。
  3. 如申請專利範圍第2項所述的靜電放電防護裝置，其中該靜電放電開關電路包括一NMOS電晶體，該開關包括一PMOS電晶體。
  4. 如申請專利範圍第3項所述的靜電放電防護裝置，其中該NMOS電晶體的源極端與基底端相耦接。
  5. 如申請專利範圍第2項所述的靜電放電防護裝置，其中該靜電放電開關電路包括一PMOS電晶體，該開關包括一PMOS電晶體。
  6. 如申請專利範圍第5項所述的靜電放電防護裝置，其中靜電放電開關電路所包括的PMOS電晶體的源極端與基底端相耦接。
  7. 如申請專利範圍第1項至第6項中任一項所述的靜電放電防護裝置，其中該電壓選擇電路包括；一第一PMOS電晶體，其源極端耦接該參考電壓，該第一PMOS電晶體的閘極端耦接該第一導電路徑，該第一PMOS電晶體的汲極端與基底端相耦接；以及一第二PMOS電晶體，其源極端和閘極端分別耦接該第一PMOS電晶體的閘極端和源極端，而該第二PMOS電晶體的汲極端則與該第一PMOS電晶體的汲極端共同耦接至該電壓選擇電路的輸出端。
  8. 如申請專利範圍第1項至第6項中任一項所述的靜電放電防護裝置，還包括：一靜電放電迴避電路，耦接於該第一導電路徑與一核心電路之間，並耦接該電阻電容控制電路的輸出端，受控於該偏壓而於該靜電放電防護模式下斷開該第一導電路徑與該核心電路間的連接。
  9. 如申請專利範圍第1項至第6項中任一項所述的靜電放電防護裝置，其中該第一導電路徑為系統電壓軌線。
  10. 如申請專利範圍第1項至第6項中任一項所述的靜電放電防護裝置，其中該第二導電路徑為接地電壓軌線。
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