TWI656811B - Printed wiring board and method of manufacturing same - Google Patents
Printed wiring board and method of manufacturing same Download PDFInfo
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- TWI656811B TWI656811B TW104123066A TW104123066A TWI656811B TW I656811 B TWI656811 B TW I656811B TW 104123066 A TW104123066 A TW 104123066A TW 104123066 A TW104123066 A TW 104123066A TW I656811 B TWI656811 B TW I656811B
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1216—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
Abstract
本發明係提供一種可削減製造步驟中之廢棄物(大量之廢液)之產生、並且縮短製造時間之印刷配線板者。 The present invention provides a printed wiring board which can reduce the generation of waste (a large amount of waste liquid) in a manufacturing process and shorten the manufacturing time.
本發明之印刷配線板100具備：絕緣性基材10；貫通孔11a，其係貫通該絕緣性基材10而形成；第1通孔11，其係向該貫通孔11a中填充第1導電膏1而形成；及第1配線21，其配設於絕緣性基材10上，與第1通孔11連接；且第1配線21具備：第1晶種層21a，其與第1通孔11連接，作為第1配線21之基底膜由第2導電膏2形成；及第1無電解電鍍層21b，其被覆第1晶種層21a。 The printed wiring board 100 of the present invention includes an insulating base material 10, a through hole 11a formed through the insulating base material 10, and a first through hole 11 filled with the first conductive paste into the through hole 11a. 1 is formed; and the first wiring 21 is disposed on the insulating base material 10 and connected to the first through hole 11; and the first wiring 21 includes the first seed layer 21a and the first through hole 11 The connection is made that the base film of the first wiring 21 is formed of the second conductive paste 2, and the first electroless plated layer 21b is covered with the first seed layer 21a.
Description
本發明係關於一種印刷配線板(printed wiring board：PWB)及其製造方法，尤其是關於一種雙面印刷配線板及多層印刷配線板以及其製造方法。 The present invention relates to a printed wiring board (PWB) and a method of manufacturing the same, and more particularly to a double-sided printed wiring board and a multilayer printed wiring board and a method of manufacturing the same.
印刷配線板係利用持續60年以上之長時間、對基板之銅箔進行蝕刻(腐蝕)而進行圖案化之減去(subtractive)法製造，產生出非常多之廢棄物。 The printed wiring board is manufactured by a subtractive method in which the copper foil of the substrate is etched (corroded) for a long period of time of 60 years or more, and a large amount of waste is generated.
又，印刷配線板之電路中之線寬之設計規則根據所搭載之半導體或電容器等零件而有所不同，為自20μm以下之最尖端之製品至0.3mm左右之通用之製品。當然，關於印刷配線板，越是線寬較寬、大型之基板，則顯影步驟、蝕刻步驟及剝離步驟中使用之廢液之量越多，目前，線寬0.1mm以上之製品佔據市場之80%。 Further, the design rule of the line width in the circuit of the printed wiring board differs depending on the components such as the semiconductor or the capacitor to be mounted, and is a general-purpose product of about 0.3 mm from the most advanced product of 20 μm or less. Of course, as for the printed wiring board, the wider the line width and the larger the substrate, the more the amount of waste liquid used in the development step, the etching step, and the stripping step. At present, the product having a line width of 0.1 mm or more occupies the market. %.
又，印刷配線板之製造步驟中之廢棄物不僅經蝕刻之銅之廢液較多，而且用以形成圖案之有機材料之掩膜(抗蝕劑)之顯影液或剝離液亦較多。 Further, the waste in the manufacturing process of the printed wiring board is not only a large amount of waste liquid of copper which is etched, but also a developing solution or a peeling liquid for a mask (resist) for forming an organic material of a pattern.
相對於此，大約20年之前，實施利用全加成法(full-additive process)進行之印刷配線板之量產，但由於利用無電解電鍍形成電路，1小時以1μm 之厚度形成，故而電鍍之生長速度較慢，導致印刷配線板之製造需要20小時以上之時間。 On the other hand, about 20 years ago, the mass production of printed wiring boards by the full-additive process was carried out, but since the circuit was formed by electroless plating, 1 μm was 1 hour. Since the thickness is formed, the growth rate of electroplating is slow, and it takes more than 20 hours to manufacture the printed wiring board.
例如，習知之多層印刷配線板之製造方法係於具有內層電路之內層電路板之表面設置絕緣層，在與內層電路連接之部位設置到達至內層電路之盲孔，向該盲孔中填充導電膏而製成通孔(via hole)，於形成有該通孔之絕緣層之表面形成無電解電鍍層，於其上形成電鍍阻劑(plating resist)，藉由電解電鍍將導體電路之部分堆高，剝離電鍍阻劑，蝕刻去除處於電鍍阻劑下之無電解電鍍而形成(例如，參照專利文獻1)。 For example, the conventional method for manufacturing a multilayer printed wiring board is to provide an insulating layer on the surface of the inner layer circuit board having the inner layer circuit, and to provide a blind hole to the inner layer circuit at a portion connected to the inner layer circuit, to the blind hole Filling a conductive paste to form a via hole, forming an electroless plating layer on the surface of the insulating layer on which the via hole is formed, forming a plating resist thereon, and conducting the conductor circuit by electrolytic plating The portion is piled up, stripped of the plating resist, and etched to remove electroless plating under the plating resist (for example, refer to Patent Document 1).
又，習知之配線基板之製造方法包含如下步驟：於包含熱硬化性樹脂之電絕緣性基材形成通孔之步驟；向上述通孔中填充由導電粒子與熱硬化性樹脂所構成之導電膏之步驟；對上述電絕緣性基材與上述導電膏進行加熱加壓而硬化之熱壓步驟；及形成與上述導電膏電性連接之配線之步驟；且於形成上述配線之步驟中，至少於兩面中之一面形成附著於上述電絕緣性基材並且與上述導電膏內之上述導電粒子結合之電鍍配線(例如，參照專利文獻2)。 Further, a method of manufacturing a conventional wiring board includes the steps of forming a via hole in an electrically insulating substrate including a thermosetting resin, and filling the via hole with a conductive paste composed of conductive particles and a thermosetting resin. a step of heat-pressing the electric insulating substrate and the conductive paste by heating and pressing; and a step of forming a wiring electrically connected to the conductive paste; and in the step of forming the wiring, at least One of the two surfaces is formed with a plating wiring that is bonded to the electrically insulating base material and bonded to the conductive particles in the conductive paste (for example, see Patent Document 2).
[先前技術文獻] [Previous Technical Literature]
[專利文獻] [Patent Literature]
[專利文獻1]日本專利特開2000-244126號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2000-244126
[專利文獻2]日本專利特開2001-308534號公報 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2001-308534
習知之多層印刷配線板之製造方法存在於電鍍阻劑之形成及剝離、以及無電解電鍍之蝕刻去除之各步驟中產生廢液之課題。 The conventional method for producing a multilayer printed wiring board has a problem in that waste liquid is generated in each step of forming and peeling of a plating resist and etching removal by electroless plating.
又，習知之配線基板之製造方法需要如下步驟：於電絕緣性基板之兩側塗佈感光性鈀觸媒之步驟；隔著光罩照射紫外線，將被照射紫外線之部分之感光性鈀觸媒活化之步驟；及將未活化之部分之感光性鈀觸媒去除之步驟；而存在配線基板之製造需要長時間之課題。 Further, a conventional method for manufacturing a wiring board requires the steps of: applying a photosensitive palladium catalyst to both sides of an electrically insulating substrate; and irradiating ultraviolet rays through the mask to irradiate the photosensitive palladium catalyst to be irradiated with ultraviolet rays. The step of activating; and the step of removing the unactivated portion of the photosensitive palladium catalyst; and the problem that the production of the wiring substrate takes a long time.
本發明係為了解決如上述之課題而完成者，其目的在於提供一種不具顯影步驟、蝕刻步驟及剝離步驟，與習知之印刷配線板進行比較可削減製造步驟中之廢棄物(大量之廢液)之產生、並且縮短製造時間之印刷配線板。 The present invention has been made to solve the problems as described above, and an object thereof is to provide a polishing step, an etching step, and a peeling step, which can reduce waste (many waste liquid) in a manufacturing step as compared with a conventional printed wiring board. A printed wiring board that produces and shortens the manufacturing time.
於本發明之印刷配線板中，具備：絕緣性基材；貫通孔，其係貫通該絕緣性基材而形成；第1通孔，其係向該貫通孔中填充導電膏而形成；及第1配線，其配設於絕緣性基材上，與第1通孔連接；且第1配線具備：第1晶種層，其與第1通孔連接，作為第1配線之基底膜由導電膏形成；及第1無電解電鍍層，其被覆第1晶種層，上述第1配線之第1晶種層僅配設於上述第1通孔上之周緣部，上述第1配線之第1無電解電鍍層於上述第1通孔之中心區域與第1通孔接觸。 The printed wiring board of the present invention includes: an insulating base; a through hole formed through the insulating base; and a first through hole formed by filling the through hole with a conductive paste; 1 wiring, which is disposed on an insulating substrate and connected to the first via hole; and the first wiring includes a first seed layer connected to the first via hole, and the conductive film is used as a base film of the first wiring And forming a first electroless plating layer covering the first seed layer, wherein the first seed layer of the first wiring is disposed only on a peripheral portion of the first via hole, and the first wiring is the first one The electrolytic plating layer is in contact with the first through hole in a central region of the first through hole.
發明之印刷配線板與習知之印刷配線板進行比較，發揮可削減製造步驟中之廢液之產生、並且縮短製造時間之效果。 In comparison with a conventional printed wiring board, the printed wiring board of the invention exhibits an effect of reducing the generation of waste liquid in the manufacturing process and shortening the manufacturing time.
1‧‧‧第1導電膏 1‧‧‧1st conductive paste
2‧‧‧第2導電膏 2‧‧‧2nd conductive paste
3‧‧‧第3導電膏 3‧‧‧3rd conductive paste
4‧‧‧第4導電膏 4‧‧‧4th conductive paste
5‧‧‧第5導電膏 5‧‧‧5th conductive paste
10‧‧‧絕緣性基材 10‧‧‧Insulating substrate
10a‧‧‧絕緣層 10a‧‧‧Insulation
11‧‧‧第1通孔 11‧‧‧1st through hole
11a‧‧‧貫通孔 11a‧‧‧through hole
12‧‧‧第2通孔 12‧‧‧2nd through hole
12a‧‧‧開口部 12a‧‧‧ openings
21‧‧‧第1配線 21‧‧‧1st wiring
21a‧‧‧第1晶種層 21a‧‧‧1st seed layer
21b‧‧‧第1無電解電鍍層 21b‧‧‧1st electroless plating
22‧‧‧第2配線 22‧‧‧2nd wiring
22a‧‧‧第2晶種層 22a‧‧‧Second seed layer
22b‧‧‧第2無電解電鍍層 22b‧‧‧2nd electroless plating
23‧‧‧第3配線 23‧‧‧3rd wiring
23a‧‧‧第3晶種層 23a‧‧‧3rd seed layer
23b‧‧‧第3無電解電鍍層 23b‧‧‧3rd electroless plating
100‧‧‧印刷配線板 100‧‧‧Printed wiring board
101‧‧‧雙面印刷配線板 101‧‧‧Double-sided printed wiring board
200‧‧‧印刷配線板 200‧‧‧Printed wiring board
201‧‧‧絕緣性基材 201‧‧‧Insulating substrate
201a‧‧‧銅箔 201a‧‧‧copper foil
202‧‧‧貫通孔 202‧‧‧through holes
203‧‧‧無電解電鍍層 203‧‧‧Electroless plating
204‧‧‧電解電鍍層 204‧‧‧Electroplating
205‧‧‧抗蝕劑 205‧‧‧Resist
206‧‧‧掩膜 206‧‧‧ mask
圖1(a)係表示第1實施形態之印刷配線板之概略構成的一例之立體圖，(b)係表示圖1(a)所示之印刷配線板之沿箭頭方向觀察之A-A'線剖視圖。 Fig. 1(a) is a perspective view showing an example of a schematic configuration of a printed wiring board according to the first embodiment, and Fig. 1(b) is a view showing the line A-A' of the printed wiring board shown in Fig. 1(a) viewed in the direction of the arrow. Cutaway view.
圖2係用以說明第1實施形態之印刷配線板之製造方法的與圖1(b)對應之剖視圖，(a)係表示絕緣性基材之剖視圖，(b)係表示形成有貫通孔之狀態之剖視圖，(c)係表示填充有第1導電膏之狀態之剖視圖，(d)係表示於絕緣性基材之正面形成有第1晶種層之狀態之剖視圖，(e)係表示於絕緣性基材之背面形成有第1晶種層之狀態之剖視圖。 FIG. 2 is a cross-sectional view corresponding to FIG. 1(b) for explaining a method of manufacturing a printed wiring board according to the first embodiment, wherein (a) is a cross-sectional view showing an insulating base material, and (b) is a cross-sectional view showing a through hole. (c) is a cross-sectional view showing a state in which a first conductive paste is filled, (d) is a cross-sectional view showing a state in which a first seed layer is formed on a front surface of an insulating substrate, and (e) is a cross-sectional view showing a state in which a first conductive paste is filled on the front surface of the insulating substrate, A cross-sectional view showing a state in which the first seed layer is formed on the back surface of the insulating base material.
圖3係用以說明習知之印刷配線板之製造方法之剖視圖，(a)係表示絕緣性基材之剖視圖，(b)係表示貫通孔形成步驟之剖視圖，(c)係表示無電解電鍍步驟之剖視圖，(d)係表示電解電鍍步驟之剖視圖，(e)係表示掩膜貼附步驟之剖視圖。 3 is a cross-sectional view for explaining a method of manufacturing a conventional printed wiring board, wherein (a) is a cross-sectional view showing an insulating substrate, (b) is a cross-sectional view showing a through-hole forming step, and (c) is an electroless plating step. In the cross-sectional view, (d) is a cross-sectional view showing an electrolytic plating step, and (e) is a cross-sectional view showing a mask attaching step.
圖4係用以說明圖3所示之習知之印刷配線板之製造方法的後續步驟之剖視圖，(a)係表示雙面曝光步驟之剖視圖，(b)係表示顯影步驟之剖視圖，(c)係表示蝕刻步驟之剖視圖，(d)係表示掩膜剝離步驟之剖視圖。 4 is a cross-sectional view for explaining a subsequent step of the manufacturing method of the conventional printed wiring board shown in FIG. 3, wherein (a) is a cross-sectional view showing a double-sided exposure step, (b) is a cross-sectional view showing a developing step, and (c) A cross-sectional view showing an etching step, and (d) is a cross-sectional view showing a mask peeling step.
圖5(a)係表示第1實施形態之第1通孔附近之另一例之俯視圖，(b)係於圖5(a)所示之第1通孔附近形成有對應之印刷配線板中的第1晶種層之狀態之剖視圖，(c)係於圖5(a)所示之第1通孔附近形成有對應之印刷配線板中的第1無電解電鍍層之狀態之剖視圖。 Fig. 5 (a) is a plan view showing another example of the vicinity of the first through hole in the first embodiment, and Fig. 5 (b) is formed in the vicinity of the first through hole shown in Fig. 5 (a). (c) is a cross-sectional view showing a state in which a first electroless plating layer in the corresponding printed wiring board is formed in the vicinity of the first via hole shown in FIG. 5(a).
圖6係用以說明第2實施形態之印刷配線板之製造方法之剖視圖，(a)係表示絕緣性基材之剖視圖，(b)係表示形成有貫通孔之狀態之剖視圖，(c) 係表示填充有第1導電膏之狀態之剖視圖，(d)係表示於絕緣性基材之雙面形成有第1晶種層之狀態之剖視圖，(e)係表示於第1晶種層上形成有第2無電解電鍍層之狀態之剖視圖。 6 is a cross-sectional view showing a method of manufacturing a printed wiring board according to a second embodiment, wherein (a) is a cross-sectional view showing an insulating substrate, and (b) is a cross-sectional view showing a state in which a through hole is formed, (c) A cross-sectional view showing a state in which a first conductive paste is filled, (d) is a cross-sectional view showing a state in which a first seed layer is formed on both surfaces of an insulating substrate, and (e) is a view on a first seed layer. A cross-sectional view showing a state in which a second electroless plating layer is formed.
圖7係用以說明圖6所示之印刷配線板之製造方法的後續步驟之剖視圖，(a)係表示於絕緣性基材之正面形成有絕緣層之狀態之剖視圖，(b)係表示於絕緣性基材之背面形成有絕緣層之狀態之剖視圖，(c)係表示於絕緣性基材之正面側之開口部中填充有第3導電膏之狀態之剖視圖，(d)係表示於絕緣性基材之背面側之開口部中填充有第3導電膏之狀態之剖視圖。 Figure 7 is a cross-sectional view showing a step subsequent to the method of manufacturing the printed wiring board shown in Figure 6, wherein (a) is a cross-sectional view showing a state in which an insulating layer is formed on the front surface of the insulating substrate, and (b) is a view showing A cross-sectional view showing a state in which an insulating layer is formed on the back surface of the insulating base material, and (c) is a cross-sectional view showing a state in which the third conductive paste is filled in the opening portion on the front side of the insulating base material, and (d) is shown in the insulating layer. A cross-sectional view showing a state in which the third conductive paste is filled in the opening on the back side of the substrate.
圖8係用以說明圖7所示之印刷配線板之製造方法的後續步驟之剖視圖，(a)係表示於絕緣性基材之正面側形成有第2晶種層之狀態之剖視圖，(b)係表示於絕緣性基材之背面側形成有第2晶種層之狀態之剖視圖，(c)係表示於第2晶種層上形成有第2無電解電鍍層之狀態之剖視圖。 8 is a cross-sectional view showing a step subsequent to the method of manufacturing the printed wiring board shown in FIG. 7, and (a) is a cross-sectional view showing a state in which a second seed layer is formed on the front side of the insulating base material, (b) A cross-sectional view showing a state in which a second seed layer is formed on the back surface side of the insulating base material, and (c) is a cross-sectional view showing a state in which the second electroless plating layer is formed on the second seed layer.
圖9(a)係表示第2實施形態之印刷配線板之概略構成的另一例之剖視圖，(b)係表示第3實施形態之印刷配線板之概略構成的另一例之剖視圖。 Fig. 9 (a) is a cross-sectional view showing another example of a schematic configuration of a printed wiring board according to a second embodiment, and Fig. 9 (b) is a cross-sectional view showing another example of a schematic configuration of a printed wiring board according to a third embodiment.
圖10係用以說明第3實施形態之印刷配線板之製造方法之剖視圖，(a)係表示於絕緣性基材之正面側形成有第3晶種層之狀態之剖視圖，(b)係表示於絕緣性基材之背面側形成有第3晶種層之狀態之剖視圖，(c)係表示於第3晶種層及第1無電解電鍍層上形成有第3無電解電鍍層之狀態之剖視圖。 FIG. 10 is a cross-sectional view showing a method of manufacturing the printed wiring board according to the third embodiment, wherein (a) is a cross-sectional view showing a state in which a third seed layer is formed on the front side of the insulating base material, and (b) is a view showing a state in which the third seed layer is formed on the front side of the insulating base material. A cross-sectional view showing a state in which a third seed layer is formed on the back surface side of the insulating base material, and (c) shows a state in which the third electroless plating layer is formed on the third seed layer and the first electroless plated layer. Cutaway view.
(本發明之第1實施形態) (First embodiment of the present invention)
本實施形態之印刷配線板100為雙面印刷配線板(雙面基板)，若大致進行區分，則如圖1所示，具備：絕緣性基材10；貫通孔11a，其係貫通該絕緣性基材10而形成；通孔(以下，稱為第1通孔11)，其係向該貫通孔11a中填充導電膏(以下，稱為第1導電膏1)而形成；及配線(以下，稱為第1配線21)，其配設於絕緣性基材10上，與第1通孔11連接。 The printed wiring board 100 of the present embodiment is a double-sided printed wiring board (double-sided board). When substantially divided, as shown in FIG. 1, the printed wiring board 100 includes an insulating base 10 and a through hole 11a through which the insulation is passed. The base material 10 is formed; a through hole (hereinafter referred to as a first through hole 11) is formed by filling a conductive paste (hereinafter referred to as a first conductive paste 1) into the through hole 11a; and wiring (hereinafter, The first wiring 21 is disposed on the insulating base material 10 and is connected to the first through hole 11 .
又，第1配線21具備：晶種層(以下，稱為第1晶種層21a)，其與第1通孔11連接，作為第1配線21之基底膜(電鍍觸媒層)由導電膏(以下，稱為第2導電膏2)形成；及無電解電鍍層(以下，稱為第1無電解電鍍層21b)，其被覆第1晶種層21a。 In addition, the first wiring 21 includes a seed layer (hereinafter referred to as a first seed layer 21a) which is connected to the first via hole 11 and is used as a base film (electroplating catalyst layer) of the first wiring 21 by a conductive paste. (hereinafter, referred to as a second conductive paste 2); and an electroless plating layer (hereinafter referred to as a first electroless plating layer 21b), which covers the first seed layer 21a.
再者，本實施形態之絕緣性基材10使用以玻璃環氧樹脂為材料之基板，但只要為絕緣材料，則並不限定於玻璃環氧樹脂，例如，亦可為以聚醯亞胺或陶瓷為材料之基板。 Further, in the insulating base material 10 of the present embodiment, a substrate made of a glass epoxy resin is used. However, the insulating material is not limited to the glass epoxy resin, and for example, it may be polyimide or Ceramic is the substrate of the material.
又，本實施形態之第1導電膏1及第2導電膏2使用環氧樹脂作為樹脂成分，亦可為於環氧樹脂中混合丙烯酸酯樹脂、醇酸樹脂、三聚氰胺樹脂或二甲苯樹脂中之1種以上而成者。 Further, in the first conductive paste 1 and the second conductive paste 2 of the present embodiment, an epoxy resin is used as the resin component, and the epoxy resin may be mixed with an acrylate resin, an alkyd resin, a melamine resin or a xylene resin. One or more kinds of adults.
又，關於第1導電膏1及第2導電膏2，作為導電粒子，可為金(Au)、銀(Ag)、銅(Cu)或鎳(Ni)中之1種之金屬粉(例如，僅為銅、僅為銀)、或將2種以上之金屬化合而成之化合物(合金)、或將2種以上之金屬粉混合而成之混合物(例如，銅及銀之混合、銅及銀與除此以外之金屬之調配、銅及銀與焊錫粒子(例如，錫-銀系、錫-鉍系等)之調配)、或將1種金屬 用另一種金屬被覆而成之金屬粉。 In addition, the first conductive paste 1 and the second conductive paste 2 may be metal powder of one of gold (Au), silver (Ag), copper (Cu), or nickel (Ni) as conductive particles (for example, a compound (alloy) in which only two or more metals are combined, or a mixture of two or more kinds of metal powders (for example, a mixture of copper and silver, copper and silver) Mixing with other metals, copper and silver and solder particles (for example, tin-silver, tin-bismuth, etc.), or one metal Metal powder coated with another metal.
尤其是於銅及銀與焊錫粒子之調配之情形時，稱為金屬化膏，於低溫(160℃左右)下與銅箔合金化而表現出穩定之導電性。又，於銅及銀與焊錫粒子之調配之情形時，大部分被合金化，熔點向高溫側(260℃以上)移動，而耐熱可靠性提高。 In particular, when copper and silver are mixed with solder particles, it is called a metallized paste, and alloyed with copper foil at a low temperature (about 160 ° C) to exhibit stable electrical conductivity. Further, in the case of blending copper and silver with solder particles, most of the alloy is alloyed, and the melting point is shifted to the high temperature side (260 ° C or higher), and the heat resistance reliability is improved.
又，第1導電膏1及第2導電膏2亦可使用酚系硬化劑、咪唑系硬化劑、陽離子系硬化劑或自由基系硬化劑等作為硬化劑，亦可添加消泡劑、增黏劑或黏著劑等作為添加劑。 Further, as the first conductive paste 1 and the second conductive paste 2, a phenol-based curing agent, an imidazole-based curing agent, a cationic curing agent, or a radical curing agent may be used as a curing agent, and an antifoaming agent may be added to increase the viscosity. An agent or an adhesive or the like is used as an additive.
再者，於本實施形態中，第1導電膏1及第2導電膏2使用拓自達電線股份有限公司製造之金屬填料(導電粒子與絕緣材料之環氧樹脂等之混合物)，作為第1通孔11之第1導電膏1之導電粒子，使用銅之金屬粉，作為第1晶種層21a之第2導電膏2之導電粒子，使用銀之金屬粉。 In the present embodiment, the first conductive paste 1 and the second conductive paste 2 are made of a metal filler (a mixture of conductive particles and an epoxy resin of an insulating material) manufactured by Tuozta Electric Wire Co., Ltd. as the first The conductive particles of the first conductive paste 1 of the through hole 11 are made of copper metal powder, and the conductive particles of the second conductive paste 2 of the first seed layer 21a are made of silver metal powder.
尤其是關於第1通孔11之第1導電膏1之導電粒子與第1晶種層21a之第2導電膏2之導電粒子，較佳為1種或多種之金屬組成、多種之金屬調配、或金屬組成及金屬調配之組合大致相同。藉此，提高第1導電膏1與第2導電膏2之親和性，第1通孔11及第1晶種層21a間之結合牢固，藉由第1通孔11對第1配線21之增黏功能，可防止第1配線21自絕緣性基材10剝離。 In particular, the conductive particles of the first conductive paste 1 of the first via hole 11 and the conductive particles of the second conductive paste 2 of the first seed layer 21a are preferably one or more metal compositions and a plurality of metal combinations. Or the combination of metal composition and metal blending is about the same. Thereby, the affinity between the first conductive paste 1 and the second conductive paste 2 is improved, and the bonding between the first via hole 11 and the first seed layer 21a is strong, and the first via hole 11 is increased by the first via hole 11. The adhesive function prevents the first wiring 21 from being peeled off from the insulating base material 10.
又，第2導電膏2中之導電粒子之平均粒徑為了使第1晶種層21a為20μm以下之低膜厚，而需要為20μm以下，相對於此，第1導電膏1中之導電粒子之平均粒徑由於第1通孔11之直徑為0.2mm~0.3mm左右，故而無需為20μm以下。 In addition, the average particle diameter of the conductive particles in the second conductive paste 2 is required to be 20 μm or less in order to make the first seed layer 21a a low film thickness of 20 μm or less, whereas the conductive particles in the first conductive paste 1 are opposed to each other. Since the average particle diameter is about 0.2 mm to 0.3 mm in diameter of the first through hole 11, it is not necessary to be 20 μm or less.
即，於本實施形態之印刷配線板100中，第1晶種層21a之第2導電膏2中之導電粒子之平均粒徑小於第1通孔11之第1導電膏1中之導電粒子之平均粒徑亦為特徵。 In the printed wiring board 100 of the present embodiment, the average particle diameter of the conductive particles in the second conductive paste 2 of the first seed layer 21a is smaller than that of the conductive particles in the first conductive paste 1 of the first via hole 11. The average particle size is also characteristic.
又，第1導電膏1若為了向貫通孔11a中填充，而僅為粒徑較大之導電粒子，則導致有鄰接之導電粒子間之間隔較大，第1通孔11之導通狀態不充分之虞。因此，第1導電膏1藉由除粒徑較大之導電粒子以外，使粒徑較小之導電粒子混合存在，可向粒徑較大之導電粒子之間混入粒徑較小之導電粒子，確保第1通孔11之導通狀態，並且亦進行整體之黏度之調整。 In addition, when the first conductive paste 1 is filled with the conductive particles having a large particle diameter in order to fill the through hole 11a, the interval between the adjacent conductive particles is large, and the conduction state of the first through hole 11 is insufficient. After that. Therefore, the first conductive paste 1 mixes conductive particles having a small particle diameter in addition to the conductive particles having a large particle diameter, and can mix conductive particles having a small particle diameter into the conductive particles having a large particle diameter. The conduction state of the first through hole 11 is ensured, and the overall viscosity is also adjusted.
即，於本實施形態之印刷配線板100中，第1通孔11之第1導電膏1中的導電粒子之粒徑之均勻度低於第1晶種層21a之第2導電膏2中的導電粒子之粒徑之均勻度亦為特徵。 In the printed wiring board 100 of the present embodiment, the uniformity of the particle diameter of the conductive particles in the first conductive paste 1 of the first through hole 11 is lower than that in the second conductive paste 2 of the first seed layer 21a. The uniformity of the particle size of the conductive particles is also characteristic.
再者，第1導電膏1及第2導電膏2亦可代替上述之導電性金屬膏，使用例如聚乙炔、聚苯胺、聚吡咯或聚噻吩等導電性聚合物(導電性高分子)。 Further, the first conductive paste 1 and the second conductive paste 2 may be used as a conductive polymer (conductive polymer) such as polyacetylene, polyaniline, polypyrrole or polythiophene instead of the above-mentioned conductive metal paste.
尤其是導電性聚合物為接近作為絕緣性基材10之材料之玻璃環氧樹脂之有機材料，熱性質大致相同、熱膨脹係數近似，故而使用導電性聚合物作為第1導電膏1，藉此，即便於向印刷配線板100安裝零件時產生之高溫下，絕緣性基材10及第1通孔11之伸長係數亦近似，而可抑制由變形導致之印刷配線板100中產生不良情況。 In particular, since the conductive polymer is an organic material which is close to the glass epoxy resin which is a material of the insulating base material 10, the thermal properties are substantially the same and the thermal expansion coefficient is similar. Therefore, a conductive polymer is used as the first conductive paste 1, whereby In other words, at a high temperature which is generated when the components are mounted on the printed wiring board 100, the elongation coefficients of the insulating base material 10 and the first through holes 11 are also approximated, and occurrence of defects in the printed wiring board 100 due to deformation can be suppressed.
又，本實施形態之第1無電解電鍍層21b由無電解鍍銅所構成，於無電解電鍍處理中使用奧野製藥工業股份有限公司製造之獨立電路 基板用無電解鍍銅液「OPC Copper NCA」。 Further, the first electroless plated layer 21b of the present embodiment is composed of electroless copper plating, and an independent circuit manufactured by Okuno Pharmaceutical Co., Ltd. is used in the electroless plating treatment. Electroless copper plating solution "OPC Copper NCA" for substrates.
再者，獨立電路基板用無電解鍍銅液「OPC Copper NCA」每1小時可使鍍銅之膜厚生長6.0μm左右，與習知之無電解鍍銅液進行比較，可明顯地提高無電解電鍍液對銀膏之析出速度。 In addition, the electroless copper plating solution "OPC Copper NCA" for the independent circuit board can increase the thickness of the copper plating to about 6.0 μm per hour, and can significantly improve the electroless plating as compared with the conventional electroless copper plating solution. The rate at which the liquid is deposited on the silver paste.
尤其是作為構成電路之第1配線21需要20μm以上之厚度，藉由使用獨立電路基板用無電解鍍銅液「OPC Copper NCA」，可於3小時以內形成15μm以上之第1無電解電鍍層21b，而為有用。 In particular, the first wiring 21 constituting the circuit needs to have a thickness of 20 μm or more, and the first electroless plating layer 21b of 15 μm or more can be formed within 3 hours by using the electroless copper plating solution "OPC Copper NCA" for the independent circuit board. And useful.
繼而，使用圖2對印刷配線板100之製造方法進行說明。 Next, a method of manufacturing the printed wiring board 100 will be described using FIG.
首先，藉由鑽孔加工、沖孔加工或雷射加工，於絕緣性基材10形成0.2mm~0.3mm左右之貫通孔11a(參照圖2(b)，貫通孔形成步驟)。 First, a through hole 11a of about 0.2 mm to 0.3 mm is formed in the insulating base material 10 by drilling, punching, or laser processing (see FIG. 2(b), a through hole forming step).
然後，使對準絕緣性基材10之正面中之貫通孔11a之形成位置利用乳劑形成有開口之網版印刷版(未圖示)與絕緣性基材10對向地配置，並將導電油墨(第1導電膏1)塗佈於網版印刷版上。 Then, a position of the through hole 11a in the front surface of the insulating substrate 10 is aligned with the insulating substrate 10 by a screen printing plate (not shown) having an opening formed by an emulsion, and the conductive ink is placed. (The first conductive paste 1) is applied onto a screen printing plate.
網版印刷機(未圖示)使刮漿板於網版印刷版之表面滑動，將網版印刷版抵壓至絕緣性基材10，通過網版印刷版之開口噴出導電油墨(第1導電膏1)，而填充至絕緣性基材10之貫通孔11a中。 A screen printing machine (not shown) slides the squeegee on the surface of the screen printing plate, presses the screen printing plate against the insulating substrate 10, and ejects the conductive ink through the opening of the screen printing plate (the first conductive The paste 1) is filled into the through holes 11a of the insulating base material 10.
再者，本實施形態之網版印刷使用對Asada Mesh股份有限公司製造之高強度絲網「HS-D500 Mesh」(目數：500目，線徑：19μm)、利用乳劑形成有開口之網版印刷版。 Further, in the screen printing of the present embodiment, a high-strength screen "HS-D500 Mesh" manufactured by Asada Mesh Co., Ltd. (mesh: 500 mesh, wire diameter: 19 μm) was used, and an open screen was formed using an emulsion. printed version.
然後，使第1導電膏1於100℃~200℃之硬化爐中熱硬化(乾燥)30分鐘~120分鐘後，藉由研磨去除自絕緣性基材10之雙面(正面、背面)突出之硬化物，而形成第1通孔11(參照圖2(c)，第1通孔形成步 驟)。 Then, the first conductive paste 1 is thermally cured (dried) in a curing oven at 100 ° C to 200 ° C for 30 minutes to 120 minutes, and then the both sides (front and back) of the insulating substrate 10 are removed by polishing. The cured material forms a first through hole 11 (refer to FIG. 2(c), the first through hole forming step Step).
然後，使對準絕緣性基材10之正面中之第1配線21(第1晶種層21a)之形成位置利用乳劑形成有開口之網版印刷版(未圖示)與絕緣性基材10對向地配置，並將導電油墨(第2導電膏2)塗佈於網版印刷版上。 Then, a screen printing plate (not shown) in which an opening is formed by aligning the first wiring 21 (first seed layer 21a) in the front surface of the insulating substrate 10 and the insulating substrate 10 is formed. The material is disposed in the opposite direction, and the conductive ink (second conductive paste 2) is applied onto the screen printing plate.
網版印刷機(未圖示)使刮漿板於網版印刷版之表面滑動，將網版印刷版抵壓至絕緣性基材10，通過網版印刷版之開口噴出導電油墨(第2導電膏2)，於絕緣性基材10之正面塗佈成線狀。 A screen printing machine (not shown) slides the squeegee on the surface of the screen printing plate, presses the screen printing plate against the insulating substrate 10, and ejects the conductive ink through the opening of the screen printing plate (second conductive The paste 2) is applied to the front surface of the insulating substrate 10 in a linear shape.
再者，本實施形態之網版印刷使用對Asada Mesh股份有限公司製造之高強度絲網「HS-D500 Mesh」(目數：500目，線徑：19μm)、利用乳劑形成有開口之網版印刷版。關於高強度絲網「HS-D500 Mesh」，有助於圖案形成時之尺寸穩定性之絲網之強度較高，而可形成線寬0.1mm左右之第1晶種層21a。 Further, in the screen printing of the present embodiment, a high-strength screen "HS-D500 Mesh" manufactured by Asada Mesh Co., Ltd. (mesh: 500 mesh, wire diameter: 19 μm) was used, and an open screen was formed using an emulsion. printed version. Regarding the high-strength screen "HS-D500 Mesh", the strength of the screen which contributes to dimensional stability at the time of pattern formation is high, and the first seed layer 21a having a line width of about 0.1 mm can be formed.
然後，使第2導電膏2於100℃~200℃之硬化爐中熱硬化(乾燥)30分鐘~120分鐘，形成作為第1配線21之基底膜之第1晶種層21a(參照圖2(d)，第1晶種層形成步驟)。 Then, the second conductive paste 2 is thermally cured (dried) in a curing oven at 100 ° C to 200 ° C for 30 minutes to 120 minutes to form a first seed layer 21 a as a base film of the first wiring 21 (see FIG. 2 (see FIG. 2 ). d), the first seed layer forming step).
再者，第1晶種層形成步驟係於絕緣性基材10之正面側形成有第1晶種層21a之後，將絕緣性基材10翻過來，藉由與絕緣性基材10之正面側相同之製造步驟，於絕緣性基材10之背面側形成第1晶種層21a(參照圖2(e))。 In addition, in the first seed layer forming step, after the first seed layer 21a is formed on the front side of the insulating base material 10, the insulating base material 10 is turned over, and the front side of the insulating base material 10 is formed. In the same manufacturing step, the first seed layer 21a is formed on the back side of the insulating base material 10 (see FIG. 2(e)).
然後，例如，藉由包含脫脂步驟、預浸步驟、鈀(Pd)置換處理步驟、鈀殘渣去除步驟及無電解鍍銅步驟之無電解電鍍處理，使第1 無電解電鍍層21b於第1晶種層21a上生長(參照圖1(b)，第1無電解電鍍層形成步驟)。 Then, for example, the first step is performed by an electroless plating treatment including a degreasing step, a prepreg step, a palladium (Pd) replacement treatment step, a palladium residue removal step, and an electroless copper plating step. The electroless plating layer 21b is grown on the first seed layer 21a (see FIG. 1(b), the first electroless plating layer forming step).
再者，本實施形態之脫脂步驟使用奧野製藥工業股份有限公司製造之藥液「OIC Cleaner」，於25℃之藥液中浸漬3分鐘，將絕緣性基材10之雙面(正面、背面)洗淨。 In addition, the degreasing step of the present embodiment is immersed in a chemical solution of 25 ° C for 3 minutes using a chemical liquid "OIC Cleaner" manufactured by Okuno Pharmaceutical Co., Ltd., and the both sides (front and back) of the insulating base material 10 are used. Wash.
又，本實施形態之預浸步驟使用奧野製藥工業股份有限公司製造之藥液「OIC Pre-dip」，於25℃之藥液中浸漬30秒鐘，提高絕緣性基材10(第1晶種層21a)與鈀之親和性。 In the prepreg step of the present embodiment, the chemical liquid "OIC Pre-dip" manufactured by Okuno Pharmaceutical Co., Ltd. is used, and immersed in a chemical solution at 25 ° C for 30 seconds to improve the insulating substrate 10 (the first seed crystal). The affinity of layer 21a) to palladium.
又，本實施形態之鈀置換處理步驟使用奧野製藥工業股份有限公司製造之藥液「OIC Accele」，於25℃之藥液中浸漬3分鐘，使鈀吸附於絕緣性基材10上。 In the palladium replacement treatment step of the present embodiment, the chemical liquid "OIC Accele" manufactured by Okuno Pharmaceutical Co., Ltd. was used, and immersed in a chemical solution at 25 ° C for 3 minutes to adsorb palladium on the insulating base material 10.
進而，本實施形態之鈀殘渣去除步驟使用奧野製藥工業股份有限公司製造之藥液「OIC Post-dip」，於25℃之藥液中浸漬1分鐘，自絕緣性基材10上之第1晶種層21a以外之基底將鈀去除。 Further, the palladium residue removal step of the present embodiment is immersed in a chemical solution of 25 ° C for 1 minute using a chemical liquid "OIC Post-dip" manufactured by Okuno Pharmaceutical Co., Ltd., and the first crystal from the insulating substrate 10 is used. The substrate other than the seed layer 21a removes palladium.
又，本實施形態之無電解鍍銅步驟使用奧野製藥工業股份有限公司製造之藥液「OPC Copper NCA(高速型)」，於55℃之藥液中浸漬180分鐘，利用由添加至電鍍液中之還原劑引起之銅離子之還原反應，使吸附於第1晶種層21a表面之鈀觸媒粒子上析出銅(第1無電解電鍍層21b)，而形成第1配線21。 In addition, the electroless copper plating step of the present embodiment is immersed in a chemical solution of 55 ° C for 180 minutes using a chemical liquid "OPC Copper NCA (High Speed Type)" manufactured by Okuno Pharmaceutical Co., Ltd., and is added to the plating solution by use. The reduction reaction of the copper ions by the reducing agent causes copper (the first electroless plating layer 21b) to be deposited on the palladium catalyst particles adsorbed on the surface of the first seed layer 21a to form the first wiring 21.
然後，為了形成連接於第1配線21之電極(未圖示)，而於絕緣性基材10(第1配線21)上之除電極之形成位置以外之區域形成抗蝕劑之掩膜，以第1配線21之第1無電解電鍍層21b為基底膜，實施無電解 鍍鎳/鍍金，而形成無電解鍍鎳/鍍金層(電極)。 Then, in order to form an electrode (not shown) connected to the first wiring 21, a mask of a resist is formed on a region other than the position at which the electrode is formed on the insulating base material 10 (the first wiring 21). The first electroless plating layer 21b of the first wiring 21 is a base film, and is subjected to electroless plating. Nickel plating/gold plating to form an electroless nickel/gold plating layer (electrode).
經過以上之步驟，完成本實施形態之印刷配線板100。 Through the above steps, the printed wiring board 100 of the present embodiment is completed.
此處，使用減去法之習知之印刷配線板200使用於絕緣性基材201之雙面(正面、背面)之整面貼附有銅箔201a之基材(參照圖3(a))，利用圖3及圖4所示之已知之製造步驟形成。再者，於圖3及圖4中，符號202為貫通孔，符號203為無電解電鍍層，符號204為電解電鍍層，符號205為抗蝕劑，符號206為掩膜。 Here, the conventional printed wiring board 200 using the subtractive method is used for the base material on which the copper foil 201a is attached to the entire surface (front surface and back surface) of the insulating base material 201 (see FIG. 3(a)). It is formed using the known manufacturing steps shown in FIGS. 3 and 4. Further, in FIGS. 3 and 4, reference numeral 202 is a through hole, reference numeral 203 is an electroless plating layer, reference numeral 204 is an electrolytic plating layer, reference numeral 205 is a resist, and reference numeral 206 is a mask.
關於習知之印刷配線板200之製造方法，例如，無電解電鍍步驟(圖3(c))之處理時間為40分鐘，電解電鍍步驟(圖3(d))之處理時間為60分鐘，掩膜貼附步驟(圖3(e))之處理時間為20分鐘，曝光(雙面)步驟(圖4(a))之處理時間為30分鐘，顯影步驟(圖4(b))之處理時間為10分鐘，蝕刻步驟(圖4(c))之處理時間為10分鐘，掩膜剝離步驟(圖4(d))之處理時間為10分鐘。 Regarding the manufacturing method of the conventional printed wiring board 200, for example, the processing time of the electroless plating step (Fig. 3 (c)) is 40 minutes, and the processing time of the electrolytic plating step (Fig. 3 (d)) is 60 minutes, mask The processing time of the attaching step (Fig. 3(e)) is 20 minutes, the processing time of the exposure (double-sided) step (Fig. 4(a)) is 30 minutes, and the processing time of the developing step (Fig. 4(b)) is The treatment time of the etching step (Fig. 4 (c)) was 10 minutes for 10 minutes, and the treatment time for the mask peeling step (Fig. 4 (d)) was 10 minutes.
即，習知之印刷配線板200之製造方法之製造時間(貫通孔形成步驟(圖3(b))除外)為180分鐘，存在顯影步驟、蝕刻步驟及掩膜去除步驟，而導致產生廢液。 That is, the manufacturing time of the manufacturing method of the conventional printed wiring board 200 (excluding the through hole forming step (Fig. 3(b))) is 180 minutes, and there are a developing step, an etching step, and a mask removing step, resulting in generation of waste liquid.
相對於此，關於本實施形態之印刷配線板100之製造方法，印刷第1導電膏1向貫通孔11a中填充、使第1導電膏1乾燥而形成第1通孔11之第1通孔形成步驟(塞孔印刷、乾燥，圖2(c))之處理時間為30分鐘。又，於絕緣性基材10之正面印刷第2導電膏2使其乾燥而形成第1晶種層21a之第1晶種層(正)形成步驟(晶種層(正)印刷、乾燥，圖2(d))之處理時間為30分鐘，於絕緣性基材10之背面印刷第2導電膏2 使其乾燥而形成第1晶種層21a之第1晶種層(背)形成步驟(晶種層(背)印刷、乾燥，圖2(e))之處理時間為30分鐘。又，對絕緣性基材10施以無電解鍍銅、而於第1晶種層21a上形成第1無電解電鍍層21b之第1無電解電鍍層形成步驟(無電解電鍍，圖1(b))之處理時間為80分鐘。 On the other hand, in the method of manufacturing the printed wiring board 100 of the present embodiment, the first conductive paste 1 is filled in the through hole 11a, and the first conductive paste 1 is dried to form the first via hole 11 to form the first via hole. The processing time of the step (plug printing, drying, Fig. 2 (c)) was 30 minutes. Moreover, the first seed layer 2 is formed by printing the second conductive paste 2 on the front surface of the insulating base material 10 to form a first seed layer 21a (positive) forming step (seed layer (positive) printing, drying, and the like). The processing time of 2 (d)) is 30 minutes, and the second conductive paste 2 is printed on the back surface of the insulating substrate 10. The treatment time of the first seed layer (back) forming step (printing of the seed layer (back), drying, and FIG. 2 (e)) for drying to form the first seed layer 21a was 30 minutes. Moreover, the first electroless plating layer forming step (electroless plating) is performed by applying electroless copper plating to the insulating base material 10 and forming the first electroless plating layer 21b on the first seed layer 21a, and FIG. 1(b) )) The processing time is 80 minutes.
即，本實施形態之印刷配線板100之製造方法之製造時間(貫通孔形成步驟(圖2(b))除外)為170分鐘，較使用減去法之習知之印刷配線板200之製造時間短，不存在顯影步驟、蝕刻步驟及掩膜去除步驟，而不會產生廢液。 In other words, the manufacturing time of the manufacturing method of the printed wiring board 100 of the present embodiment (excluding the through hole forming step (Fig. 2(b)) is 170 minutes, which is shorter than the manufacturing time of the conventional printed wiring board 200 using the subtraction method. There is no development step, etching step, and mask removal step, and no waste liquid is generated.
如以上般，本實施形態之印刷配線板100利用網版印刷形成成為第1通孔11之第1導電膏1、與成為第1配線21之第1晶種層21a之第2導電膏2，利用無電解電鍍形成第1配線21之第1無電解電鍍層21b，藉此可刪除與蝕刻步驟相關之步驟，而可實現簡易之生產製程。 As described above, the printed wiring board 100 of the present embodiment forms the first conductive paste 1 serving as the first via hole 1 and the second conductive paste 2 serving as the first seed layer 21a of the first wiring 21 by screen printing. By forming the first electroless plating layer 21b of the first wiring 21 by electroless plating, the steps related to the etching step can be deleted, and a simple production process can be realized.
又，本實施形態之印刷配線板100之製造方法與習知之印刷配線板之製造方法進行比較，可削減廢液，改善銅之利用率，並且無需用於顯影步驟、蝕刻步驟及剝離步驟之製造裝置，而可削減設備成本及生產空間。 Further, in the method of manufacturing the printed wiring board 100 of the present embodiment, the waste liquid can be reduced, the utilization of copper can be improved, and the manufacturing process, the etching step, and the peeling step can be eliminated. The device can reduce equipment costs and production space.
再者，本實施形態之印刷配線板100如圖1所示，於絕緣性基材10之正面及背面中之第1通孔11(貫通孔11a)上，將成為第1晶種層21a之第2導電膏2塗佈於整面，第1無電解電鍍層21b隔著第1晶種層21a與第1通孔11間接地接觸，但並不限定於該層結構。 Further, as shown in FIG. 1, the printed wiring board 100 of the present embodiment is a first seed layer 21a on the first through hole 11 (through hole 11a) on the front and back surfaces of the insulating base material 10. The second conductive paste 2 is applied to the entire surface, and the first electroless plated layer 21b is in indirect contact with the first through hole 11 via the first seed layer 21a, but is not limited to this layer structure.
例如，印刷配線板100亦可如圖5(a)及圖5(b)所示，於絕緣性基材10之正面及背面中之第1通孔11上，僅在第1通孔11之除中心區域以外之周緣部，塗佈成為第1晶種層21a之第2導電膏2。 For example, as shown in FIGS. 5( a ) and 5 ( b ), the printed wiring board 100 may be on the first through hole 11 in the front and back surfaces of the insulating base material 10 only in the first through hole 11 . The second conductive paste 2 to be the first seed layer 21a is applied to the peripheral portion other than the central region.
於此情形時，如圖5(c)所示，於絕緣性基材10之正面及背面中之第1通孔11上之中心區域中，第1導電膏1成為第1無電解電鍍層21b之基底膜，第1無電解電鍍層21b與第1通孔11直接接觸。 In this case, as shown in FIG. 5(c), in the central region on the first through hole 11 in the front and back surfaces of the insulating base material 10, the first conductive paste 1 becomes the first electroless plated layer 21b. In the base film, the first electroless plated layer 21b is in direct contact with the first through hole 11.
(本發明之第2實施形態) (Second embodiment of the present invention)
圖6係用以說明第2實施形態之印刷配線板之製造方法之剖視圖，圖6(a)係表示絕緣性基材之剖視圖，圖6(b)係表示形成有貫通孔之狀態之剖視圖，圖6(c)係表示填充有第1導電膏之狀態之剖視圖，圖6(d)係於絕緣性基材之雙面形成有第1晶種層之狀態之剖視圖，圖6(e)係表示於第1晶種層上形成有第2無電解電鍍層之狀態之剖視圖。圖7係用以說明圖6所示之印刷配線板之製造方法的後續步驟之剖視圖，圖7(a)係表示於絕緣性基材之正面形成有絕緣層之狀態之剖視圖，圖7(b)係表示於絕緣性基材之背面形成有絕緣層之狀態之剖視圖，圖7(c)係表示於絕緣性基材之正面側之開口部中填充有第3導電膏之狀態之剖視圖，圖7(d)係表示於絕緣性基材之背面側之開口部中填充有第3導電膏之狀態之剖視圖。圖8係用以說明圖7所示之印刷配線板之製造方法的後續步驟之剖視圖，圖8(a)係表示於絕緣性基材之正面側形成有第2晶種層之狀態之剖視圖，圖8(b)係表示於絕緣性基材之背面側形成有第2晶種層之狀態之剖視圖，圖8(c)係表示於第2晶種層上形成有第2無電解電鍍層之狀態之剖視圖。圖9(a)係表示第2實施形態之印刷配線板之概略構成的另一例之剖視圖。於圖6至圖9(a)中，與圖1至圖5相同之符號表示相同或相當之部分，省略其說明。 6 is a cross-sectional view showing a method of manufacturing a printed wiring board according to a second embodiment, wherein FIG. 6(a) is a cross-sectional view showing an insulating substrate, and FIG. 6(b) is a cross-sectional view showing a state in which a through hole is formed. 6(c) is a cross-sectional view showing a state in which the first conductive paste is filled, and FIG. 6(d) is a cross-sectional view showing a state in which the first seed layer is formed on both surfaces of the insulating base material, and FIG. 6(e) is a cross-sectional view. A cross-sectional view showing a state in which a second electroless plating layer is formed on the first seed layer. 7 is a cross-sectional view for explaining a subsequent step of the method of manufacturing the printed wiring board shown in FIG. 6, and FIG. 7(a) is a cross-sectional view showing a state in which an insulating layer is formed on the front surface of the insulating substrate, and FIG. 7(b) (a) is a cross-sectional view showing a state in which an insulating layer is formed on the back surface of the insulating base material, and FIG. 7(c) is a cross-sectional view showing a state in which the third conductive paste is filled in the opening portion on the front side of the insulating base material. 7(d) is a cross-sectional view showing a state in which the third conductive paste is filled in the opening on the back side of the insulating base material. 8 is a cross-sectional view showing a step subsequent to the method of manufacturing the printed wiring board shown in FIG. 7, and FIG. 8(a) is a cross-sectional view showing a state in which a second seed layer is formed on the front side of the insulating base material. 8(b) is a cross-sectional view showing a state in which a second seed layer is formed on the back side of the insulating base material, and FIG. 8(c) is a view showing a second electroless plating layer formed on the second seed layer. A cross-sectional view of the state. Fig. 9 (a) is a cross-sectional view showing another example of a schematic configuration of a printed wiring board according to a second embodiment. In FIGS. 6 to 9(a), the same reference numerals as those in FIGS. 1 to 5 denote the same or corresponding portions, and the description thereof will be omitted.
本實施形態之印刷配線板100如圖8(c)所示，為多層印 刷配線板，除第1實施形態之印刷配線板100(以下，稱為雙面印刷配線板101)之構成要素以外，進而具備：絕緣層10a，其積層於絕緣性基材10(雙面印刷配線板101)上；開口部12a，其形成於絕緣層10a中之連接於第1配線21之部分；通孔(以下，稱為第2通孔12)，其係向開口部12a中填充導電膏(以下，稱為第3導電膏3)而形成；及配線(以下，稱為第2配線22)，其配設於絕緣層10a上，與第2通孔12連接。 The printed wiring board 100 of the present embodiment is a multilayer printed as shown in FIG. 8(c). In addition to the components of the printed wiring board 100 (hereinafter referred to as the double-sided printed wiring board 101) of the first embodiment, the brushing board further includes an insulating layer 10a laminated on the insulating substrate 10 (double-sided printing) On the wiring board 101), the opening 12a is formed in a portion of the insulating layer 10a that is connected to the first wiring 21, and a through hole (hereinafter referred to as a second via 12) that is filled with conductive in the opening 12a. A paste (hereinafter referred to as a third conductive paste 3) is formed, and wiring (hereinafter referred to as a second wiring 22) is disposed on the insulating layer 10a and connected to the second via hole 12.
又，第2配線22具備：晶種層(以下，稱為第2晶種層22a)，其與第2通孔12連接，作為第2配線22之基底膜由導電膏(以下，稱為第4導電膏4)形成；及無電解電鍍層(以下，稱為第2無電解電鍍層22b)，其被覆第2晶種層22a。 In addition, the second wiring 22 includes a seed layer (hereinafter referred to as a second seed layer 22a) connected to the second via hole 12, and the base film of the second wiring 22 is made of a conductive paste (hereinafter referred to as a 4: a conductive paste 4) is formed; and an electroless plating layer (hereinafter referred to as a second electroless plating layer 22b) covering the second seed layer 22a.
再者，於本實施形態中，第3導電膏3對應於第1導電膏1，第4導電膏4對應於第2導電膏2，可應用第1實施形態中上述之第1導電膏1或第2導電膏2之材料，故而省略第3導電膏3及第4導電膏4之材料之說明。 In the present embodiment, the third conductive paste 3 corresponds to the first conductive paste 1, and the fourth conductive paste 4 corresponds to the second conductive paste 2, and the first conductive paste 1 described above in the first embodiment can be applied. The material of the second conductive paste 2 is omitted, and the description of the materials of the third conductive paste 3 and the fourth conductive paste 4 is omitted.
又，第2無電解電鍍層22b與第1無電解電鍍層21b同樣地由無電解鍍銅所構成，於無電解電鍍處理中使用奧野製藥工業股份有限公司製造之獨立電路基板用無電解鍍銅液「OPC Copper NCA」。 In addition, the second electroless-plated layer 22b is composed of electroless copper plating in the same manner as the first electroless-plated layer 21b, and electroless copper plating for an independent circuit board manufactured by Okuno Pharmaceutical Co., Ltd. is used for the electroless plating treatment. Liquid "OPC Copper NCA".
繼而，使用圖6至圖8對本實施形態之印刷配線板100之製造方法進行說明。 Next, a method of manufacturing the printed wiring board 100 of the present embodiment will be described with reference to FIGS. 6 to 8.
再者，關於本實施形態之印刷配線板100之製造方法，於絕緣性基材10形成貫通孔11a後至形成第1配線21(第1無電解電鍍層21b)為止之製造步驟(參照圖6)為與第1實施形態之雙面印刷配線板101之製造方法相 同之製造步驟，故而省略說明。 In the method of manufacturing the printed wiring board 100 of the present embodiment, the manufacturing process is performed after the through hole 11a is formed in the insulating base material 10 until the first wiring 21 (the first electroless plating layer 21b) is formed (see FIG. 6). The method of manufacturing the double-sided printed wiring board 101 of the first embodiment is The same steps as the manufacturing steps are omitted.
除形成於連接於第1配線21之部分之開口部12a以外，使利用乳劑形成有開口之網版印刷版(未圖示)與絕緣性基材10(雙面印刷配線板101)對向地配置，並將油墨(絕緣樹脂)塗佈於網版印刷版上。 In addition to the opening 12a formed in the portion connected to the first wiring 21, a screen printing plate (not shown) having an opening formed by an emulsion is opposed to the insulating base material 10 (double-sided printed wiring board 101). Configure and apply ink (insulating resin) to the screen printing plate.
網版印刷機(未圖示)使刮漿板於網版印刷版之表面滑動，將網版印刷版抵壓至絕緣性基材10(雙面印刷配線板101)，通過網版印刷版之開口噴出油墨(絕緣樹脂)，於絕緣性基材10(雙面印刷配線板101)之正面，除開口部12a以外，塗佈絕緣樹脂。 A screen printing machine (not shown) slides the squeegee on the surface of the screen printing plate, and presses the screen printing plate against the insulating substrate 10 (double-sided printed wiring board 101) through the screen printing plate. The ink (insulating resin) is ejected from the opening, and an insulating resin is applied to the front surface of the insulating base material 10 (double-sided printed wiring board 101) except for the opening 12a.
然後，使絕緣樹脂於120℃~130℃之硬化爐中熱硬化(乾燥)30分鐘，除開口部12a以外，於絕緣性基材10(雙面印刷配線板101)之正面形成絕緣層10a(參照圖7(a)，絕緣層積層步驟)。 Then, the insulating resin is thermally cured (dried) in a curing furnace at 120 ° C to 130 ° C for 30 minutes, and an insulating layer 10a is formed on the front surface of the insulating base material 10 (double-sided printed wiring board 101) except for the opening portion 12a ( Referring to Fig. 7(a), the insulating layer is laminated.
又，絕緣層積層步驟係於形成有絕緣性基材10(雙面印刷配線板101)之正面側之絕緣層10a之後，將絕緣性基材10翻過來，藉由與絕緣性基材10(雙面印刷配線板101)之正面側相同之製造步驟，於絕緣性基材10(雙面印刷配線板101)之背面側形成絕緣層10a(參照圖7(b))。 Further, after the insulating layer stacking step is performed on the insulating layer 10a on the front side of the insulating base material 10 (the double-sided printed wiring board 101), the insulating base material 10 is turned over by the insulating substrate 10 ( In the manufacturing process in which the front side of the double-sided printed wiring board 101) is the same, the insulating layer 10a is formed on the back side of the insulating base material 10 (double-sided printed wiring board 101) (see FIG. 7(b)).
再者，絕緣層積層步驟亦可為藉由加壓成形，除開口部12a以外，於絕緣性基材10(雙面印刷配線板101)上積層絕緣層10a之製造步驟。 In addition, the insulating layer lamination step may be a manufacturing step of laminating the insulating layer 10a on the insulating base material 10 (double-sided printed wiring board 101) except for the opening portion 12a by press molding.
加壓成形係藉由加壓成形機，於絕緣性基材10(雙面印刷配線板101)上積層將成為開口部12a之部分割除之半硬化狀態之強化塑膠成形材料(預浸料)，對預浸料進行加熱使其熔解，密接於絕緣性基材10及第1配線21並硬化，藉此於絕緣性基材10(雙面印刷配線板101)上形成絕緣層10a(參 照圖7(a)(b)，絕緣層積層步驟)。 In the press molding, a reinforced plastic molding material (prepreg) in which the portion to be the opening portion 12a is divided into a semi-hardened state is laminated on the insulating base material 10 (double-sided printed wiring board 101) by a press molding machine. The prepreg is heated and melted, and adhered to the insulating base material 10 and the first wiring 21 to be cured, whereby the insulating layer 10a is formed on the insulating base material 10 (double-sided printed wiring board 101). According to Fig. 7 (a) (b), the insulating layer is laminated.
然後，使對準絕緣性基材10(雙面印刷配線板101)上之絕緣層10a之表面中之開口部12a之形成位置利用乳劑形成有開口之網版印刷版(未圖示)與絕緣性基材10對向地配置，並將導電油墨(第3導電膏3)塗佈於網版印刷版上。 Then, the position at which the opening portion 12a is formed on the surface of the insulating layer 10a on the insulating base substrate 10 (double-sided printed wiring board 101) is formed by using an emulsion to form an opening screen printing plate (not shown) and insulating. The substrate 10 is disposed opposite to each other, and the conductive ink (third conductive paste 3) is applied onto the screen printing plate.
又，網版印刷機(未圖示)使刮漿板於網版印刷版之表面滑動，將網版印刷版抵壓至絕緣性基材10(雙面印刷配線板101)上之絕緣層10a，通過網版印刷版之開口噴出導電油墨(第3導電膏3)，而填充於絕緣層10a之開口部12a中。 Further, a screen printing machine (not shown) slides the squeegee on the surface of the screen printing plate, and presses the screen printing plate against the insulating layer 10a on the insulating substrate 10 (double-sided printed wiring board 101). The conductive ink (third conductive paste 3) is ejected through the opening of the screen printing plate, and is filled in the opening portion 12a of the insulating layer 10a.
然後，使第3導電膏3於100℃~200℃之硬化爐中熱硬化(乾燥)30分鐘~120分鐘之後，藉由研磨去除自絕緣層10a之表面突出之硬化物，而形成第2通孔12(參照圖7(c)，第2通孔形成步驟)。 Then, after the third conductive paste 3 is thermally cured (dried) in a curing oven at 100 ° C to 200 ° C for 30 minutes to 120 minutes, the cured product protruding from the surface of the insulating layer 10 a is removed by polishing to form a second pass. Hole 12 (refer to Fig. 7 (c), second through hole forming step).
再者，第2通孔形成步驟係於形成有絕緣性基材10(雙面印刷配線板101)之正面側之第2通孔12之後，將絕緣性基材10翻過來，藉由與絕緣性基材10(雙面印刷配線板101)之正面側相同之製造步驟，於絕緣性基材10(雙面印刷配線板101)之背面側形成第2通孔12(參照圖7(d))。 In addition, the second via forming step is performed by turning on the insulating substrate 10 after the second via hole 12 on the front side of the insulating substrate 10 (double-sided printed wiring board 101) is formed, and insulating the substrate 10 In the manufacturing process in which the front side of the base material 10 (double-sided printed wiring board 101) is the same, the second through hole 12 is formed on the back side of the insulating base material 10 (double-sided printed wiring board 101) (refer to FIG. 7(d) ).
然後，使對準絕緣層10a之表面中之第2配線22(第2晶種層22a)之形成位置利用乳劑形成有開口之網版印刷版(未圖示)與絕緣性基材10對向地配置，並將導電油墨(第4導電膏4)塗佈於網版印刷版上。 Then, the position where the second wiring 22 (the second seed layer 22a) is formed on the surface of the insulating layer 10a is opposed to the insulating substrate 10 by a screen printing plate (not shown) having an opening formed by an emulsion. The conductive ink (the fourth conductive paste 4) was applied to the screen printing plate.
又，網版印刷機(未圖示)使刮漿板於網版印刷版之表面滑動，將網版印刷版抵壓至絕緣性基材10(雙面印刷配線板101)上之絕緣層10a，通過網版印刷版之開口噴出導電油墨(第4導電膏4)，而於絕緣層10a之表 面塗佈成線狀。 Further, a screen printing machine (not shown) slides the squeegee on the surface of the screen printing plate, and presses the screen printing plate against the insulating layer 10a on the insulating substrate 10 (double-sided printed wiring board 101). , discharging the conductive ink (the fourth conductive paste 4) through the opening of the screen printing plate, and on the surface of the insulating layer 10a The surface is coated in a line shape.
然後，使第4導電膏4於100℃~120℃之硬化爐中熱硬化(乾燥)30分鐘~120分鐘，形成作為第2配線22之基底膜之第2晶種層22a(參照圖8(a)，第2晶種層形成步驟)。 Then, the fourth conductive paste 4 is thermally cured (dried) in a curing oven at 100 ° C to 120 ° C for 30 minutes to 120 minutes to form a second seed layer 22 a as a base film of the second wiring 22 (refer to FIG. 8 ( a), the second seed layer forming step).
再者，第2晶種層形成步驟係於絕緣性基材10(雙面印刷配線板101)之正面側形成有第2晶種層22a之後，將絕緣性基材10翻過來，藉由與絕緣性基材10(雙面印刷配線板101)之正面側相同之製造步驟，於絕緣性基材10(雙面印刷配線板101)之背面側形成第2晶種層22a(參照圖8(b))。 In addition, in the second seed layer forming step, after the second seed layer 22a is formed on the front side of the insulating base material 10 (double-sided printed wiring board 101), the insulating base material 10 is turned over, and In the manufacturing process in which the front side of the insulating base material 10 (double-sided printed wiring board 101) is the same, the second seed layer 22a is formed on the back side of the insulating base material 10 (double-sided printed wiring board 101) (refer to FIG. 8 (refer FIG. b)).
然後，例如，藉由包含脫脂步驟、預浸步驟、鈀置換處理步驟、鈀殘渣去除步驟及無電解鍍銅步驟之無電解電鍍處理，使第2無電解電鍍層22b於第2晶種層22a上生長(參照圖8(c)，第2無電解電鍍層形成步驟)。 Then, for example, the second electroless plating layer 22b is applied to the second seed layer 22a by an electroless plating treatment including a degreasing step, a prepreg step, a palladium replacement treatment step, a palladium residue removal step, and an electroless copper plating step. The upper growth (refer to Fig. 8 (c), the second electroless plating layer forming step).
再者，本實施形態之無電解電鍍處理(無電解鍍銅)為與第1實施形態之無電解電鍍處理(無電解鍍銅)相同之製造步驟，故而省略詳細之說明。 In addition, the electroless plating treatment (electroless copper plating) of the present embodiment is the same manufacturing step as the electroless plating treatment (electroless copper plating) of the first embodiment, and thus detailed description thereof will be omitted.
然後，為了形成連接於第2配線22之電極(未圖示)，而於絕緣層10a(第2配線22)上之除電極之形成位置以外之區域形成抗蝕劑之掩膜，以第2配線22之第2無電解電鍍層22b為基底膜，實施無電解鍍鎳/鍍金，而形成無電解鍍鎳/鍍金層(電極)。 Then, in order to form an electrode (not shown) connected to the second wiring 22, a mask of a resist is formed on a region other than the position at which the electrode is formed on the insulating layer 10a (second wiring 22), and the second mask is formed. The second electroless plated layer 22b of the wiring 22 is a base film, and electroless nickel plating/gold plating is performed to form an electroless nickel plating/gold plating layer (electrode).
經過以上之步驟，完成本實施形態之印刷配線板100。 Through the above steps, the printed wiring board 100 of the present embodiment is completed.
再者，於本實施形態中，僅在印刷配線板100為多層印刷配線板之方面與第1實施形態不同，除多層印刷配線板及其製造方法之作用 效果以外，發揮與第1實施形態相同之作用效果。 Further, in the present embodiment, the printed wiring board 100 is different from the first embodiment only in that it is a multilayer printed wiring board, and the function of the multilayer printed wiring board and the manufacturing method thereof is different. In addition to the effects, the same operational effects as those of the first embodiment are exhibited.
又，本實施形態之印刷配線板100係列舉4層之多層印刷配線板為例進行了說明，但藉由應用利用導電膏進行之通孔及晶種層之製造步驟以及藉由無電解電鍍進行之配線上層之製造步驟，可形成4層以上之多層印刷配線板。 Further, the printed wiring board 100 of the present embodiment has been described by taking a four-layer multilayer printed wiring board as an example, but by using a manufacturing process of a via hole and a seed layer by a conductive paste, and by electroless plating. In the manufacturing step of the upper layer of the wiring, a multilayer printed wiring board of four or more layers can be formed.
再者，本實施形態之印刷配線板100如圖8(c)所示，於絕緣性基材10之正面及背面中之第1通孔11(貫通孔11a)上，將成為第1晶種層21a之第2導電膏2塗佈於整面，第1無電解電鍍層21b隔著第1晶種層21a與第1通孔11間接地接觸。 Further, as shown in FIG. 8(c), the printed wiring board 100 of the present embodiment is a first seed crystal on the first through hole 11 (through hole 11a) on the front and back surfaces of the insulating base material 10. The second conductive paste 2 of the layer 21a is applied over the entire surface, and the first electroless plated layer 21b is in indirect contact with the first via hole 11 via the first seed layer 21a.
又，本實施形態之印刷配線板100如圖8(c)所示，於絕緣層10a之表面中之第2通孔12(開口部12a)上，將成為第2晶種層22a之第4導電膏4塗佈於整面，第2無電解電鍍層22b隔著第2晶種層22a與第2通孔12間接地接觸。 Further, as shown in FIG. 8(c), the printed wiring board 100 of the present embodiment is the fourth via hole 12 (the opening portion 12a) on the surface of the insulating layer 10a. The conductive paste 4 is applied over the entire surface, and the second electroless plated layer 22b is in indirect contact with the second through holes 12 via the second seed layer 22a.
然而，本實施形態之印刷配線板100並不限定於該層結構。 However, the printed wiring board 100 of the present embodiment is not limited to this layer structure.
例如，印刷配線板100亦可如圖9(a)(圖5(a)、圖5(b))所示，於絕緣性基材10之正面及背面中之第1通孔11上，僅在第1通孔11之除中心區域以外之周緣部，塗佈成為第1晶種層21a之第2導電膏2。 For example, as shown in FIG. 9(a) (FIG. 5(a) and FIG. 5(b)), the printed wiring board 100 may be on the first through hole 11 in the front and back surfaces of the insulating base material 10, only The second conductive paste 2 serving as the first seed layer 21a is applied to the peripheral portion of the first through hole 11 excluding the central portion.
於此情形時，如圖9(a)(圖5(c))所示，於絕緣性基材10之正面及背面中之第1通孔11上之中心區域中，第1導電膏1成為第1無電解電鍍層21b之基底膜，第1無電解電鍍層21b與第1通孔11直接接觸。 In this case, as shown in FIG. 9(a) (FIG. 5(c)), in the central region on the first through hole 11 in the front and back surfaces of the insulating base material 10, the first conductive paste 1 becomes In the base film of the first electroless plated layer 21b, the first electroless plated layer 21b is in direct contact with the first through hole 11.
同樣地，印刷配線板100亦可如圖9(a)所示，於絕緣層10a之表面中之第2通孔12上，僅在第2通孔12之除中心區域以外之周緣部，塗佈成 為第2晶種層22a之第4導電膏4。 Similarly, as shown in FIG. 9(a), the printed wiring board 100 may be coated only on the second through hole 12 of the surface of the insulating layer 10a except for the peripheral portion of the second through hole 12 other than the central portion. Cloth It is the fourth conductive paste 4 of the second seed layer 22a.
於此情形時，如圖9(a)所示，於絕緣層10a之表面中之第2通孔12上之中心區域中，第3導電膏3成為第2無電解電鍍層22b之基底膜，第2無電解電鍍層22b與第2通孔12直接接觸。 In this case, as shown in FIG. 9(a), in the central region on the second via hole 12 in the surface of the insulating layer 10a, the third conductive paste 3 becomes the base film of the second electroless plated layer 22b. The second electroless plated layer 22b is in direct contact with the second through holes 12.
藉由此種層結構，印刷配線板100於通孔(例如，第1通孔11)之部分中，如導電膏(此處，為第1導電膏1)/無電解電鍍(此處，為第1無電解電鍍層21b)/導電膏(此處，為第3導電膏3)/無電解電鍍(此處，為第2無電解電鍍層22b)般，成為導電膏與無電解電鍍之重複之層，而可提高接合之可靠性。 With such a layer structure, the printed wiring board 100 is in a portion of the through hole (for example, the first through hole 11), such as a conductive paste (here, the first conductive paste 1) / electroless plating (here, The first electroless plating layer 21b)/conductive paste (here, the third conductive paste 3)/electroless plating (here, the second electroless plating layer 22b) is a repetition of the conductive paste and the electroless plating. The layer can improve the reliability of the joint.
(本發明之第3實施形態) (Third embodiment of the present invention)
圖9(b)係表示第3實施形態之印刷配線板之概略構成的另一例之剖視圖。圖10係用以說明第3實施形態之印刷配線板之製造方法之剖視圖，圖10(a)係表示於絕緣性基材之正面側形成有第3晶種層之狀態之剖視圖，圖10(b)係表示於絕緣性基材之背面側形成有第3晶種層之狀態之剖視圖，圖10(c)係表示於第3晶種層及第1無電解電鍍層上形成有第3無電解電鍍層之狀態之剖視圖。於圖9(b)及圖10中，與圖1至圖9(a)相同之符號表示相同或相當之部分，省略其說明。 Fig. 9 (b) is a cross-sectional view showing another example of the schematic configuration of the printed wiring board of the third embodiment. FIG. 10 is a cross-sectional view showing a method of manufacturing a printed wiring board according to a third embodiment, and FIG. 10(a) is a cross-sectional view showing a state in which a third seed layer is formed on the front side of the insulating base material, and FIG. b) is a cross-sectional view showing a state in which the third seed layer is formed on the back side of the insulating base material, and FIG. 10(c) shows that the third seed layer and the first electroless plating layer are formed on the third non-electrolytic layer. A cross-sectional view of the state of the electrolytic plating layer. In FIGS. 9(b) and 10, the same reference numerals as those in FIGS. 1 to 9(a) denote the same or corresponding portions, and the description thereof will be omitted.
本實施形態之印刷配線板100如圖10(c)所示，為多層印刷配線板，除第1實施形態之雙面印刷配線板101之構成要素以外，進而具備：絕緣層10a，其積層於絕緣性基材10(雙面印刷配線板101)上；開口部12a，其形成於絕緣層10a中之連接於第1配線21之部分；及配線(以下，稱為第3配線23)，其配設於絕緣層10a上，與第1無電解電鍍層21b連接。 As shown in Fig. 10 (c), the printed wiring board 100 of the present embodiment is a multilayer printed wiring board. In addition to the components of the double-sided printed wiring board 101 of the first embodiment, the printed wiring board 100 further includes an insulating layer 10a laminated thereon. The insulating substrate 10 (double-sided printed wiring board 101); the opening 12a formed in the portion of the insulating layer 10a that is connected to the first wiring 21; and the wiring (hereinafter referred to as the third wiring 23). It is disposed on the insulating layer 10a and is connected to the first electroless plated layer 21b.
又，第3配線23具備：晶種層(以下，稱為第3晶種層23a)，其配設於絕緣層10a上之開口部12a之周緣部及自該周緣部延伸之配線之形成位置，作為第3配線23之基底膜由導電膏(以下，稱為第5導電膏5)形成；及無電解電鍍層(以下，稱為第3無電解電鍍層23b)，其填充至開口部12a中，並且被覆第1無電解電鍍層21b及第3晶種層23a。 Further, the third wiring 23 includes a seed layer (hereinafter referred to as a third seed layer 23a) disposed on a peripheral portion of the opening portion 12a of the insulating layer 10a and a wiring portion extending from the peripheral portion. The base film as the third wiring 23 is formed of a conductive paste (hereinafter referred to as a fifth conductive paste 5), and an electroless plated layer (hereinafter referred to as a third electroless plated layer 23b) filled in the opening portion 12a. The first electroless plated layer 21b and the third seed layer 23a are covered.
再者，於本實施形態中，第5導電膏5對應於第2導電膏2，由於可應用第1實施形態中上述之第2導電膏2之材料，故而省略第5導電膏5之材料之說明。 In the present embodiment, the fifth conductive paste 5 corresponds to the second conductive paste 2, and since the material of the second conductive paste 2 described in the first embodiment can be applied, the material of the fifth conductive paste 5 is omitted. Description.
又，第3無電解電鍍層23b與第1無電解電鍍層21b同樣地由無電解鍍銅所構成，於無電解電鍍處理中使用奧野製藥工業股份有限公司製造之獨立電路基板用無電解鍍銅液「OPC Copper NCA」。 In addition, the third electroless-plated layer 23b is composed of electroless copper plating in the same manner as the first electroless-plated layer 21b, and electroless copper plating for an independent circuit board manufactured by Okuno Pharmaceutical Co., Ltd. is used for the electroless plating treatment. Liquid "OPC Copper NCA".
繼而，使用圖10對本實施形態之印刷配線板100之製造方法進行說明。 Next, a method of manufacturing the printed wiring board 100 of the present embodiment will be described with reference to FIG.
再者，關於本實施形態之印刷配線板100之製造方法，於絕緣性基材10形成貫通孔11a後至形成絕緣層10a為止之製造步驟(參照圖6、圖7(a)、圖7(b))為與第2實施形態之印刷配線板100之製造方法相同之製造步驟，故而省略說明。 In the method of manufacturing the printed wiring board 100 of the present embodiment, the manufacturing process is performed after the through hole 11a is formed in the insulating base material 10 until the insulating layer 10a is formed (see FIGS. 6 and 7(a) and 7( b)) is the same manufacturing step as the method of manufacturing the printed wiring board 100 of the second embodiment, and thus the description thereof is omitted.
使對準絕緣層10a之表面中之開口部12a之周緣部及自該周緣部延伸之配線之形成位置利用乳劑形成有開口之網版印刷版(未圖示)與絕緣性基材10對向地配置，並將導電油墨(第5導電膏5)塗佈於網版印刷版上。 The peripheral portion of the opening portion 12a on the surface of the alignment insulating layer 10a and the position at which the wiring extending from the peripheral portion is formed are opposed to the insulating substrate 10 by a screen-forming plate (not shown) having an opening formed by an emulsion. The conductive ink (the fifth conductive paste 5) is applied to the screen printing plate.
網版印刷機(未圖示)使刮漿板於網版印刷版之表面滑動，將網版印 刷版抵壓至絕緣性基材10(雙面印刷配線板101)上之絕緣層10a，通過網版印刷版之開口噴出導電油墨(第5導電膏5)，於絕緣層10a之表面塗佈成環狀(對應於開口部12a之周緣部)及線狀(對應於自周緣部延伸之配線部)。 Screen printing machine (not shown) slides the squeegee on the surface of the screen printing plate and prints the screen printing The brush plate is pressed against the insulating layer 10a on the insulating substrate 10 (double-sided printed wiring board 101), and the conductive ink (the fifth conductive paste 5) is ejected through the opening of the screen printing plate to be coated on the surface of the insulating layer 10a. The ring shape (corresponding to the peripheral edge portion of the opening portion 12a) and the line shape (corresponding to the wiring portion extending from the peripheral edge portion).
然後，使第5導電膏5於100℃~200℃之硬化爐中熱硬化(乾燥)30分鐘~120分鐘，形成作為第3配線23之基底膜之第3晶種層23a(參照圖10(a)，第3晶種層形成步驟)。 Then, the fifth conductive paste 5 is thermally cured (dried) in a curing oven at 100 ° C to 200 ° C for 30 minutes to 120 minutes to form a third seed layer 23 a as a base film of the third wiring 23 (refer to FIG. 10 ( a), the third seed layer forming step).
再者，第3晶種層形成步驟係於絕緣性基材10(雙面印刷配線板101)之正面側形成有第3晶種層23a之後，將絕緣性基材10翻過來，藉由與絕緣性基材10(雙面印刷配線板101)之正面側相同之製造步驟，於絕緣性基材10(雙面印刷配線板101)之背面側形成第3晶種層23a(參照圖10(b))。 In addition, in the third seed layer forming step, after the third seed layer 23a is formed on the front side of the insulating base material 10 (double-sided printed wiring board 101), the insulating base material 10 is turned over, and In the manufacturing process in which the front side of the insulating base material 10 (double-sided printed wiring board 101) is the same, the third seed layer 23a is formed on the back side of the insulating base material 10 (double-sided printed wiring board 101) (refer to FIG. 10 ( b)).
然後，例如，藉由包含脫脂步驟、預浸步驟、鈀置換處理步驟、鈀殘渣去除步驟及無電解鍍銅步驟之無電解電鍍處理，使第3無電解電鍍層23b於第3晶種層23a及第1無電解電鍍層21b上生長(參照圖10(c)，第3無電解電鍍層形成步驟)。 Then, for example, the third electroless plating layer 23b is applied to the third seed layer 23a by an electroless plating treatment including a degreasing step, a pre-dipping step, a palladium replacement treatment step, a palladium residue removal step, and an electroless copper plating step. And growing on the first electroless plated layer 21b (see FIG. 10(c), the third electroless plating layer forming step).
再者，使第3無電解電鍍層23b於第1無電解電鍍層21b上生長之操作為向開口部12a內填充第3無電解電鍍層23b之操作，而形成絕緣層10a中之通孔。 In addition, the operation of growing the third electroless-plated layer 23b on the first electroless-plated layer 21b is an operation of filling the third electroless-plated layer 23b into the opening 12a to form a via hole in the insulating layer 10a.
又，本實施形態之無電解電鍍處理(無電解鍍銅)除向無電解鍍銅液之浸漬與第1實施形態之無電解電鍍處理(無電解鍍銅)比較為長時間以外，為與第1實施形態之無電解電鍍處理(無電解鍍銅)相同之製造步驟，故而省略詳細之說明。 In addition, the electroless plating treatment (electroless copper plating) of the present embodiment is compared with the electroless plating treatment (electroless copper plating) of the first embodiment in addition to the immersion to the electroless copper plating solution. Since the electroless plating treatment (electroless copper plating) of the first embodiment is the same as the manufacturing steps, detailed description thereof will be omitted.
然後，為了形成連接於第3配線23之電極(未圖示)，而於絕緣層10a(第3配線23)上之除電極之形成位置以外之區域形成抗蝕劑之掩膜，以第3配線23之第3無電解電鍍層23b為基底膜，實施無電解鍍鎳/鍍金，而形成無電解鍍鎳/鍍金層(電極)。 Then, in order to form an electrode (not shown) connected to the third wiring 23, a mask of a resist is formed on a region other than the position at which the electrode is formed on the insulating layer 10a (the third wiring 23), and the third layer is formed. The third electroless plated layer 23b of the wiring 23 is a base film, and electroless nickel plating/gold plating is performed to form an electroless nickel plating/gold plating layer (electrode).
經過以上之步驟，完成本實施形態之印刷配線板100。 Through the above steps, the printed wiring board 100 of the present embodiment is completed.
再者，於本實施形態中，僅在省略向開口部12a中填充第3導電膏3之步驟之方面與第2實施形態不同，除由省略該步驟引起之作用效果以外，發揮與第2實施形態相同之作用效果。 In the present embodiment, the second embodiment is different from the second embodiment in that the step of filling the third conductive paste 3 into the opening 12a is omitted, and the second embodiment is performed in addition to the effect of omitting the step. The same effect of the shape.
又，本實施形態之印刷配線板100係列舉4層之多層印刷配線板為例進行了說明，但藉由應用利用導電膏進行之通孔及晶種層之製造步驟、以及利用無電解電鍍進行之通孔及配線上層之製造步驟，而可形成4層以上之多層印刷配線板。 Further, the printed wiring board 100 of the present embodiment has been described by taking a four-layer multilayer printed wiring board as an example. However, the manufacturing process of the via hole and the seed layer by the conductive paste and the electroless plating are performed. A multilayer printed wiring board having four or more layers can be formed by the manufacturing steps of the via holes and the wiring upper layer.
再者，本實施形態之印刷配線板100如圖10(c)所示，於絕緣性基材10之正面及背面中之第1通孔11(貫通孔11a)上，將成為第1晶種層21a之第2導電膏2塗佈於整面，第1無電解電鍍層21b隔著第1晶種層21a與第1通孔11間接地接觸，但並不限定於該層結構。 Further, as shown in FIG. 10(c), the printed wiring board 100 of the present embodiment is a first seed crystal on the first through hole 11 (through hole 11a) on the front and back surfaces of the insulating base material 10. The second conductive paste 2 of the layer 21a is applied to the entire surface, and the first electroless plated layer 21b is in indirect contact with the first through hole 11 via the first seed layer 21a, but is not limited to this layer structure.
例如，印刷配線板100亦可如圖9(b)(圖5(a)、圖5(b))所示，於絕緣性基材10之正面及背面中之第1通孔11上，僅在第1通孔11之除中心區域以外之周緣部，塗佈成為第1晶種層21a之第2導電膏2。 For example, as shown in FIG. 9(b) (FIG. 5(a) and FIG. 5(b)), the printed wiring board 100 may be on the first through hole 11 in the front and back surfaces of the insulating base material 10, only The second conductive paste 2 serving as the first seed layer 21a is applied to the peripheral portion of the first through hole 11 excluding the central portion.
於此情形時，如圖9(b)(圖5(c))所示，於絕緣性基材10之正面及背面中之第1通孔11上之中心區域中，第1導電膏1成為第1無電解電鍍層21b之基底膜，而第1無電解電鍍層21b與第1通孔11直接接觸。 In this case, as shown in FIG. 9(b) (FIG. 5(c)), in the central region on the first through hole 11 in the front and back surfaces of the insulating base material 10, the first conductive paste 1 becomes The base film of the first electroless plated layer 21b is in direct contact with the first electroless plating layer 21b and the first through hole 11.
然後，印刷配線板100亦可藉由上述之本實施形態之第3晶種層形成步驟及第3無電解電鍍層形成步驟，如圖9(b)所示，以第1配線21之第1無電解電鍍層21b及第3晶種層23a為基底膜使第3無電解電鍍層23b生長，而形成絕緣層10a中之通孔及第3配線23。 Then, the printed wiring board 100 can also be subjected to the third seed layer forming step and the third electroless plating layer forming step of the present embodiment described above, and as shown in FIG. 9(b), the first wiring 21 is first. The electroless plated layer 21b and the third seed layer 23a are base films, and the third electroless plated layer 23b is grown to form through holes and third wires 23 in the insulating layer 10a.
Claims (9)
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| JP2014151083A JP6406598B2 (en) | 2014-07-24 | 2014-07-24 | Printed wiring board and manufacturing method thereof |
| JPJP2014-151083 | 2014-07-24 |
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| JP6788974B2 (en) * | 2016-02-02 | 2020-11-25 | 株式会社村田製作所 | Electronic components |
| KR102046006B1 (en) | 2016-06-07 | 2019-11-18 | 주식회사 엘지화학 | High-current transfer methods utilizing the printed circuit board |
| JP6700207B2 (en) | 2017-02-08 | 2020-05-27 | 矢崎総業株式会社 | How to electrically connect printed circuits |
| KR102421980B1 (en) * | 2017-07-26 | 2022-07-18 | 삼성전기주식회사 | Printed circuit board |
| EP3742870A4 (en) * | 2018-01-15 | 2021-10-06 | Pi-Crystal Incorporation | Flexible substrate, electronic device, and method for manufacturing electronic device |
| JP2022152324A (en) * | 2021-03-29 | 2022-10-12 | 株式会社オートネットワーク技術研究所 | Electrical component and manufacturing method of electrical component |
| WO2024043026A1 (en) * | 2022-08-25 | 2024-02-29 | 日産自動車株式会社 | Vehicular conductive circuit manufacturing method |
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| CN106538076A (en) | 2017-03-22 |
| CN106538076B (en) | 2019-05-17 |
| KR20170039102A (en) | 2017-04-10 |
| KR102371134B1 (en) | 2022-03-04 |
| TW201616927A (en) | 2016-05-01 |
| WO2016013473A1 (en) | 2016-01-28 |
| JP6406598B2 (en) | 2018-10-17 |
| JP2016025329A (en) | 2016-02-08 |
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