TWI635589B - 半導體結構 - Google Patents

半導體結構 Download PDF

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Publication number
TWI635589B
TWI635589B TW105138446A TW105138446A TWI635589B TW I635589 B TWI635589 B TW I635589B TW 105138446 A TW105138446 A TW 105138446A TW 105138446 A TW105138446 A TW 105138446A TW I635589 B TWI635589 B TW I635589B
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TW
Taiwan
Prior art keywords
plate
semiconductor structure
wafer
elastic member
dielectric layer
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TW105138446A
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English (en)
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TW201807790A (zh
Inventor
Pochun Lin
林柏均
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Nanya Technology Corporation
南亞科技股份有限公司
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Application filed by Nanya Technology Corporation, 南亞科技股份有限公司 filed Critical Nanya Technology Corporation
Publication of TW201807790A publication Critical patent/TW201807790A/zh
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Publication of TWI635589B publication Critical patent/TWI635589B/zh

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Abstract

一種半導體結構包含電子元件與板狀結構。板狀結構包含介電層結構與至少一彈性件。介電層結構具有裝置區與圍繞裝置區的邊緣區，其中電子元件設置在裝置區上，邊緣區具有至少一第一通孔。彈性件設置於第一通孔中。

Description

半導體結構
本發明是有關於一種半導體結構。
隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功能、高性能的研發方向。為滿足半導體元件高積集度(Integration)以及微型化(Miniaturization)的要求，半導體封裝結構的各項要求亦越來越高，而前所未見的問題亦可能伴隨產生。舉例來說，在半導體封裝結構的線寬和間距(Pitch)越來越小的同時，接點變得容易產生斷路。
為了進一步改善半導體封裝結構的各項特性，相關領域莫不費盡心思開發。如何能提供一種具有較佳特性的半導體封裝結構，實屬當前重要研發課題之一，亦成為當前相關領域亟需改進的目標。
本發明之一技術態樣是在提供一種半導體結構，以解決接點容易產生斷路的問題。
根據本發明一實施方式，一種半導體結構包含電子元件與板狀結構。板狀結構包含介電層結構與至少一 彈性件。介電層結構具有裝置區與圍繞裝置區的邊緣區，其中電子元件設置在裝置區上，邊緣區具有至少一第一通孔。彈性件設置於第一通孔中。
於本發明之一或多個實施方式中，介電層結構具有相對之第一面與第二面，第一面與第二面裸露彈性件。
於本發明之一或多個實施方式中，彈性件凸出於第一面與第二面的至少其中之一者。
於本發明之一或多個實施方式中，介電層結構具有相對之第一面與第二面，彈性件的厚度大於或等於第一面與第二面之間的最小直線距離。
於本發明之一或多個實施方式中，彈性件之材質為聚醯亞胺(Polyimide，PI)。
於本發明之一或多個實施方式中，彈性件穿過介電層結構。
於本發明之一或多個實施方式中，彈性件相鄰於裝置區。
於本發明之一或多個實施方式中，電子元件在板狀結構上的正投影與彈性件至少部份重疊。
於本發明之一或多個實施方式中，板狀結構之長邊為沿著第一方向，在第一方向上彈性件之中心與電子元件在板狀結構上的正投影的外緣的距離小於5毫米。
於本發明之一或多個實施方式中，板狀結構更包含圖案化導電層，圖案化導電層設置於介電層結構上。
於本發明之一或多個實施方式中，介電層結構更具有至少一第二通孔，板狀結構更包含至少一導電盲孔，導電盲孔設置於第二通孔中且電性連接圖案化導電層。
於本發明之一或多個實施方式中，介電層結構為核心層或中介層。
於本發明之於本發明之一或多個實施方式中，介電層結構包含核心層與至少一增層介電層。
於本發明之一或多個實施方式中，板狀結構為晶片承載件，且電子元件包含晶片。
於本發明之一或多個實施方式中，電子元件更包含複數個凸塊，凸塊連接晶片與板狀結構，其中裝置區的外緣由凸塊中設置於最外圍者的設置位置定義。
於本發明之一或多個實施方式中，電子元件更包含晶片黏著層(Die Attachment)，晶片黏著層設置於晶片與板狀結構之間，其中裝置區的外緣由晶片在板狀結構上的正投影的外緣定義。
於本發明之一或多個實施方式中，電子元件更包含晶片黏著層，晶片黏著層設置於晶片與板狀結構之間，板狀結構之長邊為沿著第一方向，其中裝置區小於晶片在板狀結構上的正投影，且在第一方向上裝置區的外緣與晶片在板狀結構上的正投影的外緣的距離小於5毫米。
於本發明之一或多個實施方式中，板狀結構為印刷電路板，且電子元件包含晶片承載件與設置於晶片承載件上的晶片。
於本發明之一或多個實施方式中，電子元件更包含連接晶片承載件與板狀結構的複數個凸塊，其中裝置區的外緣由凸塊中設置於最外圍者的設置位置定義。
於本發明之一或多個實施方式中，板狀結構為銅箔基板(Copper Clad Laminate)。
因為晶片為設置於裝置區上，因此裝置區將會因為晶片的支持而不會產生嚴重的翹曲。然而，因為沒有其他的支持物，邊緣區的翹曲往往很嚴重。藉由設置彈性件於邊緣區中，由裝置區傳遞至邊緣區的應力將會被彈性件吸收，因而減少邊緣區的翹曲程度，或使邊緣區的翹曲消失。因此，凸塊將不會接收到過大的應力，因而得以避免接點容易產生斷路的問題。
100‧‧‧半導體結構
110‧‧‧電子元件
111‧‧‧晶片
112、126‧‧‧凸塊
120‧‧‧板狀結構
121‧‧‧介電層結構
121a‧‧‧第一面
121b‧‧‧第二面
121h‧‧‧盲孔
121t‧‧‧第二通孔
122‧‧‧裝置區
122w‧‧‧窗口
123‧‧‧邊緣區
123t‧‧‧第一通孔
124、224‧‧‧圖案化導電層
124p‧‧‧導電層
125‧‧‧導電盲孔
127‧‧‧防焊層
127o‧‧‧開口
128a‧‧‧核心層
128b‧‧‧增層介電層
129‧‧‧彈性件
130‧‧‧封裝層
140、141‧‧‧接合導線
190‧‧‧晶片承載件
200‧‧‧印刷電路板
220‧‧‧板狀結構
221‧‧‧介電層結構
222‧‧‧裝置區
223‧‧‧邊緣區
223t‧‧‧第一通孔
224‧‧‧圖案化導電層
229‧‧‧彈性件
第1圖繪示依照本發明一實施方式之半導體結構的剖面示意圖。
第2圖繪示依照本發明另一實施方式之半導體結構的剖面示意圖。
第3圖繪示依照本發明另一實施方式之半導體結構的剖面示意圖。
第4圖繪示依照本發明另一實施方式之半導體結構的剖面示意圖。
第5圖繪示依照本發明另一實施方式之半導體結構的剖面示意圖。
第6圖繪示依照本發明另一實施方式之半導體結構的剖面示意圖。
第7圖繪示依照本發明另一實施方式之半導體結構的剖面示意圖。
第8圖至第12圖繪示依照本發明一實施方式之半導體結構的製程各步驟的剖面示意圖。
第13圖繪示依照本發明一實施方式之半導體結構與印刷電路板的剖面示意圖。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖繪示依照本發明一實施方式之半導體結構100的剖面示意圖。本發明不同實施方式提供一種半導體結構100。具體而言，半導體結構100為封裝結構。
如第1圖所繪示，一種半導體結構100包含電子元件110與板狀結構120。板狀結構120包含介電層結構 121與至少一彈性件129。介電層結構121具有裝置區122與圍繞裝置區122的邊緣區123，其中電子元件110設置在裝置區122上，邊緣區123具有至少一第一通孔123t。彈性件129設置於第一通孔123t中。
具體而言，電子元件110包含晶片111與複數個凸塊112。凸塊112連接晶片111與板狀結構120。板狀結構120為晶片承載件。
具體而言，介電層結構121更具有至少一第二通孔121t。板狀結構120更包含兩個圖案化導電層124與至少一導電盲孔125。兩個圖案化導電層124分別設置於介電層結構121的兩側。導電盲孔125設置於第二通孔121t中且電性連接圖案化導電層124。
板狀結構120更包含複數個凸塊126。凸塊126設置於設置在介電層結構121相對於電子元件110之一側上的圖案化導電層124上。
因為晶片111與板狀結構120具有不同的熱膨脹係數，晶片111與板狀結構120之間的熱膨脹係數不匹配將會導致板狀結構120的翹曲。當板狀結構120設置於印刷電路板上時，板狀結構120的翹曲將會產生應力於凸塊126上，因而導致凸塊126容易損壞，接點容易產生斷路。
因為晶片111為設置於裝置區122上，因此裝置區122將會因為晶片111的支持而不會產生嚴重的翹曲。然而，因為沒有其他的支持物，邊緣區123的翹曲往 往很嚴重。藉由設置彈性件129於邊緣區123中，由裝置區122傳遞至邊緣區123的應力將會被彈性件129吸收，因而減少邊緣區123的翹曲程度，或使邊緣區123的翹曲消失。因此，凸塊126將不會接收到過大的應力，因而得以避免接點容易產生斷路的問題。
具體而言，彈性件129相鄰於裝置區122。應了解到，以上所舉之彈性件129的具體實施方式僅為例示，而非用以限制本發明，本發明所屬技術領域中具有通常知識者，可依實際需要，彈性選擇彈性件129的具體實施方式。
具體而言，彈性件129之材質為聚醯亞胺(Polyimide，PI)。應了解到，以上所舉之彈性件129之材質僅為例示，而非用以限制本發明，本發明所屬技術領域中具有通常知識者，可依實際需要，彈性選擇彈性件129之材質。
在本實施方式中，介電層結構121為核心層，但此並不限制本發明。在其他實施方式中，介電層結構121可為中介層，例如玻璃材質的中介層或者矽材質的中介層。
具體而言，板狀結構120為銅箔基板(Copper Clad Laminate)。設置於介電層結構121的兩側的圖案化導電層124之材質為銅。
具體而言，介電層結構121具有相對之第一面121a與第二面121b，第一面121a與第二面121b裸露彈性件129。換句話說，彈性件129穿過介電層結構121。
在本實施方式中，彈性件129的厚度約等於第一面121a與第二面121b之間的最小直線距離，但此並不限制本發明。在其他實施方式中，彈性件129的厚度可能大於第一面121a與第二面121b之間的最小直線距離。
具體而言，電子元件110在板狀結構120上的正投影與彈性件129至少部份重疊。在本實施方式中，板狀結構120之長邊為沿著第一方向D，在第一方向D上彈性件129之中心與電子元件110在板狀結構120上的正投影的外緣的距離G1小於5毫米。應了解到，以上所舉之電子元件110與板狀結構120的具體實施方式僅為例示，而非用以限制本發明，本發明所屬技術領域中具有通常知識者，可依實際需要，彈性選擇電子元件110與板狀結構120的具體實施方式。
在本實施方式中，裝置區122的外緣由凸塊112中設置於最外圍者的設置位置定義。具體而言，裝置區122的外緣由凸塊112中設置於最外圍者在板狀結構120上的正投影的外緣定義。
板狀結構120更包含兩個防焊層127，防焊層127分別覆蓋設置於介電層結構121之兩側上的兩個圖案化導電層124。
第2圖繪示依照本發明另一實施方式之半導體結構100的剖面示意圖。如第2圖所繪示，本實施方式的半導體結構100與第1圖的半導體結構100大致相同，兩者的主要差異在於，在本實施方式中，彈性件129凸出於第一面121a。因此，彈性件129的厚度大於第一面121a與第二面121b之間的最小直線距離，但此並不限制本發明。在其他實施方式中，彈性件129可能凸出於第一面121a與第二面121b的至少其中之一者。
進一步來說，因為彈性件129凸出於第一面121a，且部份的彈性件129為嵌設於防焊層127中，因此這部份的彈性件129將具有與防焊層127相同的功能。換句話說，嵌設於防焊層127中的此部份的彈性件129亦具有保護圖案化導電層124的功能。
第3圖繪示依照本發明另一實施方式之半導體結構100的剖面示意圖。如第3圖所繪示，本實施方式的半導體結構100與第1圖的半導體結構100大致相同，兩者的主要差異在於，在本實施方式中，半導體結構100更包含封裝層130。封裝層130設置於板狀結構120面對電子元件110的一側並覆蓋電子元件110。在本實施方式中，封裝層130亦設置於防焊層127上且覆蓋晶片111。
封裝層130之材質為封膠膠材(Molding Compound)。具體而言，封裝層130之材質為環氧樹脂。應了解到，以上所舉之封裝層120之材質僅為例示，並非 用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇封裝層130之材質。
第4圖繪示依照本發明另一實施方式之半導體結構100的剖面示意圖。如第4圖所繪示，本實施方式的半導體結構100與第1圖的半導體結構100大致相同，兩者的主要差異在於，在本實施方式中，介電層結構121包含核心層128a與至少一增層介電層128b。進一步來說，圖案化導電層124的數量可能大於兩個，並且一些圖案化導電層124設置於核心層128a與增層介電層128b之間，或者設置於增層介電層128b與增層介電層128b之間(假如增層介電層128b的數量大於兩個)。介電層結構121更包含至少一盲孔121h與至少一埋孔(未繪示)，並且在此實施方式中可能沒有第二通孔121t。導電盲孔125設置於盲孔121h中。
第5圖繪示依照本發明另一實施方式之半導體結構100的剖面示意圖。如第5圖所繪示，本實施方式的半導體結構100與第1圖的半導體結構100大致相同，兩者的主要差異在於，在本實施方式中，電子元件110包含晶片111與晶片黏著層(Die Attachment)113，晶片黏著層113設置於晶片111與板狀結構120之間。裝置區122的外緣由晶片111在板狀結構120上的正投影的外緣定義。
進一步來說，半導體結構100更包含至少一接合導線140。接合導線140連接晶片111與設置於介電層結構121面對電子元件110之一側上的圖案化導電層124。
此外，在本實施方式中，彈性件129沒有凸出於第一面121a與第二面121b的至少其中之一者。但此並不限制本發明。在其他實施方式中，彈性件129可能凸出於第一面121a與第二面121b的至少其中之一者。
具體而言，晶片黏著層113可為黏著膠或者黏著薄膜。應了解到，以上所舉之晶片黏著層113的具體實施方式僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇晶片黏著層113的具體實施方式。
第6圖繪示依照本發明另一實施方式之半導體結構100的剖面示意圖。如第6圖所繪示，本實施方式的半導體結構100與第5圖的半導體結構100大致相同，兩者的主要差異在於，在本實施方式中，裝置區122小於晶片111在板狀結構120上的正投影，且在第一方向D上裝置區122的外緣與晶片111在板狀結構120上的正投影的外緣的距離G2小於5毫米。
第7圖繪示依照本發明另一實施方式之半導體結構100的剖面示意圖。如第7圖所繪示，本實施方式的半導體結構100與第5圖的半導體結構100大致相同，兩者的主要差異在於，在本實施方式中，裝置區122更具有窗口122w。窗口122w將晶片111裸露至板狀結構120相對於電子元件110之一側。另外，半導體結構100並沒有包含接合導線140。取而代之地，半導體結構100更包含至少一接合 導線141。接合導線141連接晶片111與設置於介電層結構121相對於電子元件110之一側上的圖案化導電層124。
第8圖至第12圖繪示依照本發明一實施方式之半導體結構100的製程各步驟的剖面示意圖。如第8圖所繪示，提供介電層結構121(在本實施方式中，介電層結構121為核心層)。然後，形成至少一第一通孔123t於介電層結構121上。
具體而言，第一通孔123t為藉由雷射鑽孔或機械鑽孔形成。應了解到，以上所舉之第一通孔123t的形成方法僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇第一通孔123t的形成方法。
如第9圖所繪示，形成至少一彈性件129於第一通孔123t中。在本實施方式中，彈性件129之材質為聚醯亞胺。彈性件129可藉由先填充溶液態聚醯亞胺於第一通孔123t中，再加熱固化溶液態聚醯亞胺而形成。
然後，如第10圖所繪示，形成兩個導電層124p於介電層結構121的兩側。在本實施方式中，導電層124p之材質為銅。導電層124p為藉由金屬熱壓而形成於介電層結構121的兩側。
如第10圖與第11圖所繪示，形成至少一第二通孔121t於介電層結構121中。然後，形成至少一導電盲孔125於第二通孔121t中。接著，圖案化導電層124p而形成兩個圖案化導電層124。之後，形成兩個防焊層127於 設置於介電層結構121的兩側的兩個圖案化導電層124上，其中這兩個防焊層127分別覆蓋這兩個圖案化導電層124。
具體而言，第二通孔121t為藉由雷射鑽孔或機械鑽孔形成。導電盲孔125為藉由電鍍形成。導電層124p為藉由蝕刻製程而圖案化形成圖案化導電層124。防焊層127分別具有複數個開口127o，以裸露圖案化導電層124。
如第12圖所繪示，設置電子元件110於圖案化導電層124上。在本實施方式中，電子元件110包含晶片111與複數個凸塊112。凸塊112連接晶片111與裸露的圖案化導電層124。
然後形成封裝層130於防焊層127與電子元件110上，於是封裝層130環繞電子元件110。
接著，形成複數個凸塊126於設置於介電層結構121相對於電子元件110之一側上的裸露的圖案化導電層124。
第13圖繪示依照本發明一實施方式之半導體結構100與印刷電路板200的剖面示意圖。如第13圖所繪示，設置半導體結構100於印刷電路板200上，在本實施方式中，凸塊126連接圖案化導電層124與印刷電路板200的圖案化導電層224。
本發明另一實施方式提供一種印刷電路板200，印刷電路板200為半導體結構。在本實施方式中， 印刷電路板200包含電子元件與板狀結構220。電子元件為半導體結構100。板狀結構220包含介電層結構221與至少一彈性件229。介電層結構221具有裝置區222與圍繞裝置區222的邊緣區223，其中半導體結構100設置在裝置區222上，邊緣區223具有至少一第一通孔223t。彈性件229設置於第一通孔223t中。
具體而言，半導體結構100包含晶片承載件190與設置於晶片承載件190上的晶片111。
具體而言，半導體結構100更包含連接晶片承載件190與板狀結構220的複數個凸塊126。裝置區222的外緣由凸塊126中設置於最外圍者的設置位置定義。具體而言，裝置區222的外緣由凸塊126中設置於最外圍者在板狀結構220上的正投影的外緣定義。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (19)

  1. 一種半導體結構，包含：一電子元件；以及一板狀結構，包含：一介電層結構，具有一裝置區與圍繞該裝置區的一邊緣區，其中該電子元件設置在該裝置區上，該邊緣區具有至少一第一通孔；以及至少一彈性件，完全填滿該第一通孔，其中該彈性件相鄰於該裝置區。
  2. 如請求項1所述之半導體結構，其中該介電層結構具有相對之一第一面與一第二面，該第一面與該第二面裸露該彈性件。
  3. 如請求項2所述之半導體結構，其中該彈性件凸出於該第一面與該第二面的至少其中之一者。
  4. 如請求項1所述之半導體結構，其中該介電層結構具有相對之一第一面與一第二面，該彈性件的厚度大於或等於該第一面與該第二面之間的最小直線距離。
  5. 如請求項1所述之半導體結構，其中該彈性件之材質為聚醯亞胺(Polyimide，PI)。
  6. 如請求項1所述之半導體結構，其中該彈性件穿過該介電層結構。
  7. 一種半導體結構，包含：一電子元件；以及一板狀結構，包含：一介電層結構，具有一裝置區與圍繞該裝置區的一邊緣區，其中該電子元件設置在該裝置區上，該邊緣區具有至少一第一通孔；以及至少一彈性件，設置於該第一通孔中，且該電子元件在該板狀結構上的正投影與該彈性件至少部份重疊。
  8. 如請求項7所述之半導體結構，其中該板狀結構之長邊為沿著一第一方向，在該第一方向上該彈性件之中心與該電子元件在該板狀結構上的正投影的外緣的距離小於5毫米。
  9. 如請求項7所述之半導體結構，其中該板狀結構更包含一圖案化導電層，該圖案化導電層設置於該介電層結構上。
  10. 如請求項9所述之半導體結構，其中該介電層結構更具有至少一第二通孔，該板狀結構更包含至少一導電盲孔，該導電盲孔設置於該第二通孔中且電性連接該圖案化導電層。
  11. 如請求項7所述之半導體結構，其中該介電層結構為一核心層或一中介層。
  12. 如請求項7所述之半導體結構，其中該介電層結構包含一核心層與至少一增層介電層。
  13. 如請求項7所述之半導體結構，其中該板狀結構為一晶片承載件，且該電子元件包含一晶片。
  14. 如請求項13所述之半導體結構，其中該電子元件更包含複數個凸塊，該些凸塊連接該晶片與該板狀結構，其中該裝置區的外緣由該些凸塊中設置於最外圍者的設置位置定義。
  15. 如請求項13所述之半導體結構，其中該電子元件更包含一晶片黏著層(Die Attachment)，該晶片黏著層設置於該晶片與該板狀結構之間，其中該裝置區的外緣由該晶片在該板狀結構上的正投影的外緣定義。
  16. 如請求項13所述之半導體結構，其中該電子元件更包含一晶片黏著層，該晶片黏著層設置於該晶片與該板狀結構之間，該板狀結構之長邊為沿著一第一方向，其中該裝置區小於該晶片在該板狀結構上的正投影，且在該第一方向上該裝置區的外緣與該晶片在該板狀結構上的正投影的外緣的距離小於5毫米。
  17. 如請求項7所述之半導體結構，其中該板狀結構為一印刷電路板，且該電子元件包含一晶片承載件與設置於該晶片承載件上的一晶片。
  18. 如請求項17所述之半導體結構，其中該電子元件更包含連接該晶片承載件與該板狀結構的複數個凸塊，其中該裝置區的外緣由該些凸塊中設置於最外圍者的設置位置定義。
  19. 如請求項7所述之半導體結構，其中該板狀結構為一銅箔基板(Copper Clad Laminate)。
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