TWI633597B - 製造晶片級半導體封裝的方法 - Google Patents

製造晶片級半導體封裝的方法 Download PDF

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TWI633597B
TWI633597B TW106140020A TW106140020A TWI633597B TW I633597 B TWI633597 B TW I633597B TW 106140020 A TW106140020 A TW 106140020A TW 106140020 A TW106140020 A TW 106140020A TW I633597 B TWI633597 B TW I633597B
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patent application
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TW106140020A
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TW201822272A (zh
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俊豪 樊
定福 柯
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新加坡商先進科技新加坡有限公司
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Abstract

本發明製造晶片級半導體封裝的方法在製造半導體封裝期間，提供了半導體晶片，該半導體晶片包括多個位於晶片表面的接合焊盤，晶片表面覆蓋有介電材料以在接合焊盤上方形成介電層。去除介電層與接合焊盤的位置相對應的部分以形成多個井，其中每個井被配置為在介電層的頂面與底面之間形成通孔以露出每個接合焊盤。然後，將導電材料沉積於井中以在接合焊盤和介電層的頂面之間形成導電層。之後，切割半導體晶片以形成多個半導體封裝。

Description

製造晶片級半導體封裝的方法
本發明涉及製造半導體封裝的工藝，特別涉及仍是晶片一部分的半導體晶片的封裝。
傳統的半導體封裝技術涉及在封裝過程中將半導體芯片安裝到器件載體如引線框或層疊基板上。儘管封裝技術的進步已經減少了此類器件載體的形狀因素，使得製造的封裝具有與正被封裝(常稱為“芯片級封裝”)的半導體芯片的輪廓幾乎相似的輪廓。在封裝前將其安裝到器件載體上的需求引入了關於最終封裝的尺寸是可減小的障礙。其他的缺點包括半導體芯片與器件載體的物理性質之間的不匹配，這會導致在被組裝的封裝中出現故障的風險更高。
為了克服常規的半導體封裝技術的限制，避免在封裝期間將半導體芯片安裝到器件載體上的需求將會是有益的。因此，封裝半導體晶片，同時它們仍是晶片的一部分。除了其他事項外，此晶片級封裝會提供小尺寸和低電感的益處。
因此，本發明的目的是尋求提供一種使用晶片級封裝來製造半導體封裝的方法。
因而，本發明提供了一種製造半導體封裝的方法，包括步驟：提供半導體晶片，所述半導體晶片包括位於所述晶片的第一側上的多個接合焊盤；用介電質材料覆蓋所述晶片的第一側以在接合焊盤上方形成介電層；去除介電層的與接合焊盤的位置相對應的部分以形成多個井，其中每個井被配置為在介電層的頂面與底面之間形成通孔以露出每個接合焊盤；將導電材料沉積於井中以在接合焊盤與介電層的頂面之間形成導電層；之後，切割半導體晶片以形成多個半導體封裝。
方便的是，下文參考示出本發明具體優選實施方案的附圖來更詳細地描述本發明。不應將附圖和有關描述的特殊性理解為取代權利要求限定的本發明的廣義識別的普遍性。
10‧‧‧晶片
12‧‧‧接合焊盤
14‧‧‧溝槽
16‧‧‧介電層
17‧‧‧殘餘物
18‧‧‧井
20‧‧‧銅層
22‧‧‧抗蝕層
24‧‧‧未掩模的部分
26‧‧‧露出部分
28‧‧‧銅柱
30‧‧‧研磨水準
32‧‧‧切割位置
34‧‧‧金屬種子層
36‧‧‧光致抗蝕層
38‧‧‧金屬層
40‧‧‧露出的金屬種子層
42‧‧‧金屬柱
44‧‧‧露出部分
46‧‧‧金屬種子層
48‧‧‧光致抗蝕層
50‧‧‧薄的金屬層
52‧‧‧金屬種子層
54‧‧‧露出部分
56‧‧‧金屬觸點
60‧‧‧半導體封裝
62‧‧‧研磨的晶片
64‧‧‧背襯模制化合物
66‧‧‧溝槽
68‧‧‧介電層
70‧‧‧井
72‧‧‧金屬種子層
74‧‧‧電鍍抗蝕層
76‧‧‧金屬層
80‧‧‧阻焊層
81‧‧‧球焊盤
82‧‧‧焊接球
84‧‧‧切割位置
86‧‧‧半導體封裝
現將參考附圖描述根據本發明的製造半導體封裝的方法的具體實施例，如下列附圖所示。
圖1A-1L示出了根據本發明的第一優選實施方案的製造工藝，其中，在該工藝期間，在介電層的整個表面上方形成金屬層；圖2A-2K示出了根據本發明的第二優選實施方案的製造工藝，其中，金屬層僅電鍍於形成在介電層的表面上的井中；圖3A-3L示出了根據本發明的第三優選實施方案的製造工藝，其中，在 該工藝期間，將金屬觸點置於半導體芯片的接合焊盤上；圖4A-4N示出了根據本發明的第四優選實施方案的製造工藝，其中，在該製造工藝的早期階段模制半導體晶片的背面。
圖1A-1L示出了根據本發明的第一優選實施方案的半導體封裝的製造工藝，其中，在該工藝期間，在介電層16的整個表面上方形成金屬層，如銅層20。
在圖1A中，提供了半導體晶片10，包括半導體芯片，所述半導體芯片包括位於晶片10的第一側的接合焊盤12。然後晶片10被部分切割至小於晶片10的厚度的深度以形成溝槽14，如圖1B所示。可使用標準刀片鋸或通過鐳射加工來形成此溝槽14。這些溝槽14優選地形成於半導體封裝60在由該工藝獲得的最終產物中預被分隔開的位置處。
在形成溝槽14後，包括接合焊盤12的晶片10的頂部或第一側以及溝槽14被介電材料覆蓋和填充以形成介電層16。形成介電層的工藝包括但不限於用環氧模制化合物進行模制，用液態旋塗介電材料進行旋塗或使用介電材料的薄膜或薄板進行層疊。優選地，介電材料應能光致成像以促進在接下來的步驟中依序顯示接合焊盤12的工藝。介電層16基本上覆蓋了晶片10的頂側以及填充了溝槽14(參見圖1C)。
之後，由介電層16覆蓋的接合焊盤12應通過去除介電層16的與接合焊盤12的位置相對應的部分如通過鑽穿包括在介電層16的介電材料而露出(參見圖1D)。可通過使用鐳射加工進行鑽孔來執行在介電層16 中形成井18的此類去除工藝，儘管也有可能會採用去除介電材料以形成井18的其他方式，如通過選擇性化學蝕刻或光致成像顯影工藝。因而，每個井18被配置為在介電層16的頂面與底面之間形成通孔以露出每個接合焊盤12。
在圖1E中，金屬種子層(其可包括薄的銅層)通過物理蒸鍍(“PVD”)或化學鍍形成在介電層16的介電材料的整個表面和露出的接合焊盤12上。除了銅之外，薄層也可由其他金屬形成，如鎳或鈦，沒有限制。
這之後，將導電材料沉積於井18中以在接合焊盤12與介電材料16的頂面之間形成導電層。這可通過將電解銅電鍍到位於晶片10的頂側的井18中來實現。結果，銅層20覆蓋介電層16的整個表面和位於井18底部的露出的接合焊盤12。
在圖1F中，之後，將光致可成像抗蝕層22施用在整個銅層20的上方。此光致可成像抗蝕層22用作隨後用於蝕刻銅層20的掩膜。因此，如通過光致成像選擇性地去除部分光致可成像抗蝕層22以使未掩膜的部分24顯影，所述未掩膜的部分24使在下面的銅層20露出(參見圖1G)。
然後，蝕刻銅層20的露出部分，使得位於光致可成像抗蝕層22的未掩膜的部分24處的銅材料被蝕刻掉以顯示介電層16的露出部分26(參見1H)。在顯示介電層16的露出部分26的工藝後，通過適宜的手段進一步選擇性剝離剩餘的光致可成像抗蝕層22，使得僅保留沉積在井18中的銅層20的一部分以留下露出的銅柱28，如圖1I所示。
在已形成露出的銅柱28後，通過晶片研磨工藝去除晶片10的底側的材料，直到晶片10的厚度減少至研磨水準30，所述研磨水準處於 足以露出填充在溝槽14中的介電材料的底部的水準。如圖1J所示，該研磨工藝使介電層16的底部露出並使包括在晶片10中的半導體芯片的不同部分分隔開以使它們通過介電層16基本上保持在一起。
在圖1K中，在已經完成研磨至研磨水準30後，沿著與溝槽14相對應的切割位置32切割晶片10，所述切割位置也與晶片10已在介電層16的底側露出的位置對應。因而，生產了包括多個切割半導體封裝60的期望的最終產品。
此外，通過設置用於沿著切割位置32切割晶片10的比溝槽14的寬度小的適宜切割寬度，人們可選擇在切割完成後沿著半導體封裝60的邊留下介電層16的殘餘物17，如圖1L所示。然後，介電層16的殘餘物17將附著在已被分隔開的半導體封裝60的側壁上。
圖2A-2K示出了根據本發明的第二優選實施方案的製造工藝，其中金屬層38僅電鍍至位於介電層16表面上的井18中。
在圖2A中，提供了半導體晶片10，所述半導體晶片包括半導體芯片，所述半導體芯片包括接合焊盤12。晶片10被部分切割至小於晶片10的厚度的深度以形成溝槽14，如圖2B所示。可使用標準刀片鋸或通過鐳射加工來形成此溝槽14。這些溝槽14優選地形成於半導體封裝60在由該工藝獲得最終產品中預被分隔開的位置處。
在形成溝槽14後，模制晶片10的頂側，使得包括介電材料的介電層16基本上覆蓋晶片10的頂側以及填充溝槽14(參見圖2C)。
之後，應通過去除介電層16的與接合焊盤12的位置相對應的某部分如通過鑽穿包括在介電層16中的介電材料來使接合焊盤12露出(參 見圖2D)。可使用鐳射加工來進行在介電層16上形成井18的鑽孔，儘管也有可能採用去除介電材料的其他方式，包括選擇性化學蝕刻或光致成像顯影工藝。
在圖2E中，通過PVD或化學鍍形成金屬種子層34(其可包括薄的銅層)。金屬種子層34覆蓋介電層16的頂側和側壁以及接合焊盤12。
然後，首先應用光致抗蝕層36以覆蓋包括井的金屬種子層34的整個頂面。之後，對該光致抗蝕層施用成像顯影工藝以僅僅露出預電鍍銅的區域(參見圖2F)。結果為在位於介電層16上的金屬種子層34的整個頂面而不是井18的上方選擇性地應用光致抗蝕層36。因此，光致抗蝕層36用於顯影金屬電鍍圖案。在圖2G中，可包括銅的金屬層38被電鍍至未被光致層36覆蓋的井18中。金屬層38的電鍍能夠使金屬層形成連接端子以將接合焊盤12電連接至介電層16的頂面。
然後，如圖2H所示，剝離光致抗蝕層36以顯示從上述電鍍步驟形成的露出的金屬種子層40和金屬柱42。然後，如圖2I所示，蝕刻露出的金屬種子層40，以顯露出介電層16的露出部分44。
在已經形成露出的金屬層38和金屬柱42後，通過晶片研磨工藝去除晶片10的底側的材料，直到晶片10的厚度減少至研磨水準30，所述研磨水準處於之前形成溝槽14的水準。如圖2J所示，該研磨工藝使介電層16的底部露出並使包括在晶片10的半導體芯片的不同部分被分隔開以使它們被介點層16基本上保持在一起。
在圖2K中，在已經完成研磨至研磨水準30後，沿著與溝槽14的切割位置32切割晶片10，所述切割位置也是介電層16已經在晶片10的 底側露出的位置。因而，產生了包括多個切割半導體封裝60的期望的最終產品。
圖3A-3L示出了根據本發明的第三優選實施方案的製造工藝，其中在工藝期間，將金屬觸點56置於半導體芯片的接合焊盤12上。
在圖3A中，提供了半導體晶片10，所述半導體晶片包括版單體芯片，所述半導體芯片包括含有接合焊盤12。晶片10被部分切割至小於晶片10的厚度的深度以形成溝槽14，如圖3B所示。可使用標準刀片鋸或通過鐳射加工形成此溝槽14。這些溝槽14優選地形成於半導體封裝60在由工藝獲得的最終產品中預被分隔開的位置處。
在形成溝槽14後，模制晶片10的頂側，使得包括介電材料的介電層16基本上覆蓋晶片10的頂側以及填充溝槽14(參見圖13C)。
之後，通過去除介電層16的與接合焊盤12的位置相對應的某部分如通過鑽穿包括在介電層16中的介電材料來露出接合焊盤12(參見圖3D)。可使用鐳射加工來執行在介電層16上形成井18的此類鑽孔，儘管也有可能採用去除介電材料的其它方式。
在圖3E中，通過PVD或化學鍍形成金屬種子層46(其可包括薄的銅層)。金屬種子層46覆蓋介電層16的頂側和側壁以及接合焊盤12。
在圖3F中，在位於介電層16上的金屬種子層46的頂面但不包括井18的上方選擇性地應用光致抗蝕層48。光致抗蝕層48用於顯影金屬電鍍圖案。
在圖3G中，將可包括銅的另一薄的金屬層50電鍍於未被光致抗蝕層48覆蓋的井18的各個表面上。與根據本發明的第二實施方案的工 藝不同，薄的金屬層50不填充整個井18但只覆蓋接合焊盤12、井18的側面以及介電層16的頂面上的小區域。
然後，如圖3H所示，剝離光致抗蝕層48以顯示位於介電層16的頂面上的露出的金屬種子層52。然後，蝕刻露出的金屬種子層46以顯示介電層16的露出部分54，如圖3I所示。在蝕刻掉露出的金屬種子層後，仍將有覆蓋接合焊盤12、井18的側壁以及與位於介電層16的頂面上的井18相鄰的小區域的剩餘的金屬層。
之後，將可包括焊料的金屬觸點56置於或附接於已經電鍍有薄的金屬層50的井18中。金屬觸點56用於形成將接合焊盤12電連接至介電層16的頂面的連接端子，並可以焊球的形式存在。
在露出的金屬觸點56已經粘附於接合焊盤上後，通過晶片研磨工藝去除晶片10的底側的材料，直到晶片10的厚度減少至研磨水準30，所述研磨水準處於之前形成溝槽14的水準。如圖3J所示，該研磨工藝使介電層16的底部露出並使包括在晶片10中的半導體芯片的不同部分被分隔開以使它們由介電層16基本上保持在一起。
在圖3K中，在已經完成研磨至研磨水準30後，沿著與溝槽14相對應的切割位置32切割晶片10，所述切割位置也是與晶片10已經在介電層16的底側露出的位置。因而，產生了包括多個切割半導體封裝60的期望的最終產品。
圖4A-4N示出了根據本發明的第四優選實施方案的製造工藝，其中在製造工藝的早期階段模制半導體晶片的背面。
在圖4A中，提供了半導體晶片10，所述半導體晶片包括半 導體芯片，所述半導體芯片包括接合焊盤12。在圖4B中，研磨晶片10(其不包括接合焊盤12)的背面或第二側以使所得到的研磨的晶片62具有在最終產品中所期望的厚度。然後，模制研磨的晶片62，使得研磨的晶片62的與第一側相對的背面或第二側以及晶片10的側面覆蓋有背襯模制化合物64(參見圖4C)，如環氧模制化合物。
在圖4D中，模制的研磨的晶片62的與背部或第二側相對的頂部或第一側被部分切割至可延伸穿過研磨過的晶片10的深度，並且部分延伸至背襯模制化合物64中以形成溝槽66。因此，部分研磨的晶片62彼此分隔開，儘管它們仍通過背襯模制化合物64保持在一起。
在形成溝槽66後，模制晶片10的頂部或第一側，使得包括介電材料的介電層68基本上覆蓋研磨的晶片62的頂部或第一側，以及填充溝槽66(參見圖4E)。然後，通過去除某部分介電層68來在介電層68上形成通孔或井70以露出已被介電層68覆蓋的接合焊盤12(參見圖4F)。可通過在介電層68上進行的去除工藝如通過使用鐳射加工進行鑽孔、選擇性化學蝕刻、光致成像顯影工藝或其他適宜的去除工藝來形成井70。
在圖4G中，通過顯影包括金屬如銅、鎳或鈦的金屬種子層72來金屬化介電層68的頂側和接合焊盤12。在圖4H中，圖案化的電鍍抗蝕層74形成在金屬種子層72的頂部。然後，將可包括銅的圖案化的金屬層76選擇性地圖案化到金屬種子層72的頂側上，如圖4I所示。
在已形成圖案化金屬層76後，剝離電鍍抗蝕層74以形成分隔開的部分圖案化的金屬層76(參見圖4J)。之後，蝕刻掉介電層68上露出的金屬種子層72的殘餘物以露出介電層68，如圖4K所示。在圖4L中，在將焊 接觸點置於圖案化的金屬層76(與接合焊盤12的位置對應)的球焊盤81上的準備過程中，將阻焊層80塗覆在圖案化的金屬層76上以覆蓋未收到焊接觸點的圖案化的金屬層76的剩餘部分。然後，將可以焊接球82的形式存在的焊接觸點在未被阻焊層80覆蓋的區域附接至位於球焊盤81上，如圖4M所示。
最終，沿著與溝槽66相對應的切割位置84切割研磨的晶片62。因而，產生了包括多個在半導體封裝86的背側具有背襯模制化合物64的切割半導體封裝86。此背襯模制化合物64有助於提高每個切割半導體封裝86的剛性。
應認識到，根據本發明的優選實施方案的製造工藝使最終半導體封裝的端子觸點直接形成到半導體芯片的接合焊盤上。這使得該製造工藝成本低廉，並且由於直接相互作用而產生更好地電學性能和更少的電學干擾。
除了特別描述的，此處描述的本發明易於變化、修改和/或添加，應理解的是本發明包括所有落在上述描述精神和範圍內的此類變化、修改和/或添加。

Claims (20)

  1. 一種製造半導體封裝的方法，其特徵在於，包括以下步驟：提供半導體晶片，所述半導體晶片包括位於所述晶片的第一側上的多個接合焊盤；用介電質材料覆蓋所述晶片的第一側以在接合焊盤上方形成介電層；去除所述介電層與接合焊盤的位置相對應的部分以形成多個井，其中每個井被配置為在介電層的頂面與底面之間形成通孔以露出每個接合焊盤；將導電材料沉積於所述井中以在所述接合焊盤與所述介電層的頂面之間形成導電層；之後切割所述半導體晶片以形成多個半導體封裝。
  2. 如申請專利範圍第1項所述的方法，其中，進一步包括步驟：在所述半導體晶片的第一側上切割出溝槽，其中用介電質材料覆蓋所述晶片的第一側的步驟進一步包括用所述介電材料填充所述溝槽。
  3. 如申請專利範圍第2項所述的方法，其中，所述切割半導體晶片的步驟進一步包括以下步驟：沿著溝槽將所述半導體封裝分隔開。
  4. 如申請專利範圍第2項所述的方法，其中，所述介電材料包括環氧模制化合物或旋塗材料。
  5. 如申請專利範圍第2項所述的方法，其中，在切割所述半導體晶片之前，將所述半導體晶片的與第一側相對的第二側研磨至足以露出填充在每個溝槽中的介電材料的底部的水準。
  6. 如申請專利範圍第5項所述的方法，其中，切割所述半導體晶片的切割寬度小於溝槽的寬度，使得介電材料粘附於已經被分隔開的所述半導體封裝的側壁上。
  7. 如申請專利範圍第1項所述的方法，其中，所述去除部分介電層包括選自由鑽孔、蝕刻和光致成像顯影工藝所組成的組的去除工藝。
  8. 如申請專利範圍第1項所述的方法，其中，在形成所述井之後，還包括步驟：在形成所述導電層之前，在所述介電材料的整個表面和接合焊盤上形成金屬種子層。
  9. 如申請專利範圍第8項所述的方法，其中，所述金屬種子層包括由物理蒸鍍或化學鍍形成的薄層，並且其中所述薄層包括由銅、鎳和鈦組成的組中的金屬。
  10. 如申請專利範圍第8項所述的方法，其中，將所述導電材料沉積於井中的步驟包括將所述導電材料沉積於包括所述井的介電材料的整個表面的上方，之後，從所述介電材料中選擇性地去除所述導電材料，使得僅保留部分沉積於井中的導電材料。
  11. 如申請專利範圍第8項所述的方法，其中，進一步包括步驟：用光致抗蝕層覆蓋位於所述井外側的所述介電材料的表面，之後，將更薄的金屬層電鍍於包括在所述井中的金屬種子層的表面上。
  12. 如申請專利範圍第11項所述的方法，其中，所述更薄的金屬層覆蓋所述接合焊盤和所述井的側壁以及位於所述井外側的介電材料的表面的小區域。
  13. 如申請專利範圍第12項所述的方法，其中，所述將導電材料沉積於井中的步驟包括步驟：將金屬觸點附接於電鍍有更薄的金屬層的區域。
  14. 如申請專利範圍第13項所述的方法，其中，所述金屬觸點包括焊球。
  15. 如申請專利範圍第1項所述的方法，其中，進一步包括步驟：在所述接合焊盤上方形成所述介電材料之前，研磨所述半導體晶片的與所述第一側相對的第二側。
  16. 如申請專利範圍第15項所述的方法，其中，進一步包括步驟：在所述接合焊盤上方形成所述介電層之前，用背襯模制化合物模制所述半導體晶片的第二側。
  17. 如申請專利範圍第16項所述的方法，其中，進一步包括步驟：在所述半導體晶片的第一側上切割出溝槽，其中所述溝槽從所述第一側延伸穿過所述半導體晶片並部分延伸至所述背襯模制化合物中，並且其中，所述用介電材料覆蓋所述晶片的第一側的步驟進一步包括用所述介電材料填充所述溝槽。
  18. 如申請專利範圍第17項所述的方法，其中，在形成所述井之後，還包括步驟：在形成所述導電層之前，在所述介電材料的整個表面和接合焊盤上形成金屬種子層。
  19. 如申請專利範圍第18項所述的方法，其中，進一步包括步驟：在形成所述導電層之前，在所述金屬種子層上形成圖案化的金屬層。
  20. 如申請專利範圍第19項所述的方法，其中，進一步包括將阻焊層塗覆在所述圖案化的金屬層上，並且其中所述將導電材料沉積於井中的步驟包括之後將焊接觸點附接於未塗覆所述阻焊層的區域。
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