CN108122789A - 制造晶片级半导体封装的方法 - Google Patents

制造晶片级半导体封装的方法 Download PDF

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Publication number
CN108122789A
CN108122789A CN201711213016.0A CN201711213016A CN108122789A CN 108122789 A CN108122789 A CN 108122789A CN 201711213016 A CN201711213016 A CN 201711213016A CN 108122789 A CN108122789 A CN 108122789A
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Prior art keywords
layer
well
bond pad
dielectric material
chip
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樊俊豪
柯定福
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ASMPT Singapore Pte Ltd
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ASM Technology Singapore Pte Ltd
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Publication of CN108122789A publication Critical patent/CN108122789A/zh
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Abstract

本发明制造晶片级半导体封装的方法在制造半导体封装期间，提供了半导体晶片，该半导体晶片包括多个位于晶片表面的接合焊盘，晶片表面覆盖有介电材料以在接合焊盘上方形成介电层。去除介电层与接合焊盘的位置相对应的部分以形成多个井，其中每个井被配置为在介电层的顶面与底面之间形成通孔以露出每个接合焊盘。然后，将导电材料沉积于井中以在接合焊盘和介电层的顶面之间形成导电层。之后，切割半导体晶片以形成多个半导体封装。

Description

制造晶片级半导体封装的方法
技术领域
本发明涉及制造半导体封装的工艺，特别涉及仍是晶片一部分的半导体芯片的封装。
背景技术
传统的半导体封装技术涉及在封装过程中将半导体芯片安装到器件载体如引线框或层叠基板上。尽管封装技术的进步已经减少了此类器件载体的形状因素，使得制造的封装具有与正被封装（常称为“芯片级封装”）的半导体芯片的轮廓几乎相似的轮廓。在封装前将其安装到器件载体上的需求引入了关于最终封装的尺寸是可减小的障碍。其他的缺点包括半导体芯片与器件载体的物理性质之间的不匹配，这会导致在被组装的封装中出现故障的风险更高。
为了克服常规的半导体封装技术的限制，避免在封装期间将半导体芯片安装到器件载体上的需求将会是有益的。因此，封装半导体芯片，同时它们仍是晶片的一部分。除了其他事项外，此晶片级封装会提供小尺寸和低电感的益处。
发明内容
因此，本发明的目的是寻求提供一种使用晶片级封装来制造半导体封装的方法。
因而，本发明提供了一种制造半导体封装的方法，包括步骤：提供半导体晶片，所述半导体晶片包括位于所述晶片的第一侧上的多个接合焊盘；用介电质材料覆盖所述晶片的第一侧以在接合焊盘上方形成介电层；去除介电层的与接合焊盘的位置相对应的部分以形成多个井，其中每个井被配置为在介电层的顶面与底面之间形成通孔以露出每个接合焊盘；将导电材料沉积于井中以在接合焊盘与介电层的顶面之间形成导电层；之后，切割半导体晶片以形成多个半导体封装。
方便的是，下文参考示出本发明具体优选实施方案的附图来更详细地描述本发明。不应将附图和有关描述的特殊性理解为取代权利要求限定的本发明的广义识别的普遍性。
附图说明
现将参考附图描述根据本发明的制造半导体封装的方法的具体实施例，如下列附图所示。
图1A-1L示出了根据本发明的第一优选实施方案的制造工艺，其中，在该工艺期间，在介电层的整个表面上方形成金属层。
图2A-2K示出了根据本发明的第二优选实施方案的制造工艺，其中，金属层仅电镀于形成在介电层的表面上的井中。
图3A-3L示出了根据本发明的第三优选实施方案的制造工艺，其中，在该工艺期间，将金属触点置于半导体芯片的接合焊盘上。
图4A-4N示出了根据本发明的第四优选实施方案的制造工艺，其中，在该制造工艺的早期阶段模制半导体晶片的背面。
具体实施方案
图1A-1L示出了根据本发明的第一优选实施方案的半导体封装的制造工艺，其中，在该工艺期间，在介电层16的整个表面上方形成金属层，如铜层20。
在图1A中，提供了半导体晶片10，包括半导体芯片，所述半导体芯片包括位于晶片10的第一侧的接合焊盘12。然后晶片10被部分切割至小于晶片10的厚度的深度以形成沟槽14，如图1B所示。可使用标准刀片锯或通过激光加工来形成此沟槽14。这些沟槽14优选地形成于半导体封装60在由该工艺获得的最终产物中预被分隔开的位置处。
在形成沟槽14后，包括接合焊盘12的晶片10的顶部或第一侧以及沟槽14被介电材料覆盖和填充以形成介电层16。形成介电层的工艺包括但不限于用环氧模制化合物进行模制，用液态旋涂介电材料进行旋涂或使用介电材料的薄膜或薄板进行层叠。优选地，介电材料应能光致成像以促进在接下来的步骤中依序显示接合焊盘12的工艺。介电层16基本上覆盖了晶片10的顶侧以及填充了沟槽14（参见图1C）。
之后，由介电层16覆盖的接合焊盘12应通过去除介电层16的与接合焊盘12的位置相对应的部分如通过钻穿包括在介电层16的介电材料而露出（参见图1D）。可通过使用激光加工进行钻孔来执行在介电层16中形成井18的此类去除工艺，尽管也有可能会采用去除介电材料以形成井18的其他方式，如通过选择性化学蚀刻或光致成像显影工艺。因而，每个井18被配置为在介电层16的顶面与底面之间形成通孔以露出每个接合焊盘12。
在图1E中，金属种子层（其可包括薄的铜层）通过物理蒸镀（“PVD”）或化学镀形成在介电层16的介电材料的整个表面和露出的接合焊盘12上。除了铜之外，薄层也可由其他金属形成，如镍或钛，没有限制。
这之后，将导电材料沉积于井18中以在接合焊盘12与介电材料16的顶面之间形成导电层。这可通过将电解铜电镀到位于晶片10的顶侧的井18中来实现。结果，铜层20覆盖介电层16的整个表面和位于井18底部的露出的接合焊盘12。
在图1F中，之后，将光致可成像抗蚀层22施用在整个铜层20的上方。此光致可成像抗蚀层22用作随后用于蚀刻铜层20的掩膜。因此，如通过光致成像选择性地去除部分光致可成像抗蚀层22以使未掩膜的部分24显影，所述未掩膜的部分24使在下面的铜层20露出（参见图1G）。
然后，蚀刻铜层20的露出部分，使得位于光致可成像抗蚀层22的未掩膜部分24处的铜材料被蚀刻掉以显示介电层16的露出部分26 （参见1H）。在显示介电层16的露出部分26的工艺后，通过适宜的手段进一步选择性剥离剩余的光致可成像抗蚀层22，使得仅保留沉积在井18中的铜层20的一部分以留下露出的铜柱28，如图1I所示。
在已形成露出的铜柱28后，通过晶片研磨工艺去除晶片10的底侧的材料，直到晶片10的厚度减少至研磨水平30，所述研磨水平处于足以露出填充在沟槽14中的介电材料的底部的水平。如图1J所示，该研磨工艺使介电层16的底部露出并使包括在晶片10中的半导体芯片的不同部分分隔开以使它们通过介电层16基本上保持在一起。
在图1K中，在已经完成研磨至研磨水平30后，沿着与沟槽14相对应的切割位置32切割晶片10，所述切割位置也与晶片10已在介电层16的底侧露出的位置对应。因而，生产了包括多个切割半导体封装60的期望的最终产品。
此外，通过设置用于沿着切割位置32切割晶片10的比沟槽14的宽度小的适宜切割宽度，人们可选择在切割完成后沿着半导体封装60的边留下介电层16的残余物17，如图1L所示。然后，介电层16的残余物17将附着在已被分隔开的半导体封装60的侧壁上。
图2A-2K示出了根据本发明的第二优选实施方案的制造工艺，其中金属层38仅电镀至位于介电层16表面上的井18中。
在图2A中，提供了半导体晶片10，所述半导体晶片包括半导体芯片，所述半导体芯片包括接合焊盘12。晶片10被部分切割至小于晶片10的厚度的深度以形成沟槽14，如图2B所示。可使用标准刀片锯或通过激光加工来形成此沟槽14。这些沟槽14优选地形成于半导体封装60在由该工艺获得最终产品中预被分隔开的位置处。
在形成沟槽14后，模制晶片10的顶侧，使得包括介电材料的介电层16基本上覆盖晶片10的顶侧以及填充沟槽14（参见图2C）。
之后，应通过去除介电层16的与接合焊盘12的位置相对应的某部分如通过钻穿包括在介电层16中的介电材料来使接合焊盘12露出（参见图2D）。可使用激光加工来进行在介电层16上形成井18的钻孔，尽管也有可能采用去除介电材料的其他方式，包括选择性化学蚀刻或光致成像显影工艺。
在图2E中，通过PVD或化学镀形成金属种子层34（其可包括薄的铜层）。金属种子层34覆盖介电层16的顶侧和侧壁以及接合焊盘12。
然后，首先应用光致抗蚀层36以覆盖包括井的金属种子层34的整个顶面。之后，对该光致抗蚀层施用成像显影工艺以仅仅露出预电镀铜的区域（参见图2F）。结果为在位于介电层16上的金属种子层34的整个顶面而不是井18的上方选择性地应用光致抗蚀层36。因此，光致抗蚀层36用于显影金属电镀图案。在图2G中，可包括铜的金属层38被电镀至未被光致层36覆盖的井18中。金属层38的电镀能够使金属层形成连接端子以将接合焊盘12电连接至介电层16的顶面。
然后，如图2H所示，剥离光致抗蚀层36以显示从上述电镀步骤形成的露出的金属种子层40和金属柱42。
在已经形成露出的金属层38和金属柱42后，通过晶片研磨工艺去除晶片10的底侧的材料，直到晶片10的厚度减少至研磨水平30，所述研磨水平处于之前形成沟槽14的水平。如图2J所示，该研磨工艺使介电层16的底部露出并使包括在晶片10的半导体芯片的不同部分被分隔开以使它们被介点层16基本上保持在一起。
在图2K中，在已经完成研磨至研磨水平30后，沿着与沟槽14的切割位置32切割晶片10，所述切割位置也是介电层16已经在晶片10的底侧露出的位置。因而，产生了包括多个切割半导体封装60的期望的最终产品。
图3A-3L示出了根据本发明的第三优选实施方案的制造工艺，其中在工艺期间，将金属触点56置于半导体芯片的接合焊盘12上。
在图3A中，提供了半导体晶片10，所述半导体晶片包括版单体芯片，所述半导体芯片包括含有接合焊盘12。晶片10被部分切割至小于晶片10的厚度的深度以形成沟槽14，如图3B所示。可使用标准刀片锯或通过激光加工形成此沟槽14。这些沟槽14优选地形成于半导体封装60在由工艺获得的最终产品中预被分隔开的位置处。
在形成沟槽14后，模制晶片10的顶侧，使得包括介电材料的介电层 16基本上覆盖晶片10的顶侧以及填充沟槽14(参见图3C)。
之后，通过去除介电层16的与接合焊盘12的位置相对应的某部分如通过钻穿包括在介电层16中的介电材料来露出接合焊盘12（参见图3D）。可使用激光加工来执行在介电层16上形成井18的此类钻孔，尽管也有可能采用去除介电材料的其它方式。
在图3E中，通过PVD或化学镀形成金属种子层46（其可包括薄的铜层）。金属种子层46覆盖介电层16的顶侧和侧壁以及接合焊盘12。
在图3F中，在位于介电层16上的金属种子层46的顶面但不包括井18的上方选择性地应用光致抗蚀层48。光致抗蚀层48用于显影金属电镀图案。
在图3G中，将可包括铜的另一薄的金属层50电镀于未被光致抗蚀层48覆盖的井18的各个表面上。与根据本发明的第二实施方案的工艺不同，薄的金属层50不填充整个井18但只覆盖接合焊盘12、井18的侧面以及介电层16的顶面上的小区域。
然后，如图3H所示，剥离光致抗蚀层48以显示位于介电层16的顶面上的露出的金属种子层52。然后，蚀刻露出的金属种子层46以显示介电层16的露出部分54，如图3I所示。在蚀刻掉露出的金属种子层后，仍将有覆盖接合焊盘12、井18的侧壁以及与位于介电层16的顶面上的井18相邻的小区域的剩余的金属层。
之后，将可包括焊料的金属触点56置于或附接于已经电镀有薄的金属层50的井18中。金属触点56用于形成将接合焊盘12电连接至介电层16的顶面的连接端子，并可以焊球的形式存在。
在露出的金属触点56已经粘附于接合焊盘上后，通过晶片研磨工艺去除晶片10的底侧的材料，直到晶片10的厚度减少至研磨水平30，所述研磨水平处于之前形成沟槽14的水平。如图3J所示，该研磨工艺使介电层16的底部露出并使包括在晶片10中的半导体芯片的不同部分被分隔开以使它们由介电层16基本上保持在一起。
在图3K中，在已经完成研磨至研磨水平30后，沿着与沟槽14相对应的切割位置32切割晶片10，所述切割位置也是与晶片10已经在介电层16的底侧露出的位置。因而，产生了包括多个切割半导体封装60的期望的最终产品。
图4A-4N示出了根据本发明的第四优选实施方案的制造工艺，其中在制造工艺的早期阶段模制半导体晶片的背面。
在图4A中，提供了半导体晶片10，所述半导体晶片包括半导体芯片，所述半导体芯片包括接合焊盘12。在图4B中，研磨晶片10（其不包括接合焊盘12）的背面或第二侧以使所得到的研磨过的晶片62具有在最终产品中所期望的厚度。然后，模制研磨的晶片62，使得研磨的晶片62的与第一侧相对的背面或第二侧以及晶片10的侧面覆盖有背衬模制化合物64（参见图4C），如环氧模制化合物。
在图4D中，模制的研磨的晶片62的与背部或第二侧相对的顶部或第一侧被部分切割至可延伸穿过研磨过的晶片10的深度，并且部分延伸至背衬模制化合物64中以形成沟槽66。因此，部分研磨的晶片62彼此分隔开，尽管它们仍通过背衬模制化合物64保持在一起。
在形成沟槽66后，模制晶片10的顶部或第一侧，使得包括介电材料的介电层68基本上覆盖研磨的晶片62的顶部或第一侧，以及填充沟槽66（参见图4E）。然后，通过去除某部分介电层68来在介电层68上形成通孔或井70以露出已被介电层68覆盖的接合焊盘12（参见图4F）。可通过在介电层68上进行的去除工艺如通过使用激光加工进行钻孔、选择性化学蚀刻、光致成像显影工艺或其他适宜的去除工艺来形成井70。
在图4G中，通过显影包括金属如铜、镍或钛的金属种子层72来金属化介电层68的顶侧和接合焊盘12。在图4H中，图案化的电镀抗蚀层74形成在金属种子层72的顶部。然后，将可包括铜的图案化的金属层76选择性地图案化到金属种子层72的顶侧上，如图4I所示。
在已形成图案化金属层76后，剥离电镀抗蚀层74以形成分隔开的部分图案化的金属层76（参见图4J）。之后，蚀刻掉介电层68上露出的金属种子层72的残余物以露出介电层68，如图4K所示。在图4L中，在将焊接触点置于图案化的金属层76（与接合焊盘12的位置对应）的球焊盘81上的准备过程中，将阻焊层80涂覆在图案化的金属层76上以覆盖未收到焊接触点的图案化的金属层76的剩余部分。然后，将可以焊接球82的形式存在的焊接触点在未被阻焊层80覆盖的区域附接至位于球焊盘81上，如图4M所示。
最终，沿着与沟槽66相对应的切割位置84切割研磨的晶片62。因而，产生了包括多个在半导体封装86的背侧具有背衬模制化合物64的切割半导体封装86。此背衬模制化合物64有助于提高每个切割半导体封装86的刚性。
应认识到，根据本发明的优选实施方案的制造工艺使最终半导体封装的端子触点直接形成到半导体芯片的接合焊盘上。这使得该制造工艺成本低廉，并且由于直接相互作用而产生更好地电学性能和更少的电学干扰。
除了特别描述的，此处描述的本发明易于变化、修改和/或添加，应理解的是本发明包括所有落在上述描述精神和范围内的此类变化、修改和/或添加。

Claims (20)

1.一种制造半导体封装的方法，其特征在于，包括以下步骤：
提供半导体晶片，所述半导体晶片包括位于所述晶片的第一侧上的多个接合焊盘；
用介电质材料覆盖所述晶片的第一侧以在接合焊盘上方形成介电层；
去除所述介电层与接合焊盘的位置相对应的部分以形成多个井，其中每个井被配置为在介电层的顶面与底面之间形成通孔以露出每个接合焊盘；
将导电材料沉积于所述井中以在所述接合焊盘与所述介电层的顶面之间形成导电层；之后切割所述半导体晶片以形成多个半导体封装。
2.根据权利要求1所述的方法，其特征在于，进一步包括步骤：在所述半导体晶片的第一侧上切割出沟槽，其中用介电质材料覆盖所述晶片的第一侧的步骤进一步包括用所述介电材料填充所述沟槽。
3.根据权利要求2所述的方法，其特征在于，所述切割半导体晶片的步骤进一步包括以下步骤：沿着沟槽将所述半导体封装分隔开。
4.根据权利要求2所述的方法，其特征在于，所述介电材料包括环氧模制化合物或旋涂材料。
5.根据权利要求2所述的方法，其特征在于，在切割所述半导体晶片之前，将所述半导体晶片的与第一侧相对的第二侧研磨至足以露出填充在每个沟槽中的介电材料的底部的水平。
6.根据权利要求5所述的方法，其特征在于，切割所述半导体晶片的切割宽度小于沟槽的宽度，使得介电材料粘附于已经被分隔开的所述半导体封装的侧壁上。
7.根据权利要求1所述的方法，其特征在于，所述去除部分介电层包括选自由钻孔、蚀刻和光致成像显影工艺所组成的组的去除工艺。
8.根据权利要求1所述的方法，其特征在于，在形成所述井之后，还包括步骤：在形成所述导电层之前，在所述介电材料的整个表面和接合焊盘上形成金属种子层。
9.根据权利要求8所述的方法，其特征在于，所述金属种子层包括由物理蒸镀或化学镀形成的薄层，并且其中所述薄层包括由铜、镍和钛组成的组中的金属。
10.根据权利要求8所述的方法，其特征在于，所述将导电材料沉积于井中的步骤包括将所述导电材料沉积于包括所述井的介电材料的整个表面的上方，之后，从所述介电材料中选择性地去除所述导电材料，使得仅保留部分沉积于井中的导电材料。
11.根据权利要求8所述的方法其特征在于，进一步包括步骤：用光致抗蚀层覆盖位于所述井外侧的所述介电材料的表面，之后，将更薄的金属层电镀于包括在所述井中的金属种子层的表面上。
12.根据权利要求11所述的方法，其特征在于，所述更薄的金属层覆盖所述接合焊盘和所述井的侧壁以及位于所述井外侧的介电材料的表面的小区域。
13.根据权利要求12所述的方法，其特征在于，所述将导电材料沉积于井中的步骤包括步骤：将金属触点附接于电镀有更薄的金属层的区域。
14.根据权利要求13所述的方法，其特征在于，所述金属触点包括焊球。
15.根据权利要求1所述的方法，其特征在于，进一步包括步骤：在所述接合焊盘上方形成所述介电材料之前，研磨所述半导体晶片的与所述第一侧相对的第二侧。
16.根据权利要求15所述的方法，其特征在于，进一步包括步骤：在所述接合焊盘上方形成所述介电层之前，用背衬模制化合物模制所述半导体晶片的第二侧。
17.根据权利要求16所述的方法，其特征在于，进一步包括步骤：在所述半导体晶片的第一侧上切割出沟槽，其中所述沟槽从所述第一侧延伸穿过所述半导体晶片并部分延伸至所述背衬模制化合物中，并且其中，所述用介电材料覆盖所述晶片的第一侧的步骤进一步包括用所述介电材料填充所述沟槽。
18.根据权利要求17所述的方法，其特征在于，在形成所述井之后，还包括步骤：在形成所述导电层之前，在所述介电材料的整个表面和接合焊盘上形成金属种子层。
19.根据权利要求18所述的方法，其特征在于，进一步包括步骤：在形成所述导电层之前，在所述金属种子层上形成图案化的金属层。
20.根据权利要求19所述的方法，其特征在于，进一步包括将阻焊层涂覆在所述图案化的金属层上，并且其中所述将导电材料沉积于井中的步骤包括之后将焊接触点附接于未涂覆所述阻焊层的区域。
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