TW200743197A - Under bump metallurgy structure of package and method of the same - Google Patents
Under bump metallurgy structure of package and method of the sameInfo
- Publication number
- TW200743197A TW200743197A TW095117168A TW95117168A TW200743197A TW 200743197 A TW200743197 A TW 200743197A TW 095117168 A TW095117168 A TW 095117168A TW 95117168 A TW95117168 A TW 95117168A TW 200743197 A TW200743197 A TW 200743197A
- Authority
- TW
- Taiwan
- Prior art keywords
- under bump
- package
- same
- bump metallurgy
- opening
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
An under bump metallization structure comprises a die having a pad disposed thereon. A dielectric layer having an opening is formed therein over the die. A barrier layer is formed within the opening and a multilayer metal layer over the barrier layer. The barrier layer and/or the multilayer have an extending part that extends outside the opening of the dielectric layer and on the upper of thereon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095117168A TW200743197A (en) | 2006-05-15 | 2006-05-15 | Under bump metallurgy structure of package and method of the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095117168A TW200743197A (en) | 2006-05-15 | 2006-05-15 | Under bump metallurgy structure of package and method of the same |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200743197A true TW200743197A (en) | 2007-11-16 |
Family
ID=57914263
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095117168A TW200743197A (en) | 2006-05-15 | 2006-05-15 | Under bump metallurgy structure of package and method of the same |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW200743197A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI449141B (en) * | 2011-10-19 | 2014-08-11 | Richtek Technology Corp | Wafer level chip scale package device and manufacturing method thereof |
TWI469296B (en) * | 2011-10-19 | 2015-01-11 | Richtek Technology Corp | Wafer level chip scale package device and manufacturing method thereof |
TWI633597B (en) * | 2016-11-30 | 2018-08-21 | 新加坡商先進科技新加坡有限公司 | Method for manufacturing wafer-level semiconductor packages |
-
2006
- 2006-05-15 TW TW095117168A patent/TW200743197A/en unknown
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI449141B (en) * | 2011-10-19 | 2014-08-11 | Richtek Technology Corp | Wafer level chip scale package device and manufacturing method thereof |
TWI469296B (en) * | 2011-10-19 | 2015-01-11 | Richtek Technology Corp | Wafer level chip scale package device and manufacturing method thereof |
TWI633597B (en) * | 2016-11-30 | 2018-08-21 | 新加坡商先進科技新加坡有限公司 | Method for manufacturing wafer-level semiconductor packages |
US10115579B2 (en) | 2016-11-30 | 2018-10-30 | Asm Technology Singapore Pte Ltd | Method for manufacturing wafer-level semiconductor packages |
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