TWI587357B - 積體電路封裝及製造方法 - Google Patents

積體電路封裝及製造方法 Download PDF

Info

Publication number
TWI587357B
TWI587357B TW104113834A TW104113834A TWI587357B TW I587357 B TWI587357 B TW I587357B TW 104113834 A TW104113834 A TW 104113834A TW 104113834 A TW104113834 A TW 104113834A TW I587357 B TWI587357 B TW I587357B
Authority
TW
Taiwan
Prior art keywords
conductive
substrate
capacitor
region
pair
Prior art date
Application number
TW104113834A
Other languages
English (en)
Other versions
TW201604923A (zh
Inventor
良 王
宏 沈
雷傑許 卡克爾
Original Assignee
英凡薩斯公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英凡薩斯公司 filed Critical 英凡薩斯公司
Publication of TW201604923A publication Critical patent/TW201604923A/zh
Application granted granted Critical
Publication of TWI587357B publication Critical patent/TWI587357B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/115—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1205—Capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/16153—Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

積體電路封裝及製造方法
本案一般係關於利用「操作晶圓(handle wafer)」來製造積體電路封裝，且更具體地，係關於製造此種封裝的操作晶圓內的離散的電性部件，例如電容器。
積體電路(IC)封裝的「晶圓級」或「晶圓規模」生產近年來已經激增，主要是由於此種生產技術提供的經濟規模，以及所產生的封裝的尺寸與成本的相應減少。
41IC封裝以及其製造方法的範例可例如在下述中找到：H.Shen等人所共同擁有的美國專利申請案第14/214,365號，其申請於2014年3月14日，且標題為「Integrated Circuits Protected by Substrates with Cavities,and Methods of Manufacture(由具有空腔的基板保護之積體電路以及製造方法)」，其全部揭示內容在此以引用之方式併入。
在此種封裝的許多可能實施例的僅一者中，從包含許多類似封裝的兩晶圓的夾設結構所切割或「單分」的封裝可包含配線基板晶圓的 一部分，有時稱為「中介層晶圓」，其具有上表面，上表面上設置有一或更多個半導體晶粒或晶片(其可為已封裝或未封裝的)，每一半導體晶粒或晶片包含一或更多個積體電路(IC)。中介層可包含導電線路的圖案，例如，以「再分佈層(RDL)」的形式，IC係多樣地導電連接至導電線路。中介層也可包含離散的電性部件，例如「溝槽電容器」，溝槽電容器形成於其表面上或其厚度內。
IC封裝可進一步包含「操作晶圓」的一部分，其包含在其下表面中的一或更多個空腔。操作晶圓的下表面可接合至中介層的上表面，使得半導體晶粒保護性地設置於操作晶圓的空腔內。操作晶圓因此不僅提供保護性環境給晶粒，也提供方便的機制來「操作」較薄的中介層晶圓(例如，大約5X10-6米(5μm)厚的量級)，或者用於在薄化操作期間(例如，藉由化學機械平坦化(CMP))固持中介層晶圓。
然而，當此種封裝的中介層晶圓製造成實質上薄的時，則會產生實際的問題，因為這限制了離散的電性部件(例如電容器)可建置至中介層的厚度中的垂直高度，且因此限制了其最大表面積或電容值。
因此，對於克服先前技術的上述與其他問題的方法與設備存在著長期且尚未滿足的需求。
根據本發明的實施例，提供方法，用於製造積體電路(IC)封裝的第一基板(例如，操作晶圓)內的離散的電性部件(亦即，電容器)，第一基板也包含空腔，用於容納安裝在相關的第二基板(例如，中介層晶 圓)上的積體電路晶粒或封裝。該新穎方法促成體積的有效率使用，且因此，減少了半導體封裝的尺寸以及最大化離散的部件的尺寸與性能(例如，電容值)。
在一實施例中，一種用於製造一積體電路封裝的方法包含：提供一操作晶圓，該操作晶圓具有一第一區域與一第二區域，該第一區域至少部分界定該操作晶圓內的一空腔，該空腔界定該第二區域。一電容器形成於該操作晶圓的該第一區域中。該電容器具有一對電極，每一電極係導電性耦接至一對導電接墊的一對應一者。這些接墊的至少一者係設置於該操作晶圓的該第一區域的一下表面上。也提供中介層。該中介層具有上表面，該上表面上設置有一導電接墊與一半導體晶粒。該半導體晶粒具有積體電路(IC)形成於其中，該積體電路係導電性耦接至設置於該中介層內或上的一再分佈層(RDL)。該操作晶圓的該下表面係接合至該中介層的該上表面，使得該半導體晶粒設置於該空腔內或之下，且該操作晶圓的該導電接墊係以一金屬對金屬的接合而導電性接合至該中介層的該導電接墊。
在另一實施例中，一種積體電路封裝包含：一第一基板，該第一基板具有一第一區域與一第二區域，該第一區域至少部分界定該基板內的一空腔，該空腔界定第二區域。一電容器設置於該第一基板的該第一區域中。該電容器包含一層介電質係夾設於兩導電板之間。兩導電板的每一導電板係導電性耦接至一對導電接墊的一對應一者，該對導電接墊的至少一者係設置於該第一區域中的該第一基板的該下表面上。提供一第二基板，該第二基板具有一上表面，該上表面上設置有一導電接墊與一半導體 晶粒。該半導體晶粒具有一積體電路形成在其中，該積體電路係導電性耦接至設置於該第二基板內或上的一再分佈層(RDL)。該第一基板的該下表面係接合至該第二基板的該上表面，使得該半導體晶粒設置於該空腔內或之下，且該第一基板的該導電接墊係以一金屬對金屬的接合而導電性接合至該第二基板的該導電接墊。
在又另一實施例中，該第二基板可進一步包含設置於其上表面之下的至少一電容器，該電容器具有一對導電板，該對導電板係導電性耦接至一對導電接墊的對應一者，該對導電接墊的至少一者包含設置於該第二基板的該下表面上的該至少一導電接墊，使得該第一基板的該電容器的該對導電板的一者係電性耦接至該第二基板的該電容器的該對導電板的一者，且該第一基板的該電容器設置於該第二基板的該電容器之上並且堆疊對準於該第二基板的該電容器。
本發明的範圍由下文所附的申請專利範圍來界定，其以引用之方式併入本章節。用於製造IC封裝的操作晶圓內的電性部件之新穎方法與設備的特徵與優點的更完整理解將藉由考量呈現於下之其一些範例實施例的詳細說明而提供給本領域中熟習技藝者，特別是如果此種考量是結合了簡短敘述於下的所附圖式，其中相似的元件符號係用於識別其個別圖式的一或更多者中所例示的相似的元件。
10‧‧‧封裝
12‧‧‧操作晶圓
14‧‧‧中介層
16‧‧‧第一區域
18‧‧‧第二區域
20‧‧‧空腔
22‧‧‧上表面
24‧‧‧晶粒
26‧‧‧凸塊
28‧‧‧再分佈層(RDL)
30‧‧‧下表面
32‧‧‧凸塊
34‧‧‧通孔
36‧‧‧導電接墊
38‧‧‧下表面
100‧‧‧封裝
112‧‧‧操作晶圓
114‧‧‧中介層
116‧‧‧第一區域
118‧‧‧第二區域
120‧‧‧空腔
122‧‧‧上表面
124‧‧‧晶粒
128‧‧‧RDL
130‧‧‧下表面
132‧‧‧凸塊
134‧‧‧通孔
138‧‧‧下表面
140‧‧‧電容器
142‧‧‧凹部
144‧‧‧桿部或脊部(第一電極或板)
146‧‧‧介電質層
148‧‧‧第二導電層
150‧‧‧上表面
152‧‧‧導電接墊
154‧‧‧導電接墊
156‧‧‧導電通孔
158‧‧‧體積
160‧‧‧通道
300‧‧‧封裝
312‧‧‧操作晶圓(基板)
314‧‧‧中介層(基板)
316‧‧‧第一區域
318‧‧‧第二區域
324‧‧‧晶粒
340‧‧‧電容器
344‧‧‧第一導電層
346‧‧‧介電質層
348‧‧‧第二導電層(第二電極或板)
358‧‧‧體積
362、364‧‧‧導電接墊
第1圖為美國專利申請案第14/214,365號所揭示的一種IC封裝10實施例 的垂直剖視圖；第2圖為本案較佳實施例之積體電路封裝垂直剖視圖；第3圖為本案較佳實施例之積體電路封裝另一垂直剖視圖；及第4圖為第3圖圓圈部分的放大圖。
本案提供用於製造半導體封裝的方法的實施例，其中電性部件(亦即，金屬-絕緣體-金屬(MIM,metal-insulator-metal)電容器係製造於第一基板(例如，操作晶圓)的選定區域內，第一基板包含空腔，用於容納安裝在第二、相關基板(例如，中介層晶圓)上的積體電路晶粒或封裝。該方法使封裝體積的使用更有效率，進而使半導體封裝尺寸減小及/或功能增強。
第1圖為上述美國專利申請案第14/214,365號所揭示的一種IC封裝10實施例的垂直剖視圖，且本發明的方法與設備可有應用至該申請案。如其所述，封裝10包含第一基板(或「操作晶圓」12)與第二基板(或「中介層」14)的「夾設結構」。操作晶圓12包含至少一「第一區域」16與至少一「第二區域」18。第一區域16至少部分地界定操作晶圓12內的空腔20，且空腔20界定第二區域18。在第1圖的特定範例IC封裝10中，操作晶圓12包含至少三個第一區域16、兩個第二區域18、與兩個對應的空腔20。然而，應理解到，操作晶圓12可包含任何數量的第一區域16與相關的第二區域18及空腔20。
在第1圖的特定範例IC封裝10中，第二基板或中介層14包含 上表面22，其中半導體晶粒或晶片24設置在其上。晶粒24具有使用熟知的IC製造技術而形成在其主動表面中的積體電路(IC)。晶粒24可包含例如所謂的「覆晶」或「控制塌陷高度晶片連接(controlled collapse chip connection)」(「C4」)的IC封裝，其藉由例如複數個回焊的焊料凸塊26而導電性耦接至形成在再分佈層(RDL)28中的對應導電接墊，再分佈層(RDL)28可設置在中介層14的上及/或下表面22、30的一者、另一者、或兩者上，或者替代地或額外地，部分或完全地設置在中介層14的厚度內。
在第1圖的特定範例實施例中，RDL 28的導電接墊與線路係藉由複數個對應的垂直互連接取連接(Vertical Interconnect Access connections)或「通孔」34而導電性耦接至中介層14的下表面30上所設置的導電接墊上所設置的焊料球或凸塊32，「通孔」34包含通過中介層14的垂直孔，其隨後使用熟知的光微影技術來內部金屬化及/或填充金屬。
焊料凸塊32可用來安裝IC封裝10並且導電性連接其中的晶粒24的IC至例如傳統的IC封裝安裝配置中下方的印刷電路板(PCB-未例示)的導電線路。此外，RDL 28內所選擇的導電線路可耦接至設置在中介層14的上表面22上的導電接墊36，導電接墊36可作為接觸墊，用於測試IC晶粒24的功能的應用，例如測試探針。當然，其他已知的導電耦接與安裝機構，例如針柵陣列(PGA)與對應的插座都可用來耦接且安裝IC晶粒24至中介層14，及/或耦接且安裝中介層14至相關的PCB(未例示)。
第一基板(或操作晶圓12)以及第二基板(或中介層14)可隨意由各種合適的材料製成，包含半導體材料(例如，矽(Si)、鍺(Ge)、與砷化鎵(GaAs))、許多類型的玻璃或陶瓷、許多類型的聚合物(例如， 環氧樹脂)、或「合成」材料，如果需要的話，可用纖維(例如，玻璃纖維)來加強這些材料。
IC封裝10的「夾設」係在封裝的製造期間，藉由將操作晶圓12的下表面38接合至中介層14的上表面22而實施。這可以用多種方式來實施，包含黏著劑接合以及藉由金屬對金屬的接合，其係在較大的力與較高的溫度之下藉由將操作晶圓12與中介層14壓縮在一起而達成。
如同上面討論的，在一些情況中，吾人希望的是，製造離散的電性部件(例如，電容器)於中介層14上或內，亦即，在其上表面22上或設置在其中的凹部內。例如，傳統的「二維」(2D)金屬-絕緣體-金屬(MIM)電容器可如此形成在中介層14的上表面上：藉由設置合適的金屬與介電質材料的交替層於其上，並且導電性耦接金屬層至導電接墊，以界定電容器的電極或板。類似的配置可實施於中介層14的上表面22中所形成的「盲」溝槽或凹部中，且此種電容器有時稱為「2D」電容器，因為所有其他因素都相同時，它們的電容值通常為其MIM層的面積(亦即，其長度乘以其寬度)的函數。
類似地，所謂的「3D」電容器可如此製造在中介層14上或中：藉由在電容器的界定中包含第三維度(亦即，高度)，藉由建構一或更多個直立的結構(例如「桿部」或「脊部」)於中介層14的上表面22上，或者替代地，於其中設置的凹部的底部上，然後設置交替的MIM層於上述的直立結構的表面之上。所有其他因素都相同時，此種3D電容器的電容值為其長度乘以其寬度乘以其高度之函數。亦即，MIM層所設置於其上的直立結構實質上用以增加該等層的面積，且因此，增加此種裝置的電容值，相 較於2D電容器來說。
然而，如同在第1圖中可看見的，可製造電性部件(例如，上述的電容器)於其上之中介層14的上表面22上的面積實質上有限，至少部分是因為操作晶圓12的存在。因此，雖然具有空腔的操作晶圓12對於晶粒24的保護與薄中介層晶圓12的支撐與處理是個好方法，但可看出，操作晶圓12的第一區域16(有時稱為「基座」或「支柱」)必須足夠高而滿足設置在空腔20內的IC晶粒或封裝24的高度，且足夠寬來滿足在晶圓薄化處理期間(例如，CMP處理)充分地支撐中介層晶圓12。此外，當中介層14做得較薄時(例如，50μm厚的量級)，即使嵌入在中介層14內的3D電容器在其中所獲得的最大電容值亦將受限，因為中介層14的薄度限制了上述的垂直結構的高度，且因此，限制了電容器的MIM層的表面積。
經發現，這是可行的且有利的：在操作晶圓12的第一區域16的其他「未利用的」體積內製造離散的電性部件，例如電阻器、電感器、發光二極管(LED)、偵測器、感測器、致動器、微機電(MEMS)裝置，且具體地，上述的電容器，且然後在兩個晶圓的接合期間導電性耦接它們至例如中介層14的RDL 28。
第2圖的垂直剖視圖為積體電路封裝100的範例實施例，其併入操作晶圓112的第一區域116中的複數個電容器140。第1與2圖的比較可看出，第2圖的特定範例IC封裝100包含第1圖的IC封裝10的許多相同特徵，包含第一基板(或操作晶圓112)與第二基板(或中介層114)。
如第1圖實施例包含三個第一區域16、兩個第二區域18、與兩個對應的空腔20，第2圖的特定操作晶圓112亦包含任何實用數量的第一 區域116與相關的第二區域118及空腔120，空腔120用於容納一或更多個IC封裝或晶粒124。
範例第二基板(或中介層114)包含上表面122，上表面122具有兩個半導體晶粒、晶片或封裝124設置在其上，且如同上述，晶粒124各自具有至少一IC形成在其表面中。範例中介層114也包含RDL 128，晶粒124多樣地導電性耦接至RDL 128，且RDL 128接著藉由對應的通孔134而導電性互連至設置在中介層114的下表面130的焊料凸塊132，及/或藉由RDL 128的導電線路而導電性互連至設置在中介層114的上表面122上的導電接墊136。
如同上述，在製造期間，操作晶圓112的下表面138係接合至中介層114的上表面122，使得晶粒124設置在空腔120的對應一者之下或內。然而，在第2圖的範例IC封裝100中，在此接合發生之前，如同上面討論的，至少一電性部件(亦即，MIM電容器140)形成於操作晶圓112的第一區域116的至少一區域的其他未利用體積中。
在一個可能的實施例中，電容器140的形成可開始於製造凹部142，凹部142具有在操作晶圓112的第一區域116的選擇一者的下表面138中的內表面。如同上面討論的，在一些實施例中，凹部142可製造成包含形成於凹部142的底部上的至少一垂直結構，例如直立的桿部或脊部144，或者替代地，此種桿部或脊部144的陣列，以實質上增加電容器140的MIM層的面積。桿部或脊部144可具有較高的長寬比，並且可具有例如矩形的水平橫截面。在一些實施例中，凹部142與桿部或脊部144可同時如此製造：藉由使用熟知的光微影技術，來圖案化所選擇的第一區域116的下表面138， 且然後蝕刻凹部142以及其中的直立的桿部或脊部144至第一區域116的下表面中。
接著產生第一導電層在凹部142的內表面上或中，包含直立的桿部或脊部144上或中，以界定電容器140的第一電極或板。在半導體(例如矽(Si))製作操作晶圓112時，第一導電層144可利用適當的摻雜劑，藉由摻雜形成有凹部的整個第一區域116而產生。例如，如果操作晶圓112包含單晶或輕度p型摻雜的矽，則整個選擇的第一區域116可摻雜有n型摻雜劑，使凹部142的內表面與其中直立的桿部或脊部144可導電。替代地，僅薄層的摻雜材料可形成在凹部142的內部與直立的桿部或脊部144的個別表面中，以使其可導電，並且藉此形成電容器140的第一電極或板。在任一情況中，摻雜可使用例如已知的擴散摻雜或離子佈植摻雜技術來實施。
在另一個可能的實施例中，電容器140的第一電極之形成如下：藉由在凹部142的內表面上與直立的桿部或脊部144的表面上沉積第一層金屬。金屬可包含例如鉭(Ta)、銅(Cu)、鈦(Ti)、氮化鈦(TiN)、銀(Ag)、金(Au)、鋁(Al)、鉻(Cr)、鈀(Pd)、鉑(Pt)、釕(Ru)、鋨(Os)、及/或銠(Rh)的一或更多者，並且可使用例如原子層沉積(ALD)、化學汽相沉積(CVD)、無電電鍍及/或濺鍍技術之一或更多者來沉積於這些表面上。
在產生第一導電層(亦即，電容器140的第一電極或板144)之後，其整個表面塗覆有介電質材料層146，以形成MIM電容器140的「I」或「絕緣體」。介電質層146可包含例如聚對二甲苯(Parylene)、氧化矽(SiO2)、氧化鉿(HfO2)、五氧化二鉭(Ta2O5)、二氧化鋯(ZrO2)、氧化 釔(Y2O3)、氧化鑭(La2O3)、二氧化鈦(TiO2)、或鈦酸鍶(SrTiO3)，並且可藉由原子層沉積(ALD)、化學汽相沉積(CVD)、無電電鍍及/或濺鍍技術來沉積於第一電極或板144上的層中。
電容器140的MIM「夾設結構」係藉由沉積第二導電層148於介電質層146的表面上而完成。第二導電層148包含電容器140的第二電極或板，且類似於第一導電層144，可包含金屬，例如鉭(Ta)、銅(Cu)、鈦(Ti)、氮化鈦(TiN)、銀(Ag)、金(Au)、鋁(Al)、鉻(Cr)、鈀(Pd)、鉑(Pt)、釕(Ru)、鋨(Os)、及/或銠(Rh)，並且可使用例如原子層沉積(ALD)、化學汽相沉積(CVD)、無電電鍍及/或濺鍍技術來沉積於介電質層146的表面上。
如同本領域中熟習技藝者將理解的，電容器140的MIM「夾設結構」並不限於一個絕緣層146與兩個導電層144、148，反倒是，可具有多個交替的介電質與導電層，用來增加電容器140的電容值。實際上，這些額外的交替層的數量主要取決於凹部142中的直立的桿部或脊部144的「間距」或之間的間隔。
在多數應用中通常希望，導電性耦接電容器140的每一電極或板144、148至設置在操作晶圓112的下表面138上的對應的導電接墊，使得當操作晶圓112接合至中介層114時，每一接墊同時導電性接合至中介層114的RDL 128中的對應的導電接墊，藉此將電容器140電性耦接至也導電性耦接至RDL 128的一或更多個電路(例如，半導體晶粒124的IC)。例如，操作晶圓112的下表面138上的電容器140的導電接墊與中介層114的上表面122上的對應的接墊可塗覆或電鍍有相同的金屬，例如鋁(AL)、金(Au) 或銅(Cu)，使得當操作晶圓112在升高的溫度與壓力之下接合至中介層114時，電容器140的導電接墊係以鋁對鋁(AL-to-AL)、金對金(Au-Au)、或銅對銅(Cu-Cu)的金屬接合而導電性耦接至中介層114的對應接墊。
然而，在一些實施例中，導電性耦接電容器140的至少一電極或板144、148至操作晶圓112的上表面150，以參與例如下面更詳細討論的那種「堆疊」配置。
在第2圖的特定範例實施例中，可看出，界定電容器140的電極或板之第二導電層148的整個下表面包含設置在操作晶圓112的下表面138上的導電接墊152，而藉由上面討論的那種導電通孔156(形成通過操作晶圓112的上表面150)，包含電容器140的第二電極或板之第一導電層144係導電性耦接至設置在操作晶圓112的上表面150上的導電接墊154。
在一些實施例中，「頭部空間」或空體積158可界定在空腔120的內表面與半導體晶粒或晶粒封裝124(當它們設置在其中時)的外表面之間。如同第2圖所示，在一些實施例中，利用適當的填料來填充這些體積158，例如環氧樹脂或熱界面材料，以加強IC封裝100內的晶粒或晶粒封裝124的安裝及/或提供晶粒或封裝124至圍繞封裝10的周圍環境之間的加強的熱轉移路徑。如同第2圖所示，在一個可能的實施例中，這可如此實施：藉由形成一或更多個通道160於連通體積158與操作晶圓112的外表面(例如，其上表面150)之間的操作晶圓112中，且然後通過通道160注入填料至體積158中。類似的通道可額外或替代地延伸於相鄰的空腔之間或空腔與操作晶圓的側邊緣之間，以容納材料的流動。
如同第3與4圖所示，在一些實施例中，形成電容器340於第 一基板(或操作晶圓312)與第二基板(或中介層314)兩者中，且然後在上述的晶圓接合操作期間以堆疊的配置將它們導電性耦接至彼此。
在第3與4圖的範例IC封裝300中，電容器340可各自包含例如T.Wang等人在美國專利號第6,613,672號中所述的一種MIM「通孔」或「溝槽」電容器340。針對下面討論的原因，這些較佳地包含矽通孔(TSV,Through Silicon Via)或溝槽形成於個別的基板312、314中，個別的基板312、314包含其上或其內形成有第一導電層344(其包含電容器340的第一電極或板)的內表面。如同第1圖與第2圖，一或更多IC封裝或晶粒324係封裝在體積358裡。如同上述，第一導電層344可包含形成在通孔或溝槽的內表面中的適當摻雜的半導體層，或者替代地，可包含沉積在該表面上的一層金屬。
如同上述，「I」或介電質層346可形成在第一導電層344的內表面之上，且介電質層346內的中空空間然後可填充有例如銅(Cu)的填料，以形成包含電容器340的第二電極或板之第二導電「層」348。
類似第2圖的IC封裝100的方式，電容器340的第一導電層344或電極通過相關的基板312或314的下表面中的開口而曝露，且導電性耦接至設置於其上的對應的導電接墊362，而電容器340的第二電極或板348(亦即，銅填料)係導電性耦接至設置在相關的基板312或314的上表面上的導電接墊364。此外，相關的基板312與314的個別電容器340可位於其個別的基板內，使得當第一與第二基板312與314以金屬對金屬而彼此接合時，第一基板312的電容器340將設置於第二基板314的電容器340的對應一者之上，並且堆疊對準於第二基板314的電容器340的對應一者，如同第3與4圖所示，且另外，第一基板312的電容器340的第一電極或板344將以金屬對金 屬的接合而導電性耦接至第二基板314的電容器340的對應一者的第二電極或板348的個別一者，如同上述。如圖第1圖及第2圖，可知操作晶圓可包含任何特別數量的第一區域316及相關的第2區域318。
有鑑於前面的詳細敘述，本領域中熟習技藝者應清楚到，許多修改、替換與變化都可對本案的IC封裝的方法與材料做出，且因此，本案的範圍不應限於本文中所述與所示的特定實施例的範圍，因為它們僅藉由其一些範例的方式，但是反而，應該完全等同於此後所附的申請專利範圍與其功能均等物的範圍。
300‧‧‧封裝
312‧‧‧操作晶圓(基板)
314‧‧‧中介層(基板)
316‧‧‧第一區域
318‧‧‧第二區域
324‧‧‧晶粒
340‧‧‧電容器
358‧‧‧體積
362‧‧‧導電接墊
364‧‧‧導電接墊

Claims (20)

  1. 一種用於製造一積體電路封裝的方法，該方法包含：提供一操作晶圓(Handle Wafer)，該操作晶圓具有一第一區域與一第二區域，該第一區域至少部分界定該操作晶圓內的一空腔，該空腔界定該第二區域；形成一電容器(Capacitor)於該操作晶圓的該第一區域中，該電容器具有一對電極，每一電極係導電性耦接至一對導電接墊的一對應的導電接墊，該對導電接墊的至少一者係設置於該第一區域中的該操作晶圓的一下表面上；提供一中介層(Interposer)，該中介層具有一上表面，該上表面上設置有一導電接墊與一半導體晶粒，該半導體晶粒具有一積體電路(IC)形成在其中，該IC係導電性耦接至設置於該中介層內或上的一再分佈層(RDL)；及接合(Bonding)該操作晶圓的該下表面至該中介層的該上表面，使得該半導體晶粒設置於該操作晶圓的該空腔內或之下，且該操作晶圓的該至少一導電接墊係以一金屬對金屬的接合而導電性接合至該中介層的該導電接墊。
  2. 如申請專利範圍第1項之方法，其中該操作晶圓的該等導電接墊的另一者係設置於其一上表面上。
  3. 如申請專利範圍第1項之方法，其中形成該電容器包含：製造一凹部於該第一區域的一下表面中，該凹部具有一內表面；產生一第一導電層於該凹部的該內表面上或中；利用一介電質層來塗覆該第一導電層；沉積一第二導電層於該介電質層上；及電性耦接該第一與第二導電層的每一者至該等導電接墊的一對應導電接墊。
  4. 如申請專利範圍第3項之方法，其中形成該電容器包含：形成至少一直立的桿部或脊部於該凹部的一底部上。
  5. 如申請專利範圍第3項之方法，其中形成該電容器包含：形成一陣列的桿部或脊部於該凹部的一底部上。
  6. 如申請專利範圍第3項之方法，其中產生該第一導電層包含：摻雜該操作晶圓的該第一區域、摻雜該凹部的該內表面、或沉積一第一金屬層於該凹部的該內表面上。
  7. 如申請專利範圍第6項之方法，其中該沉積包含：一或更多的原子層沉積(ALD)、化學汽相沉積(CVD)、無電電鍍及/或濺鍍。
  8. 如申請專利範圍第3項之方法，其中利用一層介電質之該第一導電層的該 塗覆及該第二導電層的該沉積二者之中，至少有一者包含：一或更多的原子層沉積(ALD)、化學汽相沉積(CVD)、汽相沉積及/或濺鍍。
  9. 如申請專利範圍第1項之方法，其中該半導體晶粒與該空腔的內壁之間界定一體積，且該方法進一步包含：形成一通道於該操作晶圓中，該通道連通於該體積與該操作晶圓的一外表面之間；及通過該通道注入一填料至該體積中。
  10. 如申請專利範圍第9項之方法，其中該填料包含一環氧樹脂或一熱界面材料。
  11. 如申請專利範圍第1項之方法，進一步包含：形成一電容器於該中介層的該上表面之下，該電容器具有一對電極，該對電極電性耦接至一對導電接墊的對應導電接墊，該對導電接墊的至少一者包含設置在該中介層的該上表面上的該導電接墊，藉此，該操作晶圓的該電容器的該對電極的一電極係電性耦接至該中介層的該電容器的該對電極的一電極。
  12. 一種根據申請專利範圍第1項的該方法所製造的積體電路封裝。
  13. 一種根據申請專利範圍第11項的該方法所製造的積體電路封裝。
  14. 一種積體電路封裝，包含：一第一基板，該第一基板具有一第一區域與一第二區域，該第一區域至少部分界定該基板內的一空腔，該空腔界定該第二區域；一電容器，該電容器形成於該第一基板的該第一區域中，該電容器包含一層介電質係夾設於一對導電板之間，每一導電板係導電性耦接至一對導電接墊的一對應導電接墊，該對導電接墊的至少一者係設置於該第一區域中的該第一基板的該下表面上；及一第二基板，該第二基板具有一上表面，該上表面上設置有一導電接墊與一半導體晶粒，該半導體晶粒具有一積體電路(IC)形成在其中，該IC係導電性耦接至設置於該第二基板內或上的一再分佈層(RDL)，其中該第一基板的該下表面係接合至該第二基板的該上表面，使得該半導體晶粒設置於該空腔之內或之下，且該第一基板的該至少一導電接墊係以一金屬對金屬的接合而導電性接合至該第二基板的該導電接墊。
  15. 如申請專利範圍第14項之積體電路封裝，其中該第一與第二基板的至少一者包含一半導體、玻璃、陶瓷、或一聚合物。
  16. 如申請專利範圍第14項之積體電路封裝，其中該對導電板的至少一者包含：一摻雜的半導體、鉭(Ta)、銅(Cu)、鈦(Ti)、氮化鈦(TiN)、銀(Ag)、金(Au)、鋁(Al)、鉻(Cr)、鈀(Pd)、鉑(Pt)、釕(Ru)、鋨(Os)、或銠(Rh)。
  17. 如申請專利範圍第14項之積體電路封裝，其中該介電質包含聚對二甲苯(Parylene)、氧化矽(SiO2)、氧化鉿(HfO2)、五氧化二鉭(Ta2O5)、二氧化鋯(ZrO2)、氧化釔(Y2O3)、氧化鑭(La2O3)、二氧化鈦(TiO2)、或鈦酸鍶(SrTiO3)。
  18. 如申請專利範圍第14項之積體電路封裝，其中該第一基板的該第一區域包含一摻雜的半導體。
  19. 如申請專利範圍第14項之積體電路封裝，其中該金屬對金屬的接合包含：一鋁對鋁(AL-to-AL)的接合、一金對金(Au-Au)的接合、或一銅對銅(Cu-Cu)的接合。
  20. 如申請專利範圍第14項之積體電路封裝，其中：該第二基板進一步包含設置於其上表面之下的一電容器，該電容器具有一對導電板，每一導電板係導電性耦接至一對導電接墊的一對應導電接墊，該對導電接墊的至少一者包含設置於該第二基板的該上表面上的該導電接墊，藉此該第一基板的該電容器的該對導電板的一者係電性耦接至該第二基板的該電容器的該對導電板的一者，及該第一基板的該電容器設置於該第二基板的該電容器之上並且堆疊對準(Stacked alignment)於該第二基板的該電容器。
TW104113834A 2014-05-02 2015-04-29 積體電路封裝及製造方法 TWI587357B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/268,899 US9165793B1 (en) 2014-05-02 2014-05-02 Making electrical components in handle wafers of integrated circuit packages

Publications (2)

Publication Number Publication Date
TW201604923A TW201604923A (zh) 2016-02-01
TWI587357B true TWI587357B (zh) 2017-06-11

Family

ID=53180826

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104113834A TWI587357B (zh) 2014-05-02 2015-04-29 積體電路封裝及製造方法

Country Status (4)

Country Link
US (5) US9165793B1 (zh)
KR (1) KR20160149211A (zh)
TW (1) TWI587357B (zh)
WO (1) WO2015168222A1 (zh)

Families Citing this family (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696785A (en) 1994-10-11 1997-12-09 Corning Incorporated Impurity getters in laser enclosures
US10026720B2 (en) * 2015-05-20 2018-07-17 Broadpak Corporation Semiconductor structure and a method of making thereof
US9941195B2 (en) * 2009-11-10 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical metal insulator metal capacitor
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
US9412806B2 (en) 2014-06-13 2016-08-09 Invensas Corporation Making multilayer 3D capacitors using arrays of upstanding rods or ridges
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
US9824951B2 (en) 2014-09-12 2017-11-21 Qorvo Us, Inc. Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
US10085352B2 (en) * 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10121718B2 (en) 2014-11-03 2018-11-06 Qorvo Us, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US10306777B2 (en) * 2014-12-15 2019-05-28 Bridge Semiconductor Corporation Wiring board with dual stiffeners and dual routing circuitries integrated together and method of making the same
US9287348B1 (en) * 2015-04-14 2016-03-15 Honeywell International Inc. Devices, systems, and methods for ion trapping
US9960145B2 (en) 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
DE102015205384A1 (de) * 2015-03-25 2016-09-29 Robert Bosch Gmbh Kapazitives MEMS-Sensorelement mit Bondpads zur elektrischen Kontaktierung der Messkondensatorelektroden
US20160343604A1 (en) 2015-05-22 2016-11-24 Rf Micro Devices, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
KR101672640B1 (ko) * 2015-06-23 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US10304813B2 (en) * 2015-11-05 2019-05-28 Innolux Corporation Display device having a plurality of bank structures
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
KR102614960B1 (ko) * 2016-02-29 2023-12-19 스몰텍 에이비 나노구조 에너지 저장장치 및 전자 디바이스
US10741486B2 (en) 2016-03-06 2020-08-11 Intel Corporation Electronic components having three-dimensional capacitors in a metallization stack
CN105789218A (zh) * 2016-03-10 2016-07-20 京东方科技集团股份有限公司 一种基板、其制作方法及显示装置
JP2017175000A (ja) * 2016-03-24 2017-09-28 ローム株式会社 電子部品およびその製造方法、ならびに、インターポーザ
US10090262B2 (en) 2016-05-09 2018-10-02 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
KR102019352B1 (ko) * 2016-06-20 2019-09-09 삼성전자주식회사 팬-아웃 반도체 패키지
US10079196B2 (en) 2016-07-18 2018-09-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
WO2018031994A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
WO2018031999A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10109550B2 (en) 2016-08-12 2018-10-23 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
KR102527409B1 (ko) 2016-12-19 2023-05-02 에스케이하이닉스 주식회사 칩들 사이에 열 전달 블록을 배치한 반도체 패키지 및 제조 방법
TWI672779B (zh) * 2016-12-28 2019-09-21 曦威科技股份有限公司 指紋辨識裝置、使用其之行動裝置以及指紋辨識裝置的製造方法
KR20190092584A (ko) * 2016-12-29 2019-08-07 인벤사스 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
US10504843B2 (en) 2017-05-02 2019-12-10 L. Pierre de Rochemont High speed semiconductor chip stack
US10468345B2 (en) * 2017-05-19 2019-11-05 Taiwan Semiconductor Manufacturing Company Ltd. 3D IC decoupling capacitor structure and method for manufacturing the same
US10910325B2 (en) * 2017-05-29 2021-02-02 Intel Corporation Integrated circuit packages with conductive element having cavities housing electrically connected embedded components
MY202342A (en) * 2017-06-08 2024-04-24 Intel Corp Over-molded ic package with in-mold capacitor
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
KR102385549B1 (ko) 2017-08-16 2022-04-12 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
TWI766072B (zh) * 2017-08-29 2022-06-01 瑞典商斯莫勒科技公司 能量存儲中介層裝置、電子裝置和製造方法
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
KR102404058B1 (ko) * 2017-12-28 2022-05-31 삼성전자주식회사 반도체 패키지
WO2019132958A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Microelectronic assemblies
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
TW202038266A (zh) * 2018-11-26 2020-10-16 瑞典商斯莫勒科技公司 具有離散的能量儲存構件之半導體組件
US11264332B2 (en) 2018-11-28 2022-03-01 Micron Technology, Inc. Interposers for microelectronic devices
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US20200235066A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
WO2020153983A1 (en) 2019-01-23 2020-07-30 Qorvo Us, Inc. Rf semiconductor device and manufacturing method thereof
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US11476241B2 (en) 2019-03-19 2022-10-18 Micron Technology, Inc. Interposer, microelectronic device assembly including same and methods of fabrication
KR102586890B1 (ko) * 2019-04-03 2023-10-06 삼성전기주식회사 반도체 패키지
US11374136B2 (en) * 2019-09-27 2022-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and forming method thereof
KR102276278B1 (ko) * 2019-11-05 2021-07-12 주식회사 이큐셀 반도체 공정 진단을 위한 플라즈마 센서 장치 및 이의 제조 방법
CN110828496B (zh) * 2019-11-15 2022-10-11 华天科技（昆山）电子有限公司 半导体器件及其制造方法
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
CN111128994A (zh) * 2019-12-27 2020-05-08 华为技术有限公司 一种***级封装结构及其封装方法
US20210202472A1 (en) * 2019-12-27 2021-07-01 Intel Corporation Integrated circuit structures including backside vias
US20210272885A1 (en) * 2020-02-27 2021-09-02 Intel Corporation Interposer heat spreader
US11552054B2 (en) * 2020-06-29 2023-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
CN112312654B (zh) * 2020-08-14 2021-09-17 珠海越亚半导体股份有限公司 一种嵌埋在玻璃介质中的无源器件结构及其制造方法
US11164822B1 (en) * 2020-09-28 2021-11-02 United Microelectronics Corp. Structure of semiconductor device and method for bonding two substrates
US11715594B2 (en) * 2021-05-27 2023-08-01 International Business Machines Corporation Vertically-stacked interdigitated metal-insulator-metal capacitor for sub-20 nm pitch

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115988B1 (en) * 2004-01-21 2006-10-03 Altera Corporation Bypass capacitor embedded flip chip package lid and stiffener
US20100230806A1 (en) * 2009-03-13 2010-09-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors
US20120086135A1 (en) * 2010-10-06 2012-04-12 Thompson Jeffrey C Interposers, electronic modules, and methods for forming the same
US20130181354A1 (en) * 2012-01-12 2013-07-18 Broadcom Corporation Semiconductor Interposer Having a Cavity for Intra-Interposer Die

Family Cites Families (153)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567653A (en) 1994-09-14 1996-10-22 International Business Machines Corporation Process for aligning etch masks on an integrated circuit surface using electromagnetic energy
US5701233A (en) 1995-01-23 1997-12-23 Irvine Sensors Corporation Stackable modules and multimodular assemblies
US6008536A (en) 1997-06-23 1999-12-28 Lsi Logic Corporation Grid array device package including advanced heat transfer mechanisms
US6157076A (en) 1997-06-30 2000-12-05 Intersil Corporation Hermetic thin pack semiconductor device
US6631672B2 (en) * 1997-11-03 2003-10-14 Hunterwood Technologies, Ltd. Method and apparatus for processing large square hay bales into smaller recompressed bales
US6624505B2 (en) 1998-02-06 2003-09-23 Shellcase, Ltd. Packaged integrated circuits and methods of producing thereof
JP3630551B2 (ja) 1998-04-02 2005-03-16 株式会社東芝 半導体記憶装置及びその製造方法
TW426931B (en) 1999-07-29 2001-03-21 Mosel Vitelic Inc Manufacturing method and structure of trench type capacitor having a cylindrical conductive plate
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
IL133453A0 (en) 1999-12-10 2001-04-30 Shellcase Ltd Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US6251796B1 (en) 2000-02-24 2001-06-26 Conexant Systems, Inc. Method for fabrication of ceramic tantalum nitride and improved structures based thereon
US6384473B1 (en) 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6451650B1 (en) 2001-04-20 2002-09-17 Taiwan Semiconductor Manufacturing Company Low thermal budget method for forming MIM capacitor
US7061102B2 (en) 2001-06-11 2006-06-13 Xilinx, Inc. High performance flipchip package that incorporates heat removal with minimal thermal mismatch
US6856007B2 (en) 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6620701B2 (en) 2001-10-12 2003-09-16 Infineon Technologies Ag Method of fabricating a metal-insulator-metal (MIM) capacitor
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
JP2004014714A (ja) 2002-06-05 2004-01-15 Mitsubishi Electric Corp キャパシタの製造方法
GB0221439D0 (en) 2002-09-16 2002-10-23 Enpar Technologies Inc Ion-exchange/electrochemical treatment of ammonia in waste-water
JP4056854B2 (ja) 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
US6919508B2 (en) 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US7400036B2 (en) 2002-12-16 2008-07-15 Avago Technologies General Ip Pte Ltd Semiconductor chip package with a package substrate and a lid cover
JP4390541B2 (ja) 2003-02-03 2009-12-24 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
TWI278975B (en) 2003-03-04 2007-04-11 Siliconware Precision Industries Co Ltd Semiconductor package with heatsink
SG137651A1 (en) 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
JP2004281830A (ja) 2003-03-17 2004-10-07 Shinko Electric Ind Co Ltd 半導体装置用基板及び基板の製造方法及び半導体装置
US7102217B2 (en) 2003-04-09 2006-09-05 Micron Technology, Inc. Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same
US7012326B1 (en) 2003-08-25 2006-03-14 Xilinx, Inc. Lid and method of employing a lid on an integrated circuit
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
TWI251916B (en) 2003-08-28 2006-03-21 Phoenix Prec Technology Corp Semiconductor assembled heat sink structure for embedding electronic components
US7031162B2 (en) 2003-09-26 2006-04-18 International Business Machines Corporation Method and structure for cooling a dual chip module with one high power chip
US7183643B2 (en) 2003-11-04 2007-02-27 Tessera, Inc. Stacked packages and systems incorporating the same
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
CN1645172A (zh) 2004-01-22 2005-07-27 松下电器产业株式会社 光传送路基板、光传送路内置基板、及它们的制造方法
JP4441328B2 (ja) 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP3972209B2 (ja) 2004-05-26 2007-09-05 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US7786591B2 (en) 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
US6947275B1 (en) 2004-10-18 2005-09-20 International Business Machines Corporation Fin capacitor
JP4677991B2 (ja) 2004-12-02 2011-04-27 株式会社村田製作所 電子部品及びその製造方法
KR100594952B1 (ko) 2005-02-04 2006-06-30 삼성전자주식회사 웨이퍼 레벨 패키징 캡 및 그 제조방법
WO2006124597A2 (en) 2005-05-12 2006-11-23 Foster Ron B Infinitely stackable interconnect device and method
US7767493B2 (en) 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
JP4889974B2 (ja) 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
JP2007042719A (ja) 2005-08-01 2007-02-15 Nec Electronics Corp 半導体装置
US7906803B2 (en) 2005-12-06 2011-03-15 Canon Kabushiki Kaisha Nano-wire capacitor and circuit device therewith
US7344954B2 (en) 2006-01-03 2008-03-18 United Microelectonics Corp. Method of manufacturing a capacitor deep trench and of etching a deep trench opening
US7560761B2 (en) 2006-01-09 2009-07-14 International Business Machines Corporation Semiconductor structure including trench capacitor and trench resistor
US7977579B2 (en) 2006-03-30 2011-07-12 Stats Chippac Ltd. Multiple flip-chip integrated circuit package system
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7510928B2 (en) 2006-05-05 2009-03-31 Tru-Si Technologies, Inc. Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques
US7513035B2 (en) 2006-06-07 2009-04-07 Advanced Micro Devices, Inc. Method of integrated circuit packaging
JP5107539B2 (ja) 2006-08-03 2012-12-26 新光電気工業株式会社 半導体装置および半導体装置の製造方法
TWI367557B (en) 2006-08-11 2012-07-01 Sanyo Electric Co Semiconductor device and manufaturing method thereof
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US20080128897A1 (en) 2006-12-05 2008-06-05 Tong Wa Chao Heat spreader for a multi-chip package
US7670921B2 (en) 2006-12-28 2010-03-02 International Business Machines Corporation Structure and method for self aligned vertical plate capacitor
US7800916B2 (en) 2007-04-09 2010-09-21 Endicott Interconnect Technologies, Inc. Circuitized substrate with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same
US8039309B2 (en) 2007-05-10 2011-10-18 Texas Instruments Incorporated Systems and methods for post-circuitization assembly
KR100909322B1 (ko) 2007-07-02 2009-07-24 주식회사 네패스 초박형 반도체 패키지 및 그 제조방법
EP2213148A4 (en) 2007-10-10 2011-09-07 Tessera Inc ROBUST MULTILAYER WIRING ELEMENTS AND ASSEMBLIES INCLUDING MICROELECTRONIC ELEMENTS INCLUDED
EP2215655A4 (en) 2007-11-30 2014-07-30 Skyworks Solutions Inc CAPACITATION AT WAFBERBENE USING FLIP-CHIP ATTACHMENT
US7928548B2 (en) 2008-01-07 2011-04-19 International Business Machines Corporation Silicon heat spreader mounted in-plane with a heat source and method therefor
SG142321A1 (en) 2008-04-24 2009-11-26 Micron Technology Inc Pre-encapsulated cavity interposer
US8008764B2 (en) 2008-04-28 2011-08-30 International Business Machines Corporation Bridges for interconnecting interposers in multi-chip integrated circuits
US7863096B2 (en) 2008-07-17 2011-01-04 Fairchild Semiconductor Corporation Embedded die package and process flow using a pre-molded carrier
JP2010034403A (ja) 2008-07-30 2010-02-12 Shinko Electric Ind Co Ltd 配線基板及び電子部品装置
US8101494B2 (en) 2008-08-14 2012-01-24 International Business Machines Corporation Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors
US8257985B2 (en) 2008-09-25 2012-09-04 Texas Instruments Incorporated MEMS device and fabrication method
KR20100037300A (ko) 2008-10-01 2010-04-09 삼성전자주식회사 내장형 인터포저를 갖는 반도체장치의 형성방법
JP2010092977A (ja) 2008-10-06 2010-04-22 Panasonic Corp 半導体装置及びその製造方法
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101015704B1 (ko) 2008-12-01 2011-02-22 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
US8354304B2 (en) 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
JP5308145B2 (ja) 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
US8343806B2 (en) 2009-03-05 2013-01-01 Raytheon Company Hermetic packaging of integrated circuit components
US8216887B2 (en) 2009-05-04 2012-07-10 Advanced Micro Devices, Inc. Semiconductor chip package with stiffener frame and configured lid
EP2273545B1 (en) 2009-07-08 2016-08-31 Imec Method for insertion bonding and kit of parts for use in said method
US8143097B2 (en) 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
JP5330184B2 (ja) 2009-10-06 2013-10-30 新光電気工業株式会社 電子部品装置
US8531012B2 (en) 2009-10-23 2013-09-10 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV
JP5295932B2 (ja) 2009-11-02 2013-09-18 新光電気工業株式会社 半導体パッケージ及びその評価方法、並びにその製造方法
US8519537B2 (en) 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8378480B2 (en) 2010-03-04 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy wafers in 3DIC package assemblies
US8541886B2 (en) 2010-03-09 2013-09-24 Stats Chippac Ltd. Integrated circuit packaging system with via and method of manufacture thereof
US8183696B2 (en) 2010-03-31 2012-05-22 Infineon Technologies Ag Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads
FR2960339B1 (fr) 2010-05-18 2012-05-18 Commissariat Energie Atomique Procede de realisation d'elements a puce munis de rainures d'insertion de fils
US8349653B2 (en) 2010-06-02 2013-01-08 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional metal interconnect technologies
KR101394205B1 (ko) 2010-06-09 2014-05-14 에스케이하이닉스 주식회사 반도체 패키지
US8426961B2 (en) 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
KR101129909B1 (ko) 2010-07-20 2012-03-23 주식회사 하이닉스반도체 반도체 소자의 필라형 캐패시터 및 그 형성방법
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
TWI445104B (zh) 2010-08-25 2014-07-11 Advanced Semiconductor Eng 半導體封裝結構及其製程
US9343436B2 (en) 2010-09-09 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked package and method of manufacturing the same
US8617926B2 (en) 2010-09-09 2013-12-31 Advanced Micro Devices, Inc. Semiconductor chip device with polymeric filler trench
US8830689B2 (en) 2010-09-16 2014-09-09 Samsung Electro-Mechanics Co., Ltd. Interposer-embedded printed circuit board
KR20130052652A (ko) 2010-09-18 2013-05-22 페어차일드 세미컨덕터 코포레이션 미세 전자 기계 시스템을 위한 시일된 패키징
US8666505B2 (en) 2010-10-26 2014-03-04 Medtronic, Inc. Wafer-scale package including power source
WO2012061633A2 (en) 2010-11-03 2012-05-10 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
FR2968130A1 (fr) * 2010-11-30 2012-06-01 St Microelectronics Sa Dispositif semi-conducteur comprenant un condensateur et un via de connexion electrique et procede de fabrication
US8502340B2 (en) 2010-12-09 2013-08-06 Tessera, Inc. High density three-dimensional integrated capacitors
US8575493B1 (en) 2011-02-24 2013-11-05 Maxim Integrated Products, Inc. Integrated circuit device having extended under ball metallization
US9018094B2 (en) 2011-03-07 2015-04-28 Invensas Corporation Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates
JP2012231096A (ja) 2011-04-27 2012-11-22 Elpida Memory Inc 半導体装置及びその製造方法
JP2012256846A (ja) 2011-05-16 2012-12-27 Elpida Memory Inc 半導体装置の製造方法
US20140194379A1 (en) 2011-06-03 2014-07-10 University Of Washington Through Its Center For Commercialization Methods for the production of chitin nanofibers and uses thereof
WO2012169162A1 (ja) 2011-06-06 2012-12-13 住友ベークライト株式会社 補強部材、半導体パッケージ、半導体装置、半導体パッケージの製造方法
US8409923B2 (en) 2011-06-15 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with underfill and method of manufacture thereof
US8497558B2 (en) 2011-07-14 2013-07-30 Infineon Technologies Ag System and method for wafer level packaging
US9125333B2 (en) 2011-07-15 2015-09-01 Tessera, Inc. Electrical barrier layers
EP2555239A3 (en) 2011-08-04 2013-06-05 Sony Mobile Communications AB Thermal package with heat slug for die stacks
TWI492680B (zh) 2011-08-05 2015-07-11 Unimicron Technology Corp 嵌埋有中介層之封裝基板及其製法
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US20130082383A1 (en) 2011-10-03 2013-04-04 Texas Instruments Incorporated Electronic assembly having mixed interface including tsv die
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR101932665B1 (ko) 2011-10-10 2018-12-27 삼성전자 주식회사 반도체 패키지
US9287191B2 (en) 2011-10-12 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package and method
KR20130042936A (ko) 2011-10-19 2013-04-29 에스케이하이닉스 주식회사 칩 캐리어, 이를 이용한 반도체 칩, 반도체 패키지, 및 그 제조방법들
WO2013062533A1 (en) 2011-10-25 2013-05-02 Intel Corporation Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips
US9153520B2 (en) 2011-11-14 2015-10-06 Micron Technology, Inc. Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US8518753B2 (en) 2011-11-15 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Assembly method for three dimensional integrated circuit
US9627357B2 (en) 2011-12-02 2017-04-18 Intel Corporation Stacked memory allowing variance in device interconnects
US8975711B2 (en) 2011-12-08 2015-03-10 Infineon Technologies Ag Device including two power semiconductor chips and manufacturing thereof
US8686570B2 (en) 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
JP2013183120A (ja) 2012-03-05 2013-09-12 Elpida Memory Inc 半導体装置
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8872349B2 (en) 2012-09-11 2014-10-28 Intel Corporation Bridge interconnect with air gap in package assembly
US20140091461A1 (en) 2012-09-30 2014-04-03 Yuci Shen Die cap for use with flip chip package
US9040349B2 (en) 2012-11-15 2015-05-26 Amkor Technology, Inc. Method and system for a semiconductor device package with a die to interposer wafer first bond
US8796072B2 (en) 2012-11-15 2014-08-05 Amkor Technology, Inc. Method and system for a semiconductor device package with a die-to-die first bond
US9136159B2 (en) 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9257355B2 (en) 2013-02-11 2016-02-09 The Charles Stark Draper Laboratory, Inc. Method for embedding a chipset having an intermediary interposer in high density electronic modules
US20140246227A1 (en) 2013-03-01 2014-09-04 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby
US9704809B2 (en) 2013-03-05 2017-07-11 Maxim Integrated Products, Inc. Fan-out and heterogeneous packaging of electronic components
US9111930B2 (en) 2013-03-12 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package with cavity in interposer
JP6110734B2 (ja) 2013-06-06 2017-04-05 ルネサスエレクトロニクス株式会社 半導体装置
US9685414B2 (en) 2013-06-26 2017-06-20 Intel Corporation Package assembly for embedded die and associated techniques and configurations
US20150262902A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9524883B2 (en) * 2014-05-13 2016-12-20 Invensas Corporation Holding of interposers and other microelectronic workpieces in position during assembly and other processing
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115988B1 (en) * 2004-01-21 2006-10-03 Altera Corporation Bypass capacitor embedded flip chip package lid and stiffener
US20100230806A1 (en) * 2009-03-13 2010-09-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors
US20120086135A1 (en) * 2010-10-06 2012-04-12 Thompson Jeffrey C Interposers, electronic modules, and methods for forming the same
US20130181354A1 (en) * 2012-01-12 2013-07-18 Broadcom Corporation Semiconductor Interposer Having a Cavity for Intra-Interposer Die

Also Published As

Publication number Publication date
US9831302B2 (en) 2017-11-28
US20180076278A1 (en) 2018-03-15
US9508638B2 (en) 2016-11-29
TW201604923A (zh) 2016-02-01
WO2015168222A1 (en) 2015-11-05
US20150318344A1 (en) 2015-11-05
US20190172903A1 (en) 2019-06-06
US9165793B1 (en) 2015-10-20
US10431648B2 (en) 2019-10-01
US10204977B2 (en) 2019-02-12
US20160049361A1 (en) 2016-02-18
KR20160149211A (ko) 2016-12-27
US20170077076A1 (en) 2017-03-16

Similar Documents

Publication Publication Date Title
TWI587357B (zh) 積體電路封裝及製造方法
KR102659849B1 (ko) 전도성 배리어 직접 하이브리드 접합
JP4783692B2 (ja) キャパシタ内蔵基板及びその製造方法と電子部品装置
US9224681B2 (en) CTE matched interposer and method of making
CN108269784B (zh) 中介层，以及包含中介层的半导体封装体及其制作方法
WO2011114774A1 (ja) 半導体素子内蔵基板およびその製造方法
KR20170121228A (ko) 기판을 관통하는 관통-구멍으로부터 돌출되는 전도성 비아의 돌출부를 둘러싸는 특징부를 가진 마이크로전자 구성요소
WO2015192096A2 (en) Making multilayer 3d capacitors using arrays of upstanding rods or ridges
KR20080038035A (ko) 반도체 패키지 및 적층형 반도체 패키지
CN111584455A (zh) 再分布基板、制造再分布基板的方法以及半导体封装
TW201834174A (zh) 包括互連結構之半導體系統及裝置封裝
US11380611B2 (en) Chip-on-wafer structure with chiplet interposer
US12027455B2 (en) Chip-on-wafer structure with Chiplet Interposer
US20130037946A1 (en) Semiconductor chip including bump having barrier layer, and manufacturing method thereof
US8039967B2 (en) Wiring substrate with a wire terminal
US20090236647A1 (en) Semiconductor device with capacitor
US20240030118A1 (en) Package substrate and semiconductor package including the same
CN112490187B (zh) 半导体互联结构及其制备方法
US9412686B2 (en) Interposer structure and manufacturing method thereof
KR102422244B1 (ko) 관통 전극을 갖는 반도체 장치 및 그의 제조 방법
CN210136865U (zh) 一种晶圆级封装结构
KR100897822B1 (ko) 시스템 인 패키지의 제조 방법
TW202226396A (zh) 半導體裝置及其製造方法
KR20230031883A (ko) 인터포저 없는 멀티칩 모듈