TWI575670B - 包括一用於嵌入及／或間隔半導體晶粒之獨立薄膜層之半導體裝置 - Google Patents

包括一用於嵌入及／或間隔半導體晶粒之獨立薄膜層之半導體裝置 Download PDF

Info

Publication number
TWI575670B
TWI575670B TW102139867A TW102139867A TWI575670B TW I575670 B TWI575670 B TW I575670B TW 102139867 A TW102139867 A TW 102139867A TW 102139867 A TW102139867 A TW 102139867A TW I575670 B TWI575670 B TW I575670B
Authority
TW
Taiwan
Prior art keywords
film layer
die
substrate
semiconductor
semiconductor device
Prior art date
Application number
TW102139867A
Other languages
English (en)
Other versions
TW201436118A (zh
Inventor
葉寧
邱進添
蘇瑞許 烏帕亞尤拉
付鵬
呂忠
俞志明
章遠
王麗
普拉迪波 庫馬 萊
王偉利
邰恩勇
翁錦富
金理 莫
Original Assignee
晟碟半導體（上海）有限公司
晟碟信息科技（上海）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 晟碟半導體（上海）有限公司, 晟碟信息科技（上海）有限公司 filed Critical 晟碟半導體（上海）有限公司
Publication of TW201436118A publication Critical patent/TW201436118A/zh
Application granted granted Critical
Publication of TWI575670B publication Critical patent/TWI575670B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/27318—Manufacturing methods by local deposition of the material of the layer connector in liquid form by dispensing droplets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/27848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32265—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1205—Capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1206—Inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1207—Resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

包括一用於嵌入及/或間隔半導體晶粒之獨立薄膜層之半導體裝置
對攜帶型消費性電子產品之需求之強勁增長推升了高容量儲存裝置之需要。非揮發性半導體記憶體裝置，諸如快閃記憶體儲存卡，正變得廣泛使用以滿足數位資訊儲存及交換之日益增長之需求。其等之可攜帶性、多功能性及堅固耐用設計連同其等之高可靠性及大容量，使得此等記憶體裝置對很多種電子裝置(包括例如數位相機、數位音樂播放器、電子遊戲機、PADs及蜂巢電話)中之使用係理想的。
雖然已知許多不同封裝組態，快閃記憶體儲存卡大體上可製造為單封裝系統(SiP)或多片模組(MCM)，其中複數個晶粒安裝及互連於一小佔據面積基板上。基板大體上可包含具有蝕刻於一或兩側上之一導電層之一剛性、介電基底。電連接形成於晶粒與導電層之間，且導電層提供一電引線結構以用於將晶粒連接至一主機裝置。一旦形成晶粒與基板之間之電連接，總成接著通常被包入提供一保護封裝之一模製化合物中。
圖1及圖2中展示一習知半導體封裝20之一截面側視圖及一俯視圖(沒有圖2中之模製化合物)。典型封裝包含貼附至一基板26之複數個半導體晶粒，諸如快閃記憶體晶粒22及控制器晶粒24。複數個晶粒 接合墊28在晶粒製程期間可形成於半導體晶粒22、24上。類似地，複數個接觸墊30可形成於基板26上。晶粒22可貼附至基板26，且接著晶粒24可安裝於晶粒22上。所有晶粒可接著藉由貼附各自晶粒接合墊28與接觸墊30對之間之接合線32電耦合至基板。一旦製成所有電連接，晶粒及接合線可囊封於一模製化合物34中以密封封裝且保護晶粒及接合線。
為了最有效地使用封裝佔據面積，已知將半導體晶粒彼此上下堆疊，使得其等彼此完全重疊或者具有如圖1及圖2中所展示之偏移。在一偏移組態中，將一晶粒堆疊於另一晶粒之頂部上，使得較低晶粒之接合墊留下暴露。一偏移組態提供方便接達堆疊中之半導體晶粒之各者上之接合墊之一優勢。
為了增加半導體封裝中之記憶體容量，同時維持或減小封裝之整體尺寸，相對於封裝之整體尺寸，記憶體晶粒之尺寸變大。因而，記憶體晶粒之佔據面積與基板之佔據面積幾乎一樣大是常見的。因此，用於向下線接合至基板之半導體封裝內之空間係珍貴的。特定而言，當存在多個堆疊快閃記憶體晶粒22，為所有需要製成所有必須電連接之接觸墊在基板上找到空間會變得困難。在一實際半導體封裝中之晶粒接合墊、接觸墊及接合線之數目可比圖1及圖2中所展示的多很多。為了清晰起見，圖1及圖2中所展示之數目被大大減小。此外，圖1及圖2僅包含一對記憶體晶粒22。可比在晶粒堆疊中存在更多，使得更難為所有所需接合線找到空間。
控制器晶粒24通常比記憶體晶粒22更小。因此，控制器晶粒24習知放置於記憶體晶粒堆疊之頂部。然而，當存在已經接合至基板之複數個堆疊記憶體晶粒，為所有所需的控制器晶粒接合線在基板上找到空間常常是困難的。此外，存在增加半導體裝置操作之速度之一需要，正如增加一半導體裝置內之記憶體晶粒之數目。鑑於此等因素， 一些半導體封裝與直接接合至基板之控制器晶粒一起製成。
為了之後將記憶體晶粒接合至控制器之頂部，底部記憶體晶粒具備一層液體黏著劑。底部晶粒施加至控制器晶粒頂部，使得控制器晶粒及接合線嵌入液體黏著劑層內。之後，固化液體黏著劑層。
此操作具有某些缺點。例如，液體黏著劑趨於流向底部記憶體晶粒之一上表面，在那其可污染晶粒接合墊且妨礙適當線接合至基板。此外，通常將額外記憶體晶粒添加於底部晶粒之頂部上以形成記憶體晶粒之一堆疊。習知設計之另一問題為底部晶粒(用液體黏著劑)附接至一第一站，且接著將封裝移動至一第二站，堆疊中之剩餘晶粒安裝(使用一晶粒附接黏著劑)於此處。進一步問題包含液體黏著劑固化前底部記憶體晶粒之移動，嵌入液體黏著劑內對控制器晶粒或接合線之損害，以及固化及液體黏著劑與底部記憶體晶粒之間之熱錯配對底部記憶體晶粒之損害。
20‧‧‧半導體封裝
22‧‧‧快閃記憶體晶粒/半導體晶粒/晶粒/記憶體晶粒/堆疊快閃記憶體晶粒
24‧‧‧控制器晶粒/半導體晶粒/晶粒
26‧‧‧基板
28‧‧‧晶粒接合墊
30‧‧‧接觸墊
32‧‧‧接合線
34‧‧‧模製化合物
100‧‧‧個別裝置/封裝/成品半導體裝置/成品裝置/其他封裝/半導體裝置
102‧‧‧基板
103‧‧‧芯體
104‧‧‧通孔
105‧‧‧頂部導電層/導電層
106‧‧‧電跡線/跡線
107‧‧‧底部導電層/導電層
108‧‧‧接觸墊/觸點
110‧‧‧焊料遮罩/焊料遮罩層
112‧‧‧被動組件
114‧‧‧控制器晶粒/控制器
116‧‧‧接合線
118‧‧‧晶粒接合墊
120‧‧‧薄膜層/層/固體薄膜層
130‧‧‧半導體晶粒/晶粒/記憶體晶粒
130a‧‧‧底部晶粒/晶粒
132‧‧‧晶粒附接黏著劑
140‧‧‧模製化合物
142‧‧‧焊球
150‧‧‧開口
200‧‧‧步驟
202‧‧‧步驟
204‧‧‧步驟
206‧‧‧步驟
208‧‧‧步驟
210‧‧‧步驟
212‧‧‧步驟
214‧‧‧步驟
216‧‧‧步驟
218‧‧‧步驟
220‧‧‧步驟
224‧‧‧步驟
226‧‧‧步驟
228‧‧‧步驟
230‧‧‧步驟
232‧‧‧步驟
234‧‧‧步驟
圖1係一習知半導體封裝之一截面側視圖。
圖2係一習知基板及線接合半導體晶粒之一俯視圖。
圖3係根據本發明之實施例之半導體裝置之整體製程之一流程圖。
圖4係在包含在本發明之一實施例中將一控制器晶粒表面安裝至一基板之製程內之一第一步驟之一半導體裝置之一側視圖。
圖5係圖4中所展示之半導體裝置之一俯視圖。
圖6係在包含在本發明之一實施例中在基板上形成一薄膜層之製程之一第二步驟之一半導體裝置之一側視圖。
圖7係圖6中所展示之半導體裝置之一俯視圖。
圖8係在包含在本發明之一實施例中將一晶粒堆疊安裝至基板之製程之一第三步驟之一半導體裝置之一側視圖。
圖9係展示在本發明之一實施例中用於將一薄膜層固化成最終C階之溫度及持續時間之一標繪圖。
圖10係根據本發明之一實施例之一成品半導體裝置之一側視圖。
圖11係在本發明之一替代實施例中包含安裝至基板之一晶粒堆疊之一半導體裝置之一側視圖。
圖12係在本發明之一進一步替代實施例中包含安裝至基板之一晶粒堆疊之一半導體裝置之一側視圖。
圖13至圖16係根據本發明之進一步實施例之基板上之一薄膜層之替代組態。
參考圖3至圖16現將描述本發明，在本實施例中，其係關於一半導體裝置，該半導體裝置包含獨立施加至基板以用於嵌入一表面安裝控制器晶粒及/或被動組件或用於將一記憶體晶粒堆疊與一表面安裝控制器晶粒及/或被動組件間隔之薄膜層。應理解，本發明可以許多不同形式體現，且不應被理解為限定於本文闡述之實施例。更確切的說，提供此等實施例，使得本發明將係透徹及完全的，且將完全將本發明傳達至熟習此項技術者。事實上，本發明意欲覆蓋此等實施例之替代，修改及等效，其等包含於藉由隨附申請專利範圍定義之本發明之範疇及精神內。此外，為了提供本發明之一透徹理解，在本發明之以下詳細描述中闡述數種特定細節。然而，一般技術者將清楚本發明可在沒有此等特定細節之情況下實踐本發明。
本文可使用術語「頂部」及「底部」、「上」及「下」及「垂直」及「水平」僅用於實例及繪示目的，且不意指限制本發明之描述，因為參考項目在位置及方向上可交換。
參考圖3之流程圖及圖4至圖16之俯視圖及側視圖現將解釋本發 明之一實施例。儘管圖4至圖16各展示一個別裝置100或其之一部分，應理解裝置100可與一基板面板上之複數個其他封裝100一起批次處理以達成大規模生產之經濟效益。基板面板上之封裝100之列及行之數目可變化。
基板面板開始於複數個基板102(又，圖4至圖16中展示之一此基板)。基板102可為各種不同晶片載體介質，包含一印刷電路板(PCB)、一引線框或一帶式自動接合(TAB)帶。在基板102係一PCB之情況下，基板可由具有一頂部導電層105及一底部導電層107之一芯體103形成。芯體103可由各種介電材料形成，諸如例如，聚醯亞胺積層、包含FR4及FR5之環氧樹脂、雙馬來醯亞胺三嗪(BT)及類似物。儘管對本發明不是關鍵的，芯體可具有40微米(μm)至200μm之間之一厚度，然而在替代實施例中芯體之厚度可在該範圍外變化。在替代實施例中芯體103可為陶瓷或有機的。
包圍芯體之導電層105、107可由銅或銅合金、鍍銅或鍍銅合金、合金42(42Fe/58Ni)、銅鍍剛或已知在基板面板上使用之其他金屬及材料形成。導電層可具有約10μm至25μm之一厚度，然而在替代實施例中層之厚度可在該範圍外變化。
圖3係根據本發明之實施例用於形成一半導體裝置之製程之一流程圖。在步驟200中，基板102經鑽孔以在基板102中形成直通通孔104。經由實例展示通孔104(圖式中僅編號其中一些)，且基板可包含比圖式中展示多很多之通孔104，且其等可在與圖式中所展示不同位置。然後電導型樣在步驟202中形成於頂部導電層及底部導電層之一或兩者上。電導型樣可包含電跡線106及接觸墊108。經由實例展示跡線106及接觸墊108(圖式中僅編號其中一些)，且基板102可包含比圖式中展示的更多的跡線及/或接觸墊，且其等可在與圖式中所展示之不同位置。
在實施例中，成品半導體裝置100總成可用作一BGA封裝。基板102之一下表面可包含如下文解釋之用於接收焊球之接觸墊108。在進一步實施例中，成品半導體裝置100可包含用於可移除耦合成品裝置100於一主機裝置內之接觸指狀物之一LGA封裝。在此實施例中，下表面可包含接觸指狀物，而不是接收焊球之接觸墊。基板102之頂部及/或底部表面上之電導型樣可由各種已知製程形成，包含例如各種光學微影製程。
再參考圖3，在步驟204中基板102可接著在一自動光學檢查(AOI)中檢測。一旦檢測，在步驟206中一焊料遮罩110可施加至基板。施加焊料遮罩後，接觸墊、接觸指狀物及導電圖案上之任何其他焊接區域可在一已知電鍍或薄膜沈積製程中之步驟208中被鍍覆一Ni/Au，合金42或類似物。基板102可接著在一自動檢測製程(步驟210)中且在一最終視覺檢測(步驟212)中經檢測及測試以檢查電操作，以及用於檢查污染、刮擦及變色。假定基板102通過檢測，在一步驟214中被動組件112接著可附接至基板。一或多個被動組件可包含，例如，一或多個電容器、電阻器及/或電感器，但採用其他組件。僅經由實例展示被動組件112(圖式中僅編號其中一些)，且在進一步實施例中類型及位置可變化。
諸如例如一ASIC之一控制器晶粒114在步驟216中可接著附接及電耦合至基板102。控制器晶粒114之上表面上之晶粒接合墊118可經由接合線116電耦合至接觸墊108。僅編號及展示一些接合線116及晶粒接合墊118。線接合製程可為諸如一反向球接合製程之一已知製程，但採用其他線接合製程。在進一步實施例中，控制器114可在一覆晶製程中安裝至觸點108，在此情況下可略去接合線116。
現參考圖7之側視圖，一薄膜層可在步驟218中形成於基板102上。在習知設計中，將一液體黏著劑施加至一底部記憶體晶粒，且記 憶體晶粒接著安裝於基板上，使得線接合控制器晶粒嵌入液體黏著劑內。如先前技術段落中所描述，此方法有問題，包含液體黏著劑流向記憶體晶粒之一上側，及將記憶體晶粒及液體黏著劑降低至控制器晶粒及接合線對控制器晶粒及/或控制器晶粒接合線之損害。
本發明解決此等缺點，在實施例中在一步驟218中將一薄膜層120沈積於基板上，完全嵌入控制器晶粒114、接合線116及被動組件112。薄膜層120可自動施加(不在一記憶體晶粒之一底部表面上)。圖6之側視圖及圖7之俯視圖中展示在基板102上之薄膜層120之一實例。
在實施例中，薄膜層120可為一環氧樹脂，在實例中其具有包含低流動性、非無效、低內應力、低扭曲量及非導電性之性質。此薄膜層之實例包含來自在德國杜塞爾多夫有一公司總部之Henkel AG & Co.KGaA之6202C環氧樹脂。在替代實施例中可使用其他環氧樹脂，包含例如來自台灣YizTech,Co.,Ltd.之YizBond®BS1001環氧樹脂，及自在美國明尼蘇達州聖保羅有一公司總部之3M Company之AHS-996E環氧樹脂。應理解其他環氧樹脂，及除了環氧樹脂之SMT黏著劑，在進一步實施例中可用於薄膜層120。
在實例中，薄膜層120可直接印刷至基板102之表面，在焊料遮罩層110及控制器晶粒114之頂部上，作為一A階液體或低黏度糊狀物。可使用諸如來自英格蘭多塞特之DEK International之一Horizon 02i印刷機之一薄膜印刷機，然而在進一步實施例中可使用其他印刷機用於施加薄膜層120。
在一實例中，一模板可定位於基板102之一面板上，且液體或糊狀物可印刷於模板之頂部上之基板上。模板在控制器晶粒114上方對齊之位置及形狀中具有孔隙。因此，當A階環氧樹脂施加至表面，環氧樹脂掩蓋除孔隙所在處之基板面板之所有部分。結果係A階薄膜層120施加至(例如)圖7中展示之形狀內之控制器晶粒114上方。可提供 基板102上之層120之形狀及位置以如在下文中解釋匹配安裝於基板102上之底部晶粒之形狀及位置。然而，亦如在下文中解釋，在進一步實施例中，模板可具有其他形狀之孔隙以形成其他形狀之薄膜層120。在進一步實施例中，可在沒有使用一模板之情況下施加薄膜層120。
一合適模板之一實例係一電鑄(電鑄)模板，諸如來自在美國新澤西州南普萊恩菲爾德有一公司總部之Cookson Performance Materials之Alpha Form Nickel模板。亦可使用其他模板，諸如例如，由不鏽鋼組成之模板。施加A階環氧樹脂後，可使用一刮漿板以確保模板之孔隙內之A階環氧樹脂之完全及平坦覆蓋。施加液體或糊狀環氧樹脂後，刮漿板可在模板之表面上方移動，與模板接觸，使得環氧樹脂進入(即，壓下進入)在一平整施加層中之模板之孔隙。
在實施例中，刮漿板可整合為印刷頭總成之部分，使得A階環氧樹脂藉由刮漿板展開，如同其藉由印刷頭總成施加。用於此用途之一整合印刷頭總成及刮漿板之一實例係來自DEK International之泵打印刮漿板。在進一步實施例中印刷頭總成及刮漿板可為分離的。
在實施例中，薄膜層可具有150μm至250μm之一厚度，然而其可比那更薄或更厚，部分取決於晶粒之數目及成品半導體裝置之規格，控制器晶粒114、接合線116及被動組件112之高度也一樣。在進一步實施例中薄膜層120可藉由除了印刷之方法施加。此等進一步實例包含薄膜沈積技術及噴射式點膠技術。在一實例中，A階薄膜層120在25℃可具有30,000cP，5rpm之Brookfield CP51之一初始黏度，然而應理解在進一步實施例中A階液體之黏度可高於或低於該值。
在實施例中，在基板102上形成薄膜層120後，在步驟220中及如圖8中所展示，一或多個半導體晶粒130可安裝至薄膜層120上之基板102。半導體晶粒130可為(例如)諸如一NAND快閃記憶體晶粒之記憶 體晶粒，但在進一步實施例中在步驟220中其他類型晶粒130可安裝至基板。圖8展示安裝有四個晶粒130之一實施例，但是在進一步實施例中可存在或多或少之半導體晶粒130。
在實施例中，半導體晶粒130之各者可包含用於將晶粒彼此貼附及將晶粒貼附至薄膜層120之晶粒130之一底部表面上之一晶粒附接黏著劑132。晶粒附接黏著劑可為(例如)介於在5μm至20μm之間之厚度的一薄膜，然而在進一步實施例中其可為比該範圍更薄或更厚。可在晶粒130與晶圓分離前或後施加晶粒附接黏著劑132。當在晶粒130為一晶圓之部分時來予以施加時，晶粒附接黏著劑可在一晶圓背面塗層製程中作為一B階環氧樹脂來施加。作為一實例，晶粒附接黏著劑132可為來自在日本有一總部之Nitto-Denko Corp.之EM-710H-P。晶粒附接黏著劑132之另一實例係來自Henkel AG & Co.KGaA之8988UV環氧樹脂，在晶粒130貼附至薄膜層120上之前先固化成B階。
值得注意的，不使用一底部晶粒130a上之晶粒附接黏著劑嵌入控制器114或接合線116。因而，底部晶粒130a亦可包含與其他半導體晶粒相同之B階晶粒附接黏著劑132。因此，晶粒附接黏著劑132可均勻地施加至半導體晶粒130(包含晶粒130a)之各者，例如，當晶粒130仍作為一半導體晶圓之部分而附接在一起且之後固化成B階時。此外，可在與其餘晶粒130相同之處理工具中施加底部晶粒130a。如本文所使用，B階係在一熱固黏著劑及/或環氧樹脂之反應中之一中間階，其中若在儲存或運輸時，材料係穩定的且通常維持其形狀，但當加熱時其可軟化使得可接合至與黏著劑及/或環氧樹脂接觸放置之一表面。
為了將晶粒130貼附至基板102，底部晶粒130a定位成貼靠在基板102上，使得晶粒附接黏著劑平貼於薄膜層120。如上文提及，薄膜層120可作為一A階液體或糊狀物施加至基板。在下文所描述實施例中，薄膜層120可在底部晶粒130a定位於基板102上之前固化成B階。 這使得基板面板可在薄膜層120保持穩定及完整的情況下被儲存及/或運輸。在另一實施例中，在底部晶粒130a定位於基板102上前薄膜層120可固化成C階。一C階係材料係固體且不能溶解的之一熱固黏著劑及/或環氧樹脂之反應中之一最終階，例如由於彼此交叉結合之材料中之分子。下文更詳細解釋當晶粒130a定位於其上時薄膜層120係一B階環氧樹脂及當晶粒130a定位於其上時係一C階環氧樹脂之實例。
在當晶粒130a定位於其上時薄膜層係一B階環氧樹脂之實例中，A階薄膜層120可藉由在125℃加熱90分鐘薄膜層120固化成B階。採用其他加熱溫度及時間。取決於薄膜層120之材料，在進一步實施例中，薄膜層可藉由紫外線照射固化成B階。此B階加熱步驟可發生在將A階薄膜層120施加於模板內後及移除模板前。在進一步實施例中其可發生在移除模板後(或不使用模板)。
當底部晶粒130a放置於B階薄膜層120上，基板可經加熱以軟化B階薄膜層120以促進薄膜層120與底部晶粒130a上之晶粒附接黏著劑132之間之膠黏性。施加加熱可固化薄膜層120及下晶粒130上之晶粒附接黏著劑132之兩者至彼此穩固黏附之C階固體。在一實例中，與晶粒附接黏著劑132接觸後，B階薄膜層120可在30分鐘內自室溫逐漸升溫至100℃，且在100℃以額外30分鐘來加熱薄膜層120以固化成其最終C階。在另一實例中，固化成C階環氧樹脂可發生在以30分鐘自室溫逐漸升溫至175℃且以額外30分鐘在175℃的情況下。薄膜層120固化成C階之進一步實例可發生在上文描述範圍之間之任何地方之溫度。
此外，在進一步實施例中薄膜層120固化成C階可發生在溫度及時間高於或低於上文描述實例之情況下。此外，層120之一固化成C階具有多個加熱階，例如如圖9中所展示。採用多個加熱階之其他實例，圖9中展示之任何溫度及時間段可變化。取決於薄膜層120之材 料，在進一步實施例中薄膜層以超音波方式固化成C階。
在當晶粒130a定位於其上時薄膜層係一C階環氧樹脂之一實例中，根據上文描述之任何B階與C階固化方法，A階薄膜層120可固化成B階，且隨後成C階。在一進一步實施例中，A階薄膜層120可直接固化成C階。此亦可由上文所描述之任何C階固化方法完成。一些環氧樹脂係用以從A階直接固化成C階。此等環氧樹脂在本文中係稱之為A階環氧樹脂。其他環氧樹脂用以從A階固化成中間B階且接著成C階。此等環氧樹脂在本文中係稱之為B階環氧樹脂。在當晶粒130a定位於其上時薄膜層係一C階環氧樹脂之一實例中，亦可使用A階或B階環氧樹脂。在此實施例中，最終C階薄膜層120未將底部晶粒130a黏附至基板。底部晶粒130a上之晶粒附接黏著劑132將晶粒130a接合至固體薄膜層120(在將薄膜層120固化成C階之一單獨固化步驟中)。
如上文所描述底部晶粒130a定位於薄膜層120上後，晶粒堆疊中之額外晶粒130可類似地定位於晶粒堆疊中。此外，如圖8中所展示，在步驟224中，晶粒130之各者可藉由在晶粒130上之晶粒接合墊與基板102上之接觸墊108之間形成之接合線136電耦合至基板。當所有接合線如所展示自記憶體晶粒130之一單一邊緣延伸，應理解晶粒130可具有晶粒接合墊及圍繞兩個或兩個以上邊緣之接合線。此外，堆疊中之晶粒130可彼此線接合，代替或除了各晶粒130線接合至基板102。
在實施例中，各晶粒130定位於基板上後，其可線接合至基板102。在進一步實施例中，所有晶粒可定位於基板上，且接著在此後，所有晶粒可線接合至基板。在實施例中，所有晶粒定位於晶粒堆疊內後及所有晶粒線接合至基板前或後，各晶粒130上之晶粒附接黏著劑132可經固化以將晶粒彼此接合及將晶粒接合至基板。在當晶粒130定位於晶粒堆疊中時薄膜層120係一B階環氧樹脂之實施例中，薄膜層120可與各晶粒130上之晶粒附接黏著劑132同時固化成最終C 階。在進一步實施例中，如下文所解釋，例如在模製囊封製程期間，之後可發生一B階薄膜層120及晶粒附接黏著劑132之最終固化。
晶粒堆疊及線接合、晶粒堆疊、接合線及至少一部分基板之以下安裝可在一步驟226中及如圖10中所展示囊封於一模製化合物140中。模製化合物140可包含例如固體環氧樹脂、酚樹脂、熔融石英、結晶二氧化矽、碳黑及/或金屬氫氧化物。此等模製化合物可購自(例如)總部在日本之Sumitomo及Nitto-Denko公司。採用來自其他製造者之其他模製化合物。模製化合物可根據各種已知製程施加，包含藉由轉移模製或射出模製技術。在進一步實施例中，囊封製程可藉由FFT(無流薄化)壓縮模製法來執行。
如圖10中所展示，面板上之晶粒在步驟226中囊封後，在步驟228中焊球142可焊接至各自封裝之一底部表面上之接觸墊108用於裝置係一BGA封裝之實施例。在封裝係LGA封裝之情況下，可跳過步驟226。
各自封裝可在步驟230中自面板單粒化以形成如圖10中所展示之成品半導體裝置100。各半導體裝置100可藉由各種各樣切割方法(包含鋸切、水射流切割、鐳射切割、水引導鐳射切割、乾介質切割及金剛石塗層線切割)之任何方法單粒化。雖然直線切割通常將界定矩形或方形半導體裝置100，應理解在本發明之進一步實施例中半導體裝置100可具有除了矩形及方形以外之形狀。
一旦切割封裝100，可在一步驟232中測試封裝以判定封裝是否適當運作。如技術中已知，此測試可包含電測試、預燒及其他測試。視情況在步驟234中，成品半導體裝置可包入一蓋(未展示)，例如半導體裝置係LGA封裝之情況下。
成品半導體封裝100可(例如)為一記憶體卡，諸如例如一MMC卡、一SD卡、一多用途卡、一微SD卡、一記憶體棒、一壓縮SD卡、 一ID卡、一PCMCIA卡、一SSD卡、一晶片卡、一智慧卡、一USB卡、一MCP型嵌入卡儲存器或類似物。
在上文所描述實施例中，薄膜層120可在貼附記憶體晶粒之前先固化成C階，因為底部晶粒130a包含用於將底部晶粒安裝至基板102之一晶粒附接黏著劑132。在圖11中所展示之一進一步實施例中，晶粒附接黏著劑132可自底部晶粒130a略去。在此等實施例中，底部晶粒130a可單純使用薄膜層120貼附至基板102。在此一實施例中，薄膜層在基板上形成後可固化成B階。之後，晶粒130a可定位於薄膜層120上，薄膜層加熱以軟化層，且薄膜層如上文描述固化成C階使得薄膜層120將晶粒130a接合至基板。
在上文所描述實施例中，使用薄膜層120覆蓋表面安裝控制器114及被動組件112且支撐記憶體晶粒130。在圖12所展示之一進一步實施例中，薄膜層120可支撐記憶體晶粒130且可根據上文所描述實施例(在將晶粒130定位其上之前先形成為B階或C階)之任何實施例形成。然而，在此實施例中，控制器114及/或被動組件112可定位於薄膜層120之外部之基板上。此處，薄膜層120可充當一間隔件以為表面安裝組件(諸如控制器晶粒114)在基板上提供遠離記憶體晶粒堆疊處的空間。
如上文所提及，在實施例中，薄膜層120之形狀及位置可與安裝於其上之底部晶粒130a之形狀及位置匹配。然而，在進一步實施例中薄膜層120可為各種不同形狀。圖13至圖16呈現幾個非限制性實例。在圖13及圖14中，薄膜層120與一開口150一起形成，例如在控制器晶粒114上方。開口150可為任何形狀或尺寸，或在薄膜層120之佔據面積內之任何位置。圖14及圖15展示薄膜層在若干離散區段中形成之實例。在進一步實施例中基板102上之離散區段之數目、形狀、尺寸及位置可變化。可藉由圖案化一模板提供薄膜層120之此等或其他組 態，如上文所描述，其中之孔隙如所期望，穿過孔隙薄膜層120作為一液體或糊狀物初始施加且之後固化。
總之，在一實例中，本發明係關於一半導體裝置，其包括：一基板；表面安裝至基板之一電子組件；形成於基板上之一薄膜層，電子組件至少部分嵌入薄膜層內；且至少一半導體晶粒包含具有將半導體晶粒貼附至薄膜層之一晶粒附接黏著劑之一半導體晶粒。
在一進一步實例中，本發明係關於一半導體裝置，其包括：一基板；表面安裝至基板之一電子組件；形成於基板上之一薄膜層，薄膜層與基板上之電子組件間隔開；且至少一半導體晶粒包含具有將半導體晶粒貼附至薄膜層之一晶粒附接黏著劑之一半導體晶粒。
在另一實例中，本發明係關於形成一半導體裝置之一方法，其包括步驟：(a)將一電子組件安裝於一基板上；(b)將一薄膜層施加至基板，電子組件至少部分嵌入薄膜層：在該步驟(b)中電子組件至少部分嵌入薄膜層中後(c)將薄膜層固化為至少成B階；(d)將一半導體晶粒定位於薄膜層上；及(e)將半導體晶粒貼附至薄膜層。
在一進一步實例中，本發明係關於形成一半導體裝置之一方法，其包括步驟：(a)將一控制器晶粒安裝於一基板上；(b)將一A階薄膜層施加至基板，控制器晶粒至少部分嵌入薄膜層內；在該步驟(b)中電子組件至少部分嵌入薄膜層中後(c)將薄膜層固化成C階；(d)將一半導體晶粒定位於薄膜層上，半導體晶粒包含半導體晶粒與薄膜層之間之半導體晶粒之表面上之一晶粒附接黏著劑；及(e)藉由固化晶粒附接黏著層將半導體晶粒貼附至薄膜層。
呈現本發明之先前詳細描述係用於繪示及描述目的。其並不意欲為詳盡的或將本發明限制於先前所揭示之形式。根據上文之教示，許多修改及變化都係可能的。選擇所描述實施例係為了較佳地解釋本發明之原理及其實際應用以藉此使熟習此項技術者能夠最好地利用以 各種實施例之本發明及採用適合特定用途之各種修改。本發明之範疇意欲由隨附之申請專利範圍所定義。
102‧‧‧基板
108‧‧‧接觸墊/觸點
120‧‧‧薄膜層/層/固體薄膜層
130‧‧‧半導體晶粒/晶粒/記憶體晶粒
130a‧‧‧底部晶粒/晶粒
132‧‧‧晶粒附接黏著劑

Claims (26)

  1. 一種半導體裝置，其包括：一基板；一電子組件，其經表面安裝至該基板之一外表面(external surface)；一薄膜層，其形成於該基板之該外表面上，該薄膜層係相鄰於該基板上之該電子組件且位於該電子組件之一或多側；及至少一半導體晶粒，其包含一半導體晶粒，該半導體晶粒具有將該半導體晶粒貼附至該薄膜層之一晶粒附接黏著劑。
  2. 如請求項1之半導體裝置，其中該薄膜層係一B階環氧樹脂。
  3. 如請求項1之半導體裝置，其中該薄膜層係一A階環氧樹脂。
  4. 如請求項1之半導體裝置，其中該電子組件係一控制器晶粒。
  5. 如請求項1之半導體裝置，其中該電子組件係一被動組件。
  6. 如請求項1之半導體裝置，其中該至少一半導體晶粒包括至少一記憶體晶粒。
  7. 如請求項1之半導體裝置，其進一步包括將該電子組件電耦合至該基板之接合線，該接合線嵌入該薄膜層中。
  8. 如請求項1之半導體裝置，其中該半導體裝置係一快閃記憶體封裝。
  9. 一種半導體裝置，其包括：一基板；表面安裝至該基板之一電子組件；形成於該基板上之一薄膜層，該薄膜層與該基板上之該電子組件間隔開；及 至少一半導體晶粒，其包含具有將該半導體晶粒貼附至該薄膜層之一晶粒附接黏著劑之一半導體晶粒。
  10. 如請求項9之半導體裝置，其中該薄膜層係一B階環氧樹脂。
  11. 如請求項9之半導體裝置，其中該薄膜層係一A階環氧樹脂。
  12. 如請求項9之半導體裝置，其中該薄膜層以匹配該基板上之該半導體晶粒之一形狀及位置之一形狀及位置形成於該基板上。
  13. 如請求項9之半導體裝置，其中該電子組件係一控制器晶粒與一被動組件之一者。
  14. 一種形成一半導體裝置之方法，其包括以下步驟：(a)將一電子組件安裝於一基板上；(b)將一薄膜層施加至該基板，該電子組件至少部分嵌入該薄膜層；(c)在該步驟(b)中該電子組件至少部分嵌入該薄膜層中之後將該薄膜層固化成C階；(d)將一半導體晶粒定位於該薄膜層上；及(e)將該半導體晶粒貼附至該薄膜層。
  15. 如請求項14之方法，該步驟(b)包括在該基板上印刷一液體或糊狀環氧樹脂之步驟。
  16. 如請求項14之方法，該步驟(b)包括藉由薄膜沈積及噴射式點膠之一者將一液體或糊狀環氧樹脂沈積於該基板上之步驟。
  17. 如請求項14之方法，該步驟(b)包括將一模板定位於該基板上方之步驟，該模板包含定義該基板上之該薄膜層之一形狀及位置之一孔隙，將該薄膜層施加於該模板上方及該孔隙內。
  18. 如請求項17之方法，該步驟(b)進一步包括使用一刮漿板來使該液體或糊狀物進入該模板之該孔隙內之步驟。
  19. 如請求項14之方法，該步驟(c)包括將該薄膜層固化成B階，且將 該半導體晶粒定位於該B階環氧樹脂上之該步驟。
  20. 如請求項14之方法，其中將該薄膜層固化成C階之步驟作為將該半導體晶粒貼附至該薄膜層之步驟(e)之部分發生。
  21. 如請求項14之方法，該步驟(c)包括將該薄膜層固化成C階，且將該半導體晶粒定位於該C階環氧樹脂上之步驟。
  22. 如請求項21之方法，該步驟(e)包括用與該薄膜層接觸之該半導體晶粒之一表面上形成之一晶粒附接黏著劑將該半導體晶粒貼附至該薄膜層之步驟。
  23. 一種形成一半導體裝置之方法，其包括以下步驟：(a)將一控制器晶粒安裝於一基板上；(b)將一A階薄膜層施加至該基板，該控制器晶粒至少部分嵌入該薄膜層內；(c)在該步驟(b)中該電子組件至少部分嵌入該薄膜層中後將該薄膜層固化成C階；(d)將一半導體晶粒定位於該薄膜層上，該半導體晶粒包含在該半導體晶粒與該薄膜層之間之該半導體晶粒之一表面上之一晶粒附接黏著劑；及(e)藉由固化該晶粒附接黏著層而將該半導體晶粒貼附至該薄膜層。
  24. 如請求項23之方法，該步驟(b)包括藉由絲網印刷術、薄膜沈積及噴射式點膠之一者將一液體或糊狀物施加至該基板之步驟。
  25. 如請求項23之方法，該步驟(b)包括將一模板定位於該基板上方之步驟，該模板包含定義該基板上之該薄膜層之一形狀及位置之一孔隙，該薄膜層施加於該模板上方及該孔隙內。
  26. 如請求項25之方法，該步驟(b)進一步包括使用一刮漿板來使該液體或糊狀物進入該模板之該孔隙之步驟。
TW102139867A 2013-01-09 2013-11-01 包括一用於嵌入及／或間隔半導體晶粒之獨立薄膜層之半導體裝置 TWI575670B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/070264 WO2014107848A1 (en) 2013-01-09 2013-01-09 Semiconductor device including independent film layer for embedding and/or spacing semiconductor die

Publications (2)

Publication Number Publication Date
TW201436118A TW201436118A (zh) 2014-09-16
TWI575670B true TWI575670B (zh) 2017-03-21

Family

ID=51166479

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102139867A TWI575670B (zh) 2013-01-09 2013-11-01 包括一用於嵌入及／或間隔半導體晶粒之獨立薄膜層之半導體裝置

Country Status (5)

Country Link
US (1) US9773766B2 (zh)
KR (2) KR101933364B1 (zh)
CN (1) CN104769713B (zh)
TW (1) TWI575670B (zh)
WO (1) WO2014107848A1 (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627367B2 (en) * 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
JP2016167523A (ja) * 2015-03-09 2016-09-15 株式会社東芝 半導体装置および電子機器
US9673183B2 (en) * 2015-07-07 2017-06-06 Micron Technology, Inc. Methods of making semiconductor device packages and related semiconductor device packages
CN105810661A (zh) * 2016-03-16 2016-07-27 三星半导体(中国)研究开发有限公司 集成电源模块的封装件
KR20180004413A (ko) * 2016-07-04 2018-01-12 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US20180088628A1 (en) * 2016-09-28 2018-03-29 Intel Corporation Leadframe for surface mounted contact fingers
KR102592640B1 (ko) 2016-11-04 2023-10-23 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
EP3481161A1 (en) * 2017-11-02 2019-05-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with transistor components arranged side by side
JP2019153619A (ja) * 2018-02-28 2019-09-12 東芝メモリ株式会社 半導体装置
CN110391218A (zh) * 2018-04-23 2019-10-29 晟碟半导体（上海）有限公司 具有裸芯翘起控制的半导体装置
JP2020053655A (ja) 2018-09-28 2020-04-02 キオクシア株式会社 半導体装置及び半導体装置の製造方法
KR102225956B1 (ko) * 2018-10-19 2021-03-12 세메스 주식회사 다이 본딩 장치, 기판 본딩 장치, 다이 본딩 방법 및 기판 본딩 방법
TWI665770B (zh) * 2018-12-13 2019-07-11 力成科技股份有限公司 半導體封裝結構及其製法
CN112151528A (zh) 2019-06-28 2020-12-29 西部数据技术公司 包括相对表面上的接触指的半导体装置
US11315003B2 (en) * 2019-08-14 2022-04-26 Federal Card Services, LLC RFID enabled metal transaction cards
US11094673B2 (en) * 2019-11-22 2021-08-17 Western Digital Technologies, Inc. Stacked die package with curved spacer
TWI713168B (zh) * 2020-03-09 2020-12-11 南茂科技股份有限公司 晶片封裝結構及其製造方法
US11942430B2 (en) 2021-07-12 2024-03-26 Micron Technology, Inc. Stacked die modules for semiconductor device assemblies and methods of manufacturing stacked die modules
WO2023034642A1 (en) 2021-09-06 2023-03-09 Metaland Llc Encapsulating a metal inlay with thermosetting resin and method for making a metal transaction card
US20230137512A1 (en) * 2021-11-03 2023-05-04 Western Digital Technologies, Inc. Stacked ssd semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200836306A (en) * 2007-02-16 2008-09-01 Powertech Technology Inc Multi-chip stack package
US20100027233A1 (en) * 2008-07-31 2010-02-04 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
CN102163595A (zh) * 2010-02-05 2011-08-24 海力士半导体有限公司 堆叠半导体封装

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100302593B1 (ko) 1998-10-24 2001-09-22 김영환 반도체패키지및그제조방법
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
TWI221336B (en) * 2003-08-29 2004-09-21 Advanced Semiconductor Eng Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same
JP2005275802A (ja) * 2004-03-24 2005-10-06 Omron Corp 電波読み取り可能なデータキャリアの製造方法および該製造方法に用いる基板並びに電子部品モジュール
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
KR100690960B1 (ko) 2004-06-24 2007-03-09 삼성전자주식회사 스크린 프린팅 공정을 갖는 반도체 칩 패키지 제조 방법
WO2007026392A1 (ja) 2005-08-30 2007-03-08 Spansion Llc 半導体装置およびその製造方法
US7452743B2 (en) * 2005-09-01 2008-11-18 Aptina Imaging Corporation Microelectronic imaging units and methods of manufacturing microelectronic imaging units at the wafer level
US7550834B2 (en) 2006-06-29 2009-06-23 Sandisk Corporation Stacked, interconnected semiconductor packages
US7993939B2 (en) * 2006-07-21 2011-08-09 Stats Chippac Ltd. Integrated circuit package system with laminate base
CN101026148A (zh) 2007-03-27 2007-08-29 日月光半导体制造股份有限公司 光电芯片的多芯片增层封装构造及其制造方法
CN100547607C (zh) * 2007-04-02 2009-10-07 力成科技股份有限公司 可分割记忆体磁区的模组化记忆卡装置
JP2009032013A (ja) 2007-07-26 2009-02-12 Toshiba Corp 半導体装置及びその製造方法
KR100887558B1 (ko) 2007-08-27 2009-03-09 앰코 테크놀로지 코리아 주식회사 반도체 패키지
JP4498403B2 (ja) 2007-09-28 2010-07-07 株式会社東芝 半導体装置と半導体記憶装置
US7973310B2 (en) * 2008-07-11 2011-07-05 Chipmos Technologies Inc. Semiconductor package structure and method for manufacturing the same
US7612436B1 (en) 2008-07-31 2009-11-03 Micron Technology, Inc. Packaged microelectronic devices with a lead frame
KR101060730B1 (ko) 2009-09-02 2011-08-30 에스티에스반도체통신 주식회사 적층형 ｕｓｂ 메모리 장치 및 그 제조 방법
JP2011129894A (ja) 2009-11-18 2011-06-30 Toshiba Corp 半導体装置
US8404518B2 (en) * 2009-12-13 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
JP2012129464A (ja) 2010-12-17 2012-07-05 Toshiba Corp 半導体装置およびその製造方法
US20120235188A1 (en) * 2011-03-15 2012-09-20 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Method and Apparatus for a Flat Top Light Source
JP2012216644A (ja) * 2011-03-31 2012-11-08 Toshiba Corp 半導体装置及びその製造方法
US8476111B2 (en) * 2011-06-16 2013-07-02 Stats Chippac Ltd. Integrated circuit packaging system with intra substrate die and method of manufacture thereof
KR101800440B1 (ko) * 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200836306A (en) * 2007-02-16 2008-09-01 Powertech Technology Inc Multi-chip stack package
US20100027233A1 (en) * 2008-07-31 2010-02-04 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
CN102163595A (zh) * 2010-02-05 2011-08-24 海力士半导体有限公司 堆叠半导体封装

Also Published As

Publication number Publication date
US20150221624A1 (en) 2015-08-06
WO2014107848A1 (en) 2014-07-17
US9773766B2 (en) 2017-09-26
KR20150056555A (ko) 2015-05-26
KR101933364B1 (ko) 2018-12-27
CN104769713B (zh) 2017-12-12
KR20180050436A (ko) 2018-05-14
CN104769713A (zh) 2015-07-08
TW201436118A (zh) 2014-09-16

Similar Documents

Publication Publication Date Title
TWI575670B (zh) 包括一用於嵌入及／或間隔半導體晶粒之獨立薄膜層之半導體裝置
US9240393B2 (en) High yield semiconductor device
TWI402950B (zh) 具單邊遮蓋的系統封裝模組
TWI518873B (zh) 包含交錯階梯形半導體晶粒堆疊之半導體裝置
JP2006527925A (ja) 積層された集積回路を有する集積回路パッケージおよびそのための方法
US20090085232A1 (en) Method of reducing memory card edge roughness by edge coating
CN107579061A (zh) 包含互连的叠加封装体的半导体装置
US7960209B2 (en) Semiconductor device assembly process
CN108695284A (zh) 包括纵向集成半导体封装体组的半导体设备
TWI393196B (zh) 形成用於高容量記憶卡之單層基板的方法
TWI710294B (zh) 安裝方法
JP2003298005A (ja) 半導体装置およびその製造方法
US20090140426A1 (en) Flip chip package and method for manufacturing the same
TWI518857B (zh) 用於半導體元件之線尾連接器
TWI529870B (zh) 包含一嵌入式控制器晶粒之半導體裝置及其製造方法
US8952514B2 (en) Semiconductor package
US20150214184A1 (en) Epoxy coating on substrate for die attach
US10177128B2 (en) Semiconductor device including support pillars on solder mask
JP2007134489A (ja) 半導体装置の製造方法及び半導体装置
CN106449420B (zh) 嵌埋式封装结构及其制造方法
US20100265678A1 (en) Enhancing adhesion of molding materials with substrates
CN101661927A (zh) 芯片封装
CN101661925A (zh) 芯片封装
KR20050091561A (ko) 반도체 패키지 및 그 제조 방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees