CN110391218A - 具有裸芯翘起控制的半导体装置 - Google Patents

具有裸芯翘起控制的半导体装置 Download PDF

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Publication number
CN110391218A
CN110391218A CN201810366077.9A CN201810366077A CN110391218A CN 110391218 A CN110391218 A CN 110391218A CN 201810366077 A CN201810366077 A CN 201810366077A CN 110391218 A CN110391218 A CN 110391218A
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China
Prior art keywords
bare chip
semiconductor bare
semiconductor
naked core
thickness
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CN201810366077.9A
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English (en)
Inventor
吴帅
王旭
王鑫楠
鲁鹏
王丽
陈昌恩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shengdai Semiconductor (shanghai) Co Ltd
SanDisk SemiConductor Shanghai Co Ltd
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Shengdai Semiconductor (shanghai) Co Ltd
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Application filed by Shengdai Semiconductor (shanghai) Co Ltd filed Critical Shengdai Semiconductor (shanghai) Co Ltd
Priority to CN201810366077.9A priority Critical patent/CN110391218A/zh
Priority to US15/969,272 priority patent/US10276546B1/en
Publication of CN110391218A publication Critical patent/CN110391218A/zh
Pending legal-status Critical Current

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Abstract

公开了一种具有裸芯翘起控制的半导体装置。在一个实施例中，提供了一种半导体装置，包括：衬底；堆叠在该衬底上的第一半导体裸芯；以及堆叠在该第一半导体裸芯上的多个附加的半导体裸芯，其中该多个附加的半导体裸芯以偏移配置来堆叠，使得该多个附加的半导体裸芯中的每个的边缘悬垂于其所堆叠于上的半导体裸芯的边缘之上；其中该多个附加的半导体裸芯中的最顶部半导体裸芯的厚度大于其他附加的半导体裸芯中的任何一个的厚度。提供了其他实施例。

Description

具有裸芯翘起控制的半导体装置
技术领域
本公开通常涉及半导体领域，具体地，涉及具有裸芯翘起控制的半导体装置。
背景技术
对便携式消费电子产品的需求的强劲增长推动了对高容量储存装置的需要。非易失性半导体存储器装置正被广泛用于满足对数字信息储存和交换的日益增长的需求。它们的便携性、通用性和坚固的设计连同它们的高可靠性和大容量已经使得这样的存储器装置非常适合用于各种各样的电子装置中，包括例如数码相机、数字音乐播放器、视频游戏控制台、PDA和蜂窝电话。
尽管已知许多不同的封装配置，但是闪存储存卡通常可以制造为***级封装(SiP)或多芯片模块(MCM)，其中多个裸芯被安装并互连在小足印的衬底上。通常，衬底可以包括具有在一侧或两侧上蚀刻的导电层的刚性的、介电的基底。在裸芯和(多个)导电层之间形成电连接，并且(多个)导电层提供用于将裸芯连接到主机装置的电引线结构。一旦在裸芯与衬底之间形成电连接，该装配件就可以包封在模制化合物中，该模制化合物提供了保护的封装体。
为了最有效地使用封装足印，已知的是，将半导体裸芯上下叠置，或者在相邻的裸芯之间采用间隔层的情况下将其彼此完全重叠。在偏移配置中，将裸芯堆叠在另一裸芯的顶部上，使得下部裸芯的键合垫保持暴露。偏移配置提供了便利地接入在堆叠体中的半导体裸芯中的每个上的键合垫的优点。
随着半导体裸芯变得更薄，并且为了增加半导体封装体中的存储器容量，堆叠在半导体封装体内的裸芯的数量继续增加。
发明内容
通过介绍的方式，以下实施例涉及具有裸芯翘起控制的半导体装置。在一个实施例中，提供了一种半导体装置，包括：衬底；堆叠在该衬底上的第一半导体裸芯；以及堆叠在该第一半导体裸芯上的多个附加的半导体裸芯，其中该多个附加的半导体裸芯以偏移配置来堆叠，使得该多个附加的半导体裸芯中的每个的边缘悬垂于其所堆叠于上的半导体裸芯的边缘之上；其中该多个附加的半导体裸芯中的最顶部半导体裸芯的厚度大于其他附加的半导体裸芯中的任何一个的厚度。
在一些实施例中，多个附加的半导体裸芯中的最顶部半导体裸芯的厚度足以至少部分地抵消在多个附加的半导体裸芯中的另一个中的翘起。
在一些实施例中，最顶部半导体裸芯的厚度大于约61微米。
在一些实施例中，最顶部半导体裸芯的厚度大于约76微米。
在一些实施例中，最顶部半导体裸芯的厚度大于约102微米。
在一些实施例中，第一半导体裸芯和多个附加的半导体裸芯中的至少一个包括存储器裸芯。
在一些实施例中，最顶部半导体裸芯包括无源元件和有源元件中的至少一个。
在一些实施例中，最顶部半导体裸芯没有无源元件和有源元件。
在一些实施例中，第一半导体裸芯和多个附加的半导体裸芯的总数是偶数。
在一些实施例中，第一半导体裸芯和多个附加的半导体裸芯的总数是奇数。
在另一实施例中，提供了一种制造半导体裸芯的方法。该方法包括：将第一半导体裸芯堆叠在衬底上；在该第一半导体裸芯上堆叠至少一个附加的半导体裸芯，其中该至少一个附加的半导体裸芯被堆叠，使得该至少一个附加的半导体裸芯中的每个的边缘悬垂于其所堆叠于上的半导体裸芯的边缘之上，其中包括至少一个悬垂体；以及在该至少一个附加的半导体裸芯上堆叠翘起抵消的半导体裸芯，其中该翘起抵消的半导体裸芯配置为至少部分地抵消向上翘起的至少一个悬垂体的向上翘起。
在一些实施例中，翘起抵消的半导体裸芯的厚度大于至少一个附加的半导体裸芯中的任何一个的厚度。
在一些实施例中，翘起抵消的半导体裸芯的厚度大于约61微米。
在一些实施例中，第一半导体裸芯和至少一个附加的半导体裸芯中的至少一个包括存储器裸芯。
在一些实施例中，翘起抵消的半导体裸芯包括无源元件和有源元件中的至少一个。
在一些实施例中，该方法还包括连接在衬底上的电连接垫、第一半导体裸芯和至少一个附加的半导体裸芯之间的引线键合体。
在另一实施例中，提供了一种半导体装置，包括：衬底；堆叠在衬底上的第一半导体裸芯；以及堆叠在第一半导体裸芯上的至少一个附加的半导体裸芯，其中至少一个附加的半导体裸芯被堆叠，使得至少一个附加的半导体裸芯中的每个的边缘悬垂于其所堆叠于上的半导体裸芯的边缘之上，其中包含向上翘起的至少一个悬垂体；以及用于至少部分地抵消至少一个悬垂体的向上翘起的构件。
在一些实施例中，构件包括半导体裸芯，该半导体裸芯的厚度大于至少一个附加的半导体裸芯中的任何一个的厚度。
在一些实施例中，厚度大于约61微米。
在一些实施例中，构件包括半导体裸芯，该半导体裸芯的厚度大于至少一个附加的半导体裸芯中的任何一个的厚度，并且构件包括无源元件和有源元件中的至少一个。
其它实施例是可能的，并且每个实施例可以单独使用或组合在一起使用。相应地，现在将参照附图描述各个实施例。
附图说明
图1是根据实施例的半导体装置的整个制造过程的流程图。
图2是根据实施例的在制造过程中的第一步骤处的半导体装置的侧视图。
图3是根据实施例的在制造过程中的第二步骤处的半导体装置的俯视图。
图4是根据实施例的在制造过程中的第三步骤处的半导体装置的侧视图。
图5是根据实施例的在制造过程中的第四步骤处的半导体装置的侧视图。
图6是根据实施例的在制造过程中的第五步骤处的半导体装置的侧视图。
图7和图8是实施例的裸芯翘起问题的图示。
图9A和图9B是实施例的单个裸芯堆叠体和双个裸芯堆叠体的图示。
图10是实施例的裸芯翘起解决方案的图示。
图11是实施例的具有较厚顶部裸芯的裸芯堆叠体的图示。
图12是图示了实施例的多个裸芯的堆叠体中的裸芯翘起的图。
图13是示出了实施例的第16个裸芯翘起的图。
图14是示出了实施例的16层裸芯堆叠体中的裸芯翘起的图。
具体实施方式
现在将参照图1-14描述以下实施例。可以理解的是，本发明可以以很多不同的形式来实施，而不应被解释为对本文阐述的实施例的限制。确切地说，提供这些实施例使得本公开将是透彻和完整的，并将向本领域的技术人员完全地传达本发明。实际上，本发明旨在覆盖这些实施例的替代、修改和等同，这些实施例的替代、修改和等同被包括在由所附权利要求限定的本发明的范围和精神之内。此外，在以下详细描述中，提出许多具体的细节以便提供透彻的理解。然而，对本领域的普通技术人员将清楚的是，本发明可以在没有这样的具体细节的情况下来实践。
如可以在本文中使用的术语“顶部”和“底部”、“上部”和“下部”以及“垂直”和“水平”仅是通过示例和说明性目的的方式，并不意味着限制本发明，因为所引用的项目可以在位置和取向进行交换。此外，如本文所使用的，术语“大致上”、“近似”和/或“约”意思是，指定的尺寸或参数对于给定的应用可以在可接受的制造公差内变化。在一个实施例中，可接受的制造公差为±0.25％。
现在将参照附图描述实施例。尽管一些图示出了单独的装置100或其部分，但应该理解的是，装置100可以连同衬底面板上的多个其他封装体100一起批量处理以实现规模经济。衬底面板上的封装体100的行数和列数可以变化。
衬底面板开始于多个衬底102(图2中示出了一个这样的衬底)。衬底102可以是各种不同的芯片载体介质，包括印刷电路板(PCB)、引线框架或者带自动键合(tapeautomated bonded,TAB)带。在衬底102是PCB的情况下，衬底可以由具有顶部导电层105和底部导电层107的芯103形成，如图2所示。芯103可以由各种介电材料形成，例如聚酰亚胺层压板、包括FR4和FR5的环氧树脂、双马来酰亚胺三嗪(BT)等。尽管不是严格的，但芯可以具有在40微米(μm)至200μm之间的厚度，但是在替代实施例中，层的厚度可以在该范围之外变化。在替代实施例中，芯103可以是陶瓷或有机的。
围绕芯的导电层105、107可以由铜或铜合金、镀铜或镀铜合金、合金42(42Fe/58Ni)、镀铜钢或已知用于衬底面板上的其他金属和材料来形成。导电层可以具有约10μm至25μm的厚度，但是在替代实施例中，层的厚度可以在该范围之外变化。
图1是根据实施例的用于形成半导体装置的制造过程的流程图。在步骤200中，可以钻孔衬底102以在衬底102中限定通孔过孔104。过孔104(其中在图中仅一些被编号)作为示例，并且衬底102可以包括比图中所示的更多许多的过孔104，并且它们可以处于与图中所示的不同的位置。接下来在步骤202中，在顶部导电层和底部导电层中的一个或两个上形成电导图案(conductance pattern)。(多个)电导图案可以包括电迹线106和接触垫108，如在例如图3和图4中所示的。迹线106和接触垫108(其中在图中仅一些被编号)作为示例，并且衬底102可以包括比图中示出的更多的迹线和/或接触垫，并且它们可以处于与图中所示的不同的位置。
在实施例中，完成的半导体装置100装配件可以用作BGA(球栅阵列)封装体。衬底102的下表面可以包括用于接收焊球的接触垫108，如下所述。在其他实施例中，完成的半导体装置100可以是LGA(平面栅阵列)封装体，该LGA封装体包括用于将完成的装置100可移除地耦合在主机装置内的接触指。在这样的实施例中，下表面可以包括接触指而不是接收焊球的接触垫。衬底102的顶部和/或底部表面上的电导图案可以通过各种已知的过程形成，包括例如各种光刻过程。
再次参照图1，然后可以在步骤204中以自动光学检验(AOI)来检验衬底102。一旦检验，在步骤206中就可以将焊接掩模110施加到衬底。在施加焊接掩模之后，在步骤208中，电导图案上的接触垫、接触指和任何其他焊接区域可以在已知的电镀或薄膜沉积过程中电镀有Ni/Au、合金42等。然后，可以在自动检验过程(步骤210)和最终的目视检验(步骤212)中检验和测试衬底102，以检查电操作，并且对污染、划痕和变色进行检查。
假设衬底102通过检验，则接下来可以在步骤214中将无源组件112粘附到衬底。一个或多个无源组件可以包括例如一个或多个电容器、电阻器和/或电感器，但是可以预期其他组件。所示的无源部件112(在附图中仅有一些被编号)仅作为示例，并且在其他实施例中，数量、类型和位置可以不同。如下所述，也可以使用有源元件。
在一个实施例中，在步骤220中，接下来可以在衬底102上形成半导体裸芯堆叠体。参考图5，多个半导体裸芯124可以以偏移的阶梯配置上下叠置，以形成第一裸芯堆叠体120。可以使用裸芯贴附膜将裸芯粘附到衬底和/或将裸芯彼此粘附。作为一个示例，裸芯贴附粘合剂可以是来自Henkel AG&Co.KGaA的8988UV环氧树脂，其被固化到B阶段以将裸芯124初步地粘附在堆叠体120中，并且随后被固化到最终的C阶段以将裸芯124永久地粘附在堆叠体120中。
半导体裸芯124可以例如是存储器裸芯，诸如NAND闪存裸芯，但是可以使用其他类型的裸芯124。因此，应该理解的是，虽然本文中可以使用“存储器裸芯”作为示例，但是可以使用任何适当类型的半导体裸芯。图5示出了其中八个裸芯124安装在堆叠体120中的实施例。然而，在其他实施例中，在堆叠体中可以存在多于或少于八个裸芯。此外，可以使用多个裸芯堆叠体。
在形成裸芯堆叠体120之后，可以将***层128粘附到堆叠体120中的上部裸芯124，如图5所示。***层128可以以与堆叠体120中的另一裸芯124相同的方式进行偏移并且偏移相同的范围。***层128可以是例如由FR4和FR5形成的刚性层，或例如由聚酰亚胺带形成的柔性层。电导图案形成在***层的上表面上。如下面所解释的，提供电导图案和***层是出于将来自***层128的一侧上的接触垫的信号传递到***层的相对侧上的对应的接触垫的目。现在参照图6的侧视图，一旦形成裸芯堆叠体120，堆叠体120中的相应的裸芯124就可以使用堆叠体中的裸芯到衬底102的各自的引线键合体130电连接到衬底。此后，连接控制器裸芯(步骤224)、接着是包封(步骤226)、焊球放置(步骤228)、单体化(singulation)(步骤230)、测试(步骤232)以及装在盖中(步骤234)。
如上所述，随着半导体裸芯变得更薄，并且为了增加半导体封装体中的存储器容量，堆叠在半导体封装体内的裸芯的数量继续增加。由于裸芯厚度和封装体厚度变得越来越薄，可能遇到的一个问题是半导体裸芯“翘起”(或“翘曲”)。半导体裸芯翘起是指半导体裸芯的边缘向上弯曲(“顺弯(bow)”)。通常，半导体裸芯的机械强度与其厚度成比例。因此，减小半导体裸芯的厚度会减小其机械强度。如果在生产期间，在半导体裸芯上存在净剩余拉应力，则半导体裸芯将倾向于向内推动，并且悬垂于下部半导体裸芯之上的半导体裸芯的边缘将向上弯曲。
在图7和图8中示意性地图示了半导体裸芯翘起。图7示出了安装到衬底302的第一半导体裸芯322，并且第二半导体裸芯324堆叠在第一半导体裸芯322上。如在本文中所使用的，“堆叠”或“安装”可以意指直接地堆叠或安装，或者经由一个或多个中间组件间接地堆叠或安装。在一个实施例中，第二半导体裸芯324以偏移配置堆叠，使得第二半导体裸芯324的边缘悬垂于第一半导体裸芯322的边缘之上，第二半导体裸芯324堆叠在第一半导体裸芯322上。如图7所示，第二半导体裸芯324的悬垂于第一半导体裸芯224之上的部分(“悬垂体”)向上翘起。随着堆叠的半导体裸芯的数量增加(即，裸芯翘起与半导体裸芯的数量累积)，翘起量增加，如图8所示，其中第三半导体裸芯326比第二半导体裸芯324具有更大的翘起。这种顺弯或翘曲是不希望的，因为高裸芯翘起可能导致裸芯暴露良率损失并且可能导致产品不能正常工作。随着半导体裸芯变得越来越薄并且半导体裸芯堆叠体长得越来越高，裸芯翘起变得越来越成为问题。例如，3D NAND BiCS晶片通常比2D NAND具有更厚的金属层和更高的裸芯翘曲，因此3D NAND比2D NAND更易受半导体裸芯翘起问题的影响。
可以使用若干技术来减轻(或理想地消除)半导体封装体中的由在每个半导体裸芯的与待随后引线键合的端部相对的端部处的累积的裸芯翘曲所引起的半导体裸芯翘起。例如，可以在最顶部半导体裸芯的悬垂体上分配环氧树脂柱，以试图平衡裸芯翘起。然而，在裸芯贴附之后引入分配器过程可能需要新的过程和控制方法。此外，这种方法存在潜在的可靠性风险。即，分配环氧树脂柱和模制化合物将是两步过程，并且在环氧树脂柱和模制化合物之间将存在界面。如果潮气进入界面，可能会发生可以影响可靠性的故障。作为另一示例，单个裸芯堆叠体400(图9A)可以由两个裸芯堆叠体410、420(图9B)替代，以减少裸芯翘起累积。(如图9B中所示，由于悬垂体，使用较厚的裸芯作为第九个裸芯，而其他裸芯较薄)。然而，这种方法可能存在若干缺陷。首先，这种方法可能涉及使用多次裸芯贴附过程替换一次裸芯贴附过程，并且使用两次存储器引线键合过程替换一次存储器引线键合过程。此外，这种方法可能导致接合芯片量的增加。通常，接合裸芯可能承受较高的机械应力，并且具有较高的开裂可能性。因此，接合裸芯量越高，良率损失的可能性就越大。
在一个实施例中，通过在堆叠体的顶部使用比在其下面的较薄的裸芯324、326、328更厚的裸芯328(即，在堆叠体中位于远离衬底302)来解决半导体裸芯翘起，即使在其下面的裸芯不具有均匀的厚度。(尽管在此示例中使用单个顶部较厚的裸芯，但在另一实施例中，顶部X数量个裸芯比其余的裸芯更厚，其中X>1)。顶部裸芯可以像其他裸芯一样制造，但顶部裸芯具有更大的厚度。由于具有足够高的模量而不会更厚，顶部裸芯可以至少部分地抵消在其下方的一个或多个较薄的半导体裸芯中的翘起，由此至少部分地平衡掉在其下面的薄裸芯中的一个或多个上的翘起，从而减少整体的裸芯翘起。在一个实施例中，当4-16个裸芯堆叠且薄裸芯小于约61μm时，最顶部半导体裸芯的厚度大于约61μm、76μm或102μm。当然，可以使用其他适当的厚度。通常，最顶部半导体裸芯的厚度越大，翘起控制越好。
存在几个与这些实施例相关联的优点。例如，与上面讨论的多裸芯片堆叠体方法相比，该实施例使用单向(one-way)裸芯堆叠体设计、两次裸芯贴附过程和一次存储器引线键合过程。这提供了使用单次运行引线键合程序的翘起控制，不引入附加的材料界面，并且具有整体更好的裸芯翘起控制效果，而没有上述潜在的可靠性风险。这样，这些实施例可以用于帮助制造具有较薄封装体的高容量储存产品。
这些实施例可以以任何合适的方式来实现。例如，如图10所示，存储器堆叠体中较厚的顶部裸芯可以像存储器堆叠体中的其他裸芯一样，采用引线键合体将其电连接到堆叠体中的其他裸芯。也就是说，就像在它下方的裸芯一样，顶部裸芯可以是“功能”裸芯，因为它包含任何组合的无源和/或有源元件。通过非限制性的示例，无源半导体存储器元件包含ReRAM装置元件，其在一些实施例中包含电阻率转换储存元件(诸如反熔丝、相变材料等)，并且可选地包含导向元件(诸如二极管等)。进一步通过非限制性示例，有源半导体存储器元件包含EEPROM和闪存装置元件，其在一些实施例中包含含有电荷储存区域的元件，诸如浮置栅极、导电纳米粒子、或电荷储存介电材料。在图11所示的示例中，较厚的顶部裸芯是在16-裸芯堆叠体中的第16个裸芯。
在另一实施例中，堆叠体中的较厚顶部裸芯是非功能裸芯(例如“虚设裸芯”或“镜(mirror)”)，并且仅用于提供翘起控制。在这种替代中，如果使用16-裸芯堆叠体，那么将会有16个功能裸芯，并且在顶部有一个“镜”裸芯，堆叠中共有17个裸芯(即总共为奇数而不是总共为偶数)。然而，使用功能裸芯作为最顶部的厚裸芯避免了对间隔体的需要，并且可以使得每小时高的裸芯贴附单位(DA UPH)和更低的成本(例如，镜裸芯的成本)。以16个裸芯的堆叠体作为示例，当使用功能裸芯时，总共使用16个裸芯。15x DAUPH将高于16x DA，并且不需要镜。与此相反，当使用镜裸芯代替功能裸芯时，总共将会有17个裸芯(16个功能裸芯和一个镜裸芯)。镜裸芯的使用意味着更低的UPH和更高的成本。
图12-14呈现了16-裸芯结构中的裸芯翘起的建模数据。总体上，该数据示出，随着顶部裸芯越来越厚，裸芯翘起和总的堆叠高度变得越低。更具体地说，图12示出了具有较厚的顶部裸芯的裸芯翘起控制效果更好，其中“36/10*15+102/20”选项具有最小的裸芯翘起。36是裸芯厚度，10是裸芯贴附膜厚度，以及15是裸芯的数量。102是顶部裸芯厚度，以及20是顶部裸芯的裸芯贴附厚度。
在图13和图14中，进行了四个实验(“回合(leg)”)。
回合(leg) 堆叠体 顶部裸芯
1 36/10*16 36/10
2 36/10*15+61/20 61/20
3 36/10*15+76/10 76/10
4 36/10*15+102/20 102/20
这些实验的目的是验证裸芯翘起与不同的顶部裸芯厚度之间的关系，以及确定工具的有效效果和副作用(例如拾取问题和开裂问题)。这些实验中使用的材料是BiCS3 256G虚设晶片/760 DAF：36/10μm、61/20μm、76/10μm(SKT)、102/20μm，具有DA 800和普通的摩擦尖端固定器。如图13和图14中所示，随着顶部裸芯厚度的增加，顶部裸芯翘起降低，并且最大的堆叠高度降低。另外，当顶部裸芯的厚度为102μm时，裸芯翘起和最大堆叠高度的标准偏差变小。
上述详细描述意在理解为本发明可以采取的所选择的形式的示例，而不作为本发明的限定。只有下面的权利要求(包括所有的等同)意在限定本发明要求保护的范围。最后，应该指出的是，本文中描述的任何实施例的任何方面可以单独使用或彼此组合使用。

Claims (20)

1.一种半导体装置，包括：
衬底；
堆叠在所述衬底上的第一半导体裸芯；以及
在所述第一半导体裸芯上的多个附加的半导体裸芯，其中所述多个附加的半导体裸芯以偏移配置来堆叠，使得所述多个附加的半导体裸芯中的每个的边缘悬垂于其所堆叠于上的所述半导体裸芯的边缘之上；
其中所述多个附加的半导体裸芯中的最顶部半导体裸芯的厚度大于其他附加的半导体裸芯中的任何一个的厚度。
2.如权利要求1所述的半导体装置，其中所述多个附加的半导体裸芯中的最顶部半导体裸芯的厚度足以至少部分地抵消在所述多个附加的半导体裸芯中的另一个中的翘起。
3.如权利要求1所述的半导体装置，其中所述最顶部半导体裸芯的厚度大于约61微米。
4.如权利要求3所述的半导体装置，其中所述最顶部半导体裸芯的厚度大于约76微米。
5.如权利要求4所述的半导体装置，其中所述最顶部半导体裸芯的厚度大于约102微米。
6.如权利要求1所述的半导体装置，其中所述第一半导体裸芯和所述多个附加的半导体裸芯中的至少一个包括存储器裸芯。
7.如权利要求1所述的半导体装置，其中所述最顶部半导体裸芯包括无源元件和有源元件中的至少一个。
8.如权利要求1所述的半导体装置，其中所述最顶部半导体裸芯没有无源元件和有源元件。
9.如权利要求1所述的半导体装置，其中所述第一半导体裸芯和所述多个附加的半导体裸芯的总数是偶数。
10.如权利要求1所述的半导体装置，其中所述第一半导体裸芯和所述多个附加的半导体裸芯的总数是奇数。
11.一种制造半导体裸芯的方法，所述方法包括：
将第一半导体裸芯堆叠在衬底上；
在所述第一半导体裸芯上堆叠至少一个附加的半导体裸芯，其中所述至少一个附加的半导体裸芯被堆叠，使得所述至少一个附加的半导体裸芯中的每个的边缘悬垂于其所堆叠于上的所述半导体裸芯的边缘之上，其中包括至少一个悬垂体；以及
在所述至少一个附加的半导体裸芯上堆叠翘起抵消的半导体裸芯，其中所述翘起抵消的半导体裸芯配置为至少部分地抵消向上翘起的所述至少一个悬垂体的向上翘起。
12.如权利要求11所述的方法，其中所述翘起抵消的半导体裸芯的厚度大于所述至少一个附加的半导体裸芯中的任何一个的厚度。
13.如权利要求11所述的方法，其中所述翘起抵消的半导体裸芯的厚度大于约61微米。
14.如权利要求11所述的方法，其中所述第一半导体裸芯和所述至少一个附加的半导体裸芯中的至少一个包括存储器裸芯。
15.如权利要求11所述的方法，其中所述翘起抵消的半导体裸芯包括无源元件和有源元件中的至少一个。
16.如权利要求11所述的方法，还包括连接在所述衬底上的电连接垫、所述第一半导体裸芯和所述至少一个附加的半导体裸芯之间的引线键合体。
17.一种半导体装置，包括：
衬底；
堆叠在所述衬底上的第一半导体裸芯；以及
堆叠在所述第一半导体裸芯上的至少一个附加的半导体裸芯，其中所述至少一个附加的半导体裸芯被堆叠，使得所述至少一个附加的半导体裸芯中的每个的边缘悬垂于其所堆叠于上的所述半导体裸芯的边缘之上，其中包括向上翘起的至少一个悬垂体；以及
用于至少部分地抵消所述至少一个悬垂体的向上翘起的构件。
18.一种半导体装置，包括：
衬底；
堆叠在所述衬底上的第一半导体裸芯，所述第一半导体裸芯具有与所述第一半导体裸芯的正交边缘平行地限定的x轴和y轴；以及
安装在所述第一半导体裸芯上的多个附加的半导体裸芯，其中所述多个附加的半导体裸芯具有与所述多个附加的半导体裸芯的正交边缘平行地限定的x轴和y轴，进一步地，其中所述多个附加的半导体裸芯中的每个被安装为沿着所述x轴相对于所述第一半导体裸芯偏移；
其中所述多个附加的半导体裸芯中的最顶部半导体裸芯的厚度大于其他附加的半导体裸芯中的任何一个的厚度。
19.如权利要求18所述的半导体装置，其中所述厚度大于约61微米。
20.如权利要求18所述的半导体装置，其中所述多个附加的半导体裸芯中的最顶部半导体裸芯的厚度足以至少部分地抵消在所述多个附加的半导体裸芯中的另一个中的翘起。
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