TWI569341B - 引線連結感測器封裝體及方法 - Google Patents
引線連結感測器封裝體及方法 Download PDFInfo
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- TWI569341B TWI569341B TW104125084A TW104125084A TWI569341B TW I569341 B TWI569341 B TW I569341B TW 104125084 A TW104125084 A TW 104125084A TW 104125084 A TW104125084 A TW 104125084A TW I569341 B TWI569341 B TW I569341B
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Description
本申請案主張在2014年8月18日提出申請之美國臨時申請案第62/038,429號的利益,該美國臨時申請案是被併入於此中作為參考。
本發明係有關於封裝積體電路(半導體)晶片。
一積體電路晶片藉由使用打線來把該積體電路晶片連接到一基板來安裝於該基板上在晶片封裝工業上業已是主要的做法。由於更輕薄行動裝置的消費者需求持續成長,晶片封裝結構在尺寸上也必須縮減,尤其是封裝體高度,以符合輕薄裝置趨勢。
一種習知封裝方案是在美國公告申請案2003/0201535號案中揭示,而且是被顯示在圖1中。該封裝體1包括一接合至一有機封裝基板3的影像感測器晶片2,其中,該晶片2是以接合導線4電氣連接到該基板3。該等接合導線4是以樹脂5包封而然後在保留晶片2之活性區域7露出時再次以包封劑6包封。該活性區域7是由一透明元件8封閉。
該影像感測器晶片2是以黏著劑9連接到基體3。去封裝導電性(Off package electrical conductivity)是利用錫球10達成。
這封裝體結構的問題是為其之尺寸,特別是其之高度,無法如希望一樣縮減。
前述的問題和需求是由一封裝晶片總成解決,該封裝晶片總成包含一包括一具有第一頂表面和第一底表面且由半導體材料形成之第一基體的半導體晶片、一體地形成在該第一頂表面上或中的一半導體裝置、及位於該第一頂表面且電氣耦合到該半導體裝置的數個第一銲墊。一第二基體包括第二頂表面和第二底表面,一延伸在該第二頂表面與第二底表面之間的第一孔洞、一個或多個延伸在該第二頂表面與第二底表面之間的第二孔洞、位於該第二頂表面的數個第二銲墊、位於該第二底表面的數個第三銲墊、及電氣耦合到該等第二銲墊和該等第三銲墊的數個導體。該第一頂表面是被鎖固到該第二底表面,致使該半導體裝置與該第一孔洞對準,而該等第一銲墊中的每一者是與該一個或多個第二孔洞對準。數條導線,各電氣連接在該等第一銲墊中之一者與該等第二銲墊中之一者之間且是各通過該一個或多個第二孔洞中之一者。
一封裝晶片總成包含一包括一具有第一頂表面和第一底表面且由半導體材料形成的第一基體、一體地形成在該第一頂表面上或中的一半導體裝置、位於該第一頂
表面且電氣耦合到該半導體裝置的數個第一銲墊、一個或多個於該第一頂表面中所形成的溝渠、及數個導電軌跡,各具有一電氣連接到該等第一銲墊中之一者之第一部份、一延伸在該第一頂表面之上且是與該第一頂表面隔絕之第二部份、及一向下延伸至該一個或多個溝渠內之第三部份。一第二基體包括第二頂表面和第二底表面,位於該第二頂表面的數個第二銲墊、位於該第二底表面的數個第三銲墊、及電氣耦合到該等第二銲墊和到該等第三銲墊的導體。該第一底表面是被鎖固到該第二頂表面。數條導線,各電氣連接在該等數個導電軌跡中之一者之第三部份中之一者與該等第二銲墊中之一者之間。
一種形成封裝晶片總成的方法,包含提供一半導體晶片、提供一第二基體、把它們鎖固在一起、及把它們電氣連接在一起。該半導體晶片包括一具有第一頂表面與第一底表面之由半導體材料形成的第一基體、一體地形成於該第一頂表面上或中的一半導體裝置、及位在該第一頂表面且電氣耦合到該半導體裝置的數個第一銲墊。該第二基體包括第二頂表面與第二底表面、一延伸在該第二頂表面與第二底表面之間的第一孔洞、一個或多個延伸在該第二頂與第二底表面之間的第二孔洞、位在該第二頂表面的數個第二銲墊、位在該第二底表面的數個第三銲墊、及電氣耦合到該等第二銲墊與該等第三銲墊的數個導體。該鎖固包括把該第一頂表面鎖固到該第二底表面,致使該半導體裝置與該第一孔洞對準,而且該等第一銲墊中之每一者
與該一個或多個第二孔洞中之一者對準。該電氣連接包括電氣連接數條導線中之每一者在該等第一銲墊中之一者與該等第二銲墊中之一者之間,其中,該數條導線中之每一者通過該一個或多個第二孔洞中之一者。
一種形成封裝晶片總成的方法包括提供一半導體晶片(其包括一具有第一頂表面和第一底表面之由半導體材料形成的第一基體、一體地形成於該第一頂表面上或中的一半導體裝置、及位於該第一頂表面電氣連接到該半導體裝置的數個第一銲墊)、形成一個或多個溝渠至該第一頂表面中、形成數個導電軌跡,各具有一電氣連接到該等第一銲墊中之一者之第一部份、一延伸在該第一頂表面之上且與該第一頂表面隔絕之第二部份、及一向下延伸至該一個或多個溝渠中之一者內之第三部份、提供一第二基體(其包括第二頂表面和第二底表面、位於該第二頂表面的數個第二銲墊、位於該第二底表面的數個第三銲墊、及電氣耦合到該等第二銲墊和到該等第三銲墊的數個導體)、把該第一底表面鎖固到該第二頂表面、及將數條導線中之每一者電氣連接在該等數個導電軌跡中之一者之第三部份中之一者、與該等第二銲墊中之一者之間。
本發明的其他目的與特徵將會藉由審視該說明書、申請專利範圍及附圖而變得清楚明白。
1‧‧‧封裝體
2‧‧‧影像感測器晶片
3‧‧‧有機封裝基板
4‧‧‧接合導線
5‧‧‧樹脂
6‧‧‧包封劑
7‧‧‧活性區域
8‧‧‧透明元件
9‧‧‧黏著劑
10‧‧‧錫球
20‧‧‧扇出型基板
22‧‧‧導體
24,26‧‧‧銲墊
28,30‧‧‧孔洞
32‧‧‧基板
34‧‧‧黏著劑
36‧‧‧晶片
38‧‧‧半導體基體
40‧‧‧活性區域
42‧‧‧半導體裝置
44‧‧‧接合銲墊
46‧‧‧黏著劑
48‧‧‧空穴
50‧‧‧導線
52‧‧‧包封劑
54‧‧‧互連件
56‧‧‧封裝晶片總成
58‧‧‧主機板
60‧‧‧接觸銲墊
62‧‧‧導體
70‧‧‧光阻
72‧‧‧溝渠
74‧‧‧光阻
76‧‧‧鈍化層
78‧‧‧光阻
80‧‧‧導電材料
82‧‧‧光阻
84‧‧‧黏著劑
86‧‧‧包封劑黏著材料
88‧‧‧劃線
90‧‧‧電氣裝置
92‧‧‧連接器
96‧‧‧孔
98‧‧‧互連件
100‧‧‧接合銲墊
102‧‧‧接合銲墊
104‧‧‧介電材料
圖1是為一習知半導體封裝體的側視橫截面圖。
圖2A-2I是為描繪在形成本發明之封裝晶片總成
中之步驟的側視橫截面圖。
圖3A從側視與上視橫截面方向描繪該封裝晶片總成之元件的關聯。
圖3B從側視與下視橫截面方向描繪該封裝晶片總成之元件的關聯。
圖4是為一描繪被安裝到一主基體之封裝晶片總成的側視橫截面圖。
圖5A-5M是為描繪在形成本發明之封裝晶片總成之另一實施例中之步驟的側視橫截面圖。
圖6是為一描繪被安裝到一主基體之封裝晶片總成之另一實施例的側視橫截面圖。
圖7和8是為描繪被安裝到一主基體之封裝晶片總成之另一實施例的上視圖。
圖9是為一描繪被安裝到一主基體之封裝晶片總成之另一實施例的側視橫截面圖。
本發明是為一提供超越現存封裝解決方案之實質厚度優勢的封裝晶片總成。整體封裝體高度能夠藉由透過改進的扇出型封裝體結構及對晶粒幾何的變化來使接合導線迴圈高度最佳化來被縮減。
圖2A-2I描繪封裝晶片總成的形成,其以製作或提供一扇出型基板20開始,該扇出型基板20可以由硬或可撓材料製成,諸如陶瓷、聚醯亞胺、FR4、BT、半導體矽、
玻璃、或任何其他眾所周知的中介層基板材料。基板20可以是單或多-層,具有至少一個包含電氣導體22的電氣佈線層。電氣導體22的佈局/設計可以是隨機或者偽隨機,以及晶粒佈局/設計的高度獨立。該等電氣佈線導體22電氣連接在該基板之頂表面上的導線接合銲墊24俾互連在該基板之底表面上的(接合)銲墊26,如在圖2A中所示。如果該基板20是由導電材料製成的話,那麼導體22與銲墊24/26是藉著絕緣材料來與該基板材料隔離。
一活性區域孔洞28是被形成貫穿基板20(其會與在下面所討論之半導體晶片的活性區域對準)。數個接合銲墊孔洞30也是被形成貫穿該基板20(其會與在下面所討論之半導體晶片的接合銲墊對準)。最好的是該等孔洞28和30不與導體22、導線接合銲墊24和互連銲墊26中之任一者衝突,如在圖2B中所示。孔洞28,30能夠利用一打孔器、CNC路徑規劃器、蝕刻或任何其他合適的切割方法來被形成。該等孔洞28,30可以具有斜或垂直側壁。圖2C和2D描繪基板20之孔洞與銲墊的兩種不同佈局結構。在每一結構中,每一接合銲墊孔洞30會是與半導體晶片之複數接合銲墊對準。
一基板32是利用黏著劑34來貼附到該基板20。基板32延伸在孔洞28之上,如在圖2E中所示。為了具有光學作用區域的半導體晶片(在下面討論),基板32能夠為光學上透明或半透明。就如此的應用而言,基板32能夠為聚甲基丙烯酸甲酯(poly(methyl methacrylate))、玻璃、藍寶石、
聚碳酸酯或任何其他透明或半透明材料。最好的是,該基板是光學上透明玻璃。該基板32的較佳厚度是處於50μm至1000μm的範圍內。該基板32可以被塗佈有耐刮耐衝擊塗層、抗油性塗層、諸如IR,AR般的一個或多個光學層或任何其他合適的光學層。藉由施加切割膠帶到該基板32之上(其保護該基板32並且在切割製程期間固持住它),並且利用機械切割、蝕刻、雷射或任何其他眾所周知的切割方法來切割該基板,基板32能夠被切割成適當尺寸(在尺寸上最好是稍微大於孔洞28)。藉著UV去活化(UV deactivation)和取放製程(pick and place process)該經切割基板32能夠脫離該切割膠帶。黏著劑34可以是一聚合物、環氧樹脂、樹脂或任何其他合適的接合劑。例如,環氧樹脂基黏著材料能夠利用一注射系統來被分配到基板32上。一取放系統能夠被使用來把基板32置於基板20上。
一半導體晶片36接著被提供,如在圖2F中所示。晶片36包括一半導體基體38,及在該基體之上(頂)表面之包含一諸如影像感測器、紅外線感測器、光線感測器等等般之半導體裝置42的活性區域40。在該基體之頂表面的接合銲墊44是直接地或間接地電氣耦合到該半導體裝置42(即,for off chip conductivity)。該晶片36可以是,例如,由一包含複數個半導體裝置42的晶圓製成,其中,在該晶圓被切割成個別晶片36之前,切割膠帶是被施加在該晶圓的頂表面之上,在那之後該晶圓能夠被薄化(自底表面蝕刻--該晶圓最好被薄化到150μm或以下)。諸如晶片36般的晶片在習
知技藝中是眾所周知的而於此中不再作進一步描述。
黏著劑46然後被沉積在基板20及/或基體38上。黏著劑46可以是聚合物、環氧樹脂、樹脂、黏晶膠帶、或任何其他在習知技藝中是眾所周知的合適接合劑或方法。例如,環氧樹脂基黏著劑可以利用一注射系統來被分配到該基板20上。晶片36是藉由利用取放製程來被取放到該基板20上,藉此黏著劑46把該基板20的底表面牢貼到該晶片36的頂表面以致於一氣閉性密封空穴48是被形成在該活性區域40與基板32之間。最終結構是被顯示在圖2G中。
如在圖2H中所示導線50被使用來把晶片36連接到基板20。具體地,每一導線50具有一個連接到(基板20之)接合銲墊24中之一者的末端和另一個連接到(晶片36之)接合銲墊44中之一者的末端。這些連接把來自裝置42的訊號供應到導體22及到互連銲墊26。一迴圈高度(即,在基板20/38之上表面之上之迴圈導線50的最高點)最好是比基板32的頂表面低。包封劑52然後被沉積在該等導線50和銲墊24/44之上。最好的是,包封劑材料52的上表面是比該等導線50的迴圈高度高但比基板32的頂表面低。最好的是包封劑52也被沉積在晶片基板38的邊緣之上及在基板20的底表面上。包封劑52的用途是為密封與保護在下面的結構。然後,互連件54形成於該基板20的互連銲墊26上。互連件54可以是例如球柵陣列(BGA)、島柵陣列(LGA)、或任何其他合適的互連件方法。BGA是較理想的類型中之一者而且是被顯示在圖式中。BGA互連件54能夠藉由錫球噴射製程
(solder ball jetting process)或錫球落下製程(solder ball drop process)來被形成在基板20上。該BGA互連件54應向下延伸比晶片36的底表面及在其上的包封劑52低,俾致使容易連接到BGA互連件54。最終的封裝晶片總成56是被顯示在圖2I中。
圖3A從側視與頂視橫截面圖顯示封裝晶片總成56之元件的關聯。圖3B從側面與底面顯示封裝晶片總成56之元件的關聯。圖4顯示被安裝到一主基板58的封裝晶片總成56(例如,使用SMT製程)。該主基板58可以是為具有接觸銲墊60(與互連件54和導體62電氣接觸)的硬或可撓印刷電路板或任何其他類型的主基板。
關於該封裝晶片總成56,該半導體晶片36是連接到該基板20,藉此在接觸銲墊44上之晶片的電氣訊號是經由導線50被發送到銲墊24,透過導體22,到互連銲墊26和連接到其那裡的互連件54。基板20包括用於使晶片36之銲墊44保持露出以允許打線製程的孔洞30。該基板20也包括用於使晶片36之活性區域40保持露出以允許該活性區域40(與在其中的半導體裝置42)接收光線或其他感測能量的活性區域孔洞28。該基板32是連接在基板20的頂側之上,因此氣密地密封和保護該晶片活性區域40。該基板20在底側具有用於把封裝晶片總成56安裝到主基板58的互連件26。因為該晶片36被接合到該基板20的底側佔用當利用諸如BGA般之互連件安裝該總成到主基板時正常是被浪費之空間的部份,實質高度降低是能夠被達成。此外,接合導線
50通過該基板20,因此與現存封裝解決方案比較起來更縮減高度輪廓。這結構對於影像感測器、IR感測器、光線感測器或任何其他光學相關感測器來說是特別理想的。
圖5A-5M描繪封裝晶片總成之另一實施例的形成。可比或相類似組件將會由相同的元件編號標示。除了依然處於晶圓態樣之外,該形成是從以上所述之半導體晶片36的提供開始(即,數個晶片36形成在一單一晶圓基體38上,在選擇地薄化之後,以及在切割之前),如在圖5A中所示。光阻70是被沉積在該基體38的活性側上,覆蓋該活性區域40和該等接合銲墊44。光阻70能夠以旋塗、噴塗、乾薄膜或者任何其他合適的光阻沉積方法來被沉積。光阻70被顯影(即,利用光刻曝光與蝕刻製程來被曝光和選擇地移除),其圖案化該光阻以露出在兩相鄰晶粒之間的矽基體38(但沒有露出活性區域40和接合銲墊44),如在圖5B中所示。
基體38的露出部份是利用各向異性乾蝕刻來被蝕刻以形成溝渠72到基體38的頂表面內。蝕刻劑可以是例如CF4、SF6或任何其他合適的蝕刻劑。溝渠72的壁最好,但不是必要,是斜的。溝渠72能夠被形成在活性區域40及其相關接合銲墊44的全部四個側、三個側、兩個側或一個側上。最好的是,溝渠72的深度不超過基體38之垂直高度的75%。圖5C顯示最終結構,在光阻70被移除之後。
光阻74然後被沉積在該基體38的活性側上,而且是被顯影(即,被曝光和選擇地移除),其圖案化光阻74俾
露出該矽基體38(但保留剛好設置在活性區域40與接合銲墊44之上而不是在其間之區域的光阻74),如在圖5D中所示。鈍化層(即,絕緣材料)76是被沉積在該結構上。該鈍化層76可以是二氧化矽、氮化矽、鈦、前述鈍化層的組合或任何其他合適的矽鈍化電氣絕緣材料。鈍化層76可以是而且最好是利用物理氣相沉積(PVD)來被沉積。最終結構是被顯示在圖5E中(在光阻74的移除之後)。
光阻78然後是被沉積在半導體裝置晶圓的活性側上,而且是被顯影(即,被曝光和選擇地移除),僅保留在活性區域40之上的光阻78。一層導電材料80是被沉積在該鈍化層76和光阻78之上。該導電材料層80可以是銅、鋁或任何其他合適的導電材料,而且可以利用物理氣相沉積(PVD)、電鍍或任何其他合適的沉積方法來被沉積。最好的是,該導電材料層80是為銅而且是藉濺鍍而然後電鍍來被沉積。光阻82然後是被沉積在導電層80之上,而且是被顯影(即,被曝光和選擇地移除),保留光阻82原封不動除了在活性區域40之上以及位於溝渠72之中央或附近的之外,如在圖5F中所示。蝕刻然後是被使用來移除導電層80的露出部份,保留導電材料之向從接合銲墊44中之一者向下延伸至溝渠72中之一者內的軌跡80,如在圖5G中所示(在光阻82和78被移除之後)。軌跡80是與接合銲墊44電氣接觸,但卻是由於鈍化層76而與基體38隔絕,藉此把該等接合銲墊44電氣佈線至溝渠72內。
基板32是直接連接到活性區域40之上,如在圖
5H中所示。如上所述,基板32可以是聚甲基丙烯酸甲酯(poly(methyl methacrylate))、玻璃、藍寶石、聚碳酸酯或任何其他合適材料,可以是光學上透明或半透明,而且可以是被塗佈有耐刮耐衝擊塗層、抗油性塗層、諸如IR、AR般的一個或多個光學層或任何其他合適的光學層。基板32是利用可以為光學上透明/半透明的接合黏著劑84來被連接。黏著劑84可以是利用注射沉積製程來被沉積在活性區域40上或在基板32上,而然後該基板32是直接連接到該活性區域40。如同在先前所述的實施例中一樣,在基板32與活性區域40之間是無間隙或空穴。
假如基板32是直接安裝到活性區域40,基板32可以是藍寶石,而且更具體地為複數片在不同晶體平面方向層疊的單一晶體藍寶石。很多層的藍寶石片是利用熔合(fusion)、黏著或任何其他合適的接合技術來被接合。選擇地,該多層藍寶石基板32可以包含一導電柵格(conductive grid)、一導電網格(conductive mesh)、或者一懸浮導電粒子層(suspended conductive particle layer)。這導電層可以被連接到一接地元件以防止對半導體裝置42的靜電放電(ESD)損害。這導電層也能夠被設計來加強該裝置的散熱速率。藍寶石由於其之硬度、耐久性以及防刮而會是合意的。這些實力(strengths)在藍寶石片在不同平面方位上堆疊時是能夠被加強。由於這些實力,矽晶粒能夠被較佳地保護免於諸如指壓般的物理力。藍寶石的優異實力允許它比諸如玻璃般的其他材料更薄。該藍寶石基板厚度可以是100
μm到1000μm而且依然提供晶片36適足的保護。較薄的藍寶石允許一個整體較薄裝置,而且允許該活性區域40更敏感。當半導體裝置42是為一用於指紋確認之手指越接近活性區域40越佳的電容性感測器時,這會是尤其重要的。藍寶石最好是在被安裝到晶片36之前利用一雷射切割製程來被切割。
圖5I顯示一用於安裝基板32到晶片36上的另一實施例,其中,無黏著劑被沉積在基板32與晶片36的活性區域40之間,其會改進該活性區域敏感度、減低光學或觸覺損失、以及減低整體裝置高度。該基板32在其之側面是連接有藉著注射方法沉積,最好是在真空下沉積的包封劑/黏著材料86。該材料86最好是比該基板32的頂表面低。
晶圓級切割/切片然後是沿著通過溝渠72的劃線88執行,得到如在圖5J中所示之個別的半導體晶片36。切片能夠由機械切割、雷射切割、化學蝕刻或任何其他合適製程執行。單片晶片36然後是被接合到上述之基板20的頂表面,但在這實施例中基板20不包含孔洞28和30而且晶片36不被接合到基板20的底表面。導線50被用來把晶片36連接到基板20。具體地,每一導線50具有一個末端連接到(基板20之)該等接合銲墊24中之一者和另一個末端連接到在該等溝渠72中之一者內之(晶片36之)該等軌跡80中之一者。這些連接使得來自裝置42的訊號,通過接合銲墊42、軌跡80、導線50、接合銲墊24、導體22並且到互連銲墊26上。迴圈高度(即,迴圈導線50的最高點)最好是比基板32
的頂表面低。該迴圈高度可以被做得比溝渠72的深度更低(與不必從接合銲墊44行走導線50及/或沿著基體38的頂表面行走之軌跡80的任何部份比較起來)。包封劑52然後被沉積在導線50、接合銲墊24與軌跡80之上。最好的是,包封劑材料52的頂表面是比基板32的頂表面低,但比導線50的峰高度高一若干量(例如,5μm),如在圖5K中所示。包封劑52能夠利用注射、射出成型或任何其他合適之眾所周知的包封製程來被沉積。最好的是,沉積方法是為射出成型。
互連件54然後是被形成在基板20的互連銲墊26上。互連件54可以是例如如在圖5L中所示的球柵陣列(BGA)、如在圖5M中所示的島柵陣列(LGA)、或者任何其他合適的互連技術。該封裝晶片總成56然後被安裝在主基板58上(例如,使用SMT製程),如在圖6中所示。圖7和8顯示能夠被安裝/連接到主基板58之其他組件的範例,包括諸如處理器、記憶體、電容器等等的電氣裝置90,以及供基板58用的連接器92。這實施例結構給定基板32與半導體裝置42的接觸(直接或透過黏著劑84)對於生物特徵識別半導體裝置來說是理想的。
圖9描繪在圖2I中所示之實施例的另一實施例。取代包括電氣佈線導體22在其內(用於把在基板之頂表面上的導線接合銲墊24電氣連接來互連(接合)在基板之底表面上的銲墊26)的基板20,基板20能夠由諸如導電半導體材料或玻璃材料般的固體材料製成。在這實施例中的基板20包括延伸在基板20之頂表面與底表面之間的孔96。導
電材料是被沉積在孔96內以形成延伸通過基板20的電氣互連件98。導線50連接到在基板20之頂表面附近的電氣互連件98(直接或使用接合銲墊100),而互連件54連接到在基板之底表面附近的電氣互連件98(直接或使用接合銲墊102)。
電氣互連件98是藉著一層兼容介電材料104來與基板20隔絕。一兼容介電材料是為一在所有三個垂直方向上展現兼容性的相對軟性材料(例如,防焊劑),而且能夠適應在諸如半導體結晶(~2.6ppm/℃)般之基板材料與諸如Cu(~17ppm/℃)般之互連件材料之間不匹配的熱膨脹係數(CTE)。兼容介電材料104最好是聚合物,諸如BCB(苯並環丁烯(Benzocyclobutene))、防焊劑、阻焊劑、FR4、模鑄化合物、或者BT環氧樹脂般。在基板20是由導電半導體材料製成的情況中該兼容介電材料104作用來使電氣互連件98與基板20電氣地隔絕(所以該兩者不電氣地短路在一起)。在基板20是由玻璃製成的情況中兼容介電材料104作用來減低在基板20上的金屬應力。
應要理解的是本發明不受限為上述以及於此中所描繪的實施例,而是涵蓋落在後附申請專利範圍之範圍之內的所有變化。例如,於此中對本發明的參照不傾向於限制任何申請專利範圍或者申請專利範圍項目的範圍,取而代之的是僅達成對會由申請專利範圍中之一者或多者所覆蓋之一個或多個特徵的參照。上述之材料、製程與數值範例是僅為例證而已,而不應被認為限制該等申請專利範
圍。此外,從該等申請專利範圍與說明書很顯而易知,不是所有方法步驟需要按照所描繪或主張的確切順序來被執行,而是能夠以任何允許本發明之封裝晶片總成之合適形成的順序執行。最後,單層的材料能夠被形成為複數層如此或相似材料,反之亦然。
應要注意的是,如於此中所使用,該等用語"在..之上"和"在...上"皆含括地包括"直接地在...上"(無中間材料、元件或空間設置於其間)及"非直接地在....上"(中間材料、元件或空間設置於其間)。同樣地,該等用語"相鄰"包括"直接相鄰"(無中間材料、元件或空間設置於其間)和"非直接相鄰"(中間材料、元件或空間設置在其間)、"被安裝到"包括"直接安裝到"(無中間材料、元件或空間設置於其間)及"非直接安裝到"(中間材料、元件或空間設置於其間)、及"電氣地耦合"包括"直接電氣地耦合到"(無把該等元件電氣連接在一起的中間材料、元件或空間設置於其間)及"非直接電氣地耦合到"(把該等元件電氣連接在一起的中間材料、元件或空間設置於其間)。例如,形成一元件"在一基板之上"能夠包括形成該元件直接在該基板上,無中間材料/元件在其間,以及形成該元件非直接在該基板上,有一個或多個中間材料/元件在其間。
20‧‧‧基板
22‧‧‧導體
24‧‧‧銲墊
26‧‧‧銲墊
32‧‧‧基板
34‧‧‧黏著劑
36‧‧‧晶片
38‧‧‧半導體基體
40‧‧‧活性區域
42‧‧‧半導體裝置
44‧‧‧接合銲墊
46‧‧‧黏著劑
48‧‧‧空穴
50‧‧‧導線
52‧‧‧包封劑
54‧‧‧互連件
56‧‧‧封裝晶片總成
Claims (24)
- 一種封裝晶片總成,包含:一半導體晶片包括:由半導體材料形成的一第一基體,其具有第一頂表面與第一底表面,一體地形成於該第一頂表面上或中的一半導體裝置,且位於該第一頂表面的數個第一銲墊,其電氣耦合到該半導體裝置;一第二基體包括:第二頂表面和第二底表面,延伸在該第二頂表面與第二底表面之間的一第一孔洞,延伸在該第二頂表面與第二底表面之間的一個或多個第二孔洞,位於該第二頂表面的數個第二銲墊,位於該第二底表面的數個第三銲墊,及電氣耦合到該等第二銲墊和該等第三銲墊的數個導體;其中,該第一頂表面是被鎖固到該第二頂表面,致使該半導體裝置與該第一孔洞對準,而且該等第一銲墊中之每一者是與該一個或多個第二孔洞中之一者對準;及 數條導線,各電氣連接在該等第一銲墊中之一者與該等第二銲墊中之一者之間且各通過該一個或多個第二孔洞中之一者。
- 如請求項1之總成,更包含:被鎖固到該第二頂表面且覆蓋該第一孔洞的一第三基體。
- 如請求項2之總成,其中,該第三基體是光學上透明或者半透明的。
- 如請求項3之總成,其中,該半導體裝置是為一影像感測器、一紅外線感測器、與一光線感測器中之一者。
- 如請求項1之總成,更包含:覆蓋該等導線並充填該一個或多個第二孔洞的包封劑。
- 如請求項1之總成,更包含:沿著該第一基體的側壁從該第二底表面延伸,並到達該第一底表面的包封劑。
- 如請求項1之總成,更包含:一第三基體包括:第三頂表面與第三底表面,及位於該第三頂表面的第四銲墊;各把該等第三銲墊中之一者電氣耦合至該等第四銲墊中之一者的數個電氣互連件。
- 如請求項1之總成,更包含:數個延伸在該第二頂表面與該第二底表面之間的孔 洞,其中,該等導體是為在該數個孔洞內的導電材料,各延伸在該等第二銲墊中之一者與該等第三銲墊中之一者之間。
- 一種封裝晶片總成,包含:一半導體晶片包括:由半導體材料形成的一第一基體,其具有第一頂表面與第一底表面,一體地形成於該第一頂表面上或中的一半導體裝置,位於該第一頂表面的數個第一銲墊,其電氣耦合到該半導體裝置,一個或多個於該第一頂表面中所形成的溝渠,及數個導電軌跡,各具有電氣連接到該等第一銲墊中之一者之一第一部份、延伸在該第一上表面上且是與該第一上表面隔絕的一第二部份、和向下延伸至該一個或多個溝渠中之一者之一第三部份;一第二基體包括:第二頂表面和第二底表面;位於該第二頂表面的數個第二銲墊,位於該第二底表面的數個第三銲墊,及電氣耦合到該等第二銲墊和該等第三銲墊的數個導體;其中,該第一底表面被鎖固到該第二頂表面;及 數條導線,各電氣連接在該等數條導電軌跡中之一者之第三部份中之一者與該等第二銲墊中之一者之間,以及一第三基體包括:第三頂表面與第三底表面,及位於該第三頂表面的數個第四銲墊;數個電氣互連件,各把該等第三銲墊中之一者電氣耦合到該等第四銲墊中之一者。
- 如請求項9之總成,更包含:被鎖固到該第一頂表面且是設置在該半導體裝置之上的一第四基體。
- 如請求項10之總成,其中,該第四基體是在沒有任何中介材料之下被直接鎖固到該第一頂表面。
- 如請求項10之總成,更包含:設置在該第四基體與該第一頂表面之間的黏著材料。
- 如請求項10之總成,其中,該第四基體包含複數片以不同晶體平面方位層疊的單晶藍寶石。
- 如請求項10之總成,其中,該第四基體是光學上透明或半透明。
- 如請求項14之總成,其中,該半導體裝置是為一影像感測器、一紅外線感測器、與一光線感測器中之一者。
- 如請求項9之總成,更包含:覆蓋該等導線與該等導電軌跡的包封劑。
- 一種形成封裝晶片總成的方法,包含:提供一半導體晶片,該半導體晶片包括:由半導體材料形成的一第一基體,其具有第一頂表面與第一底表面,一體地形成於該第一頂表面上或中的一半導體裝置,及位於該第一頂表面的數個第一銲墊,其電氣耦合到該半導體裝置的;提供一第二基體,該第二基體包括:第二頂表面和第二底表面,延伸在該第二頂表面與第二底表面之間的一第一孔洞,延伸在該第二頂表面與第二底表面之間的一個或多個第二孔洞,位於該第二頂表面的數個第二銲墊,位於該第二底表面的數個第三銲墊,及電氣耦合到該等第二銲墊和該等第三銲墊的數個導體;把該第一頂表面鎖固到該第二底表面,致使該半導體裝置與該第一孔洞對準,而且該等第一銲墊中之每一者與該一個或多個第二孔洞中之一者對準;及電氣連接在該等第一銲墊中之一者與該等第二銲墊中之一者之間之數條導線中之每一者,其中,該數條導線中之每一者通過該一個或多個第二孔洞中之一者。
- 如請求項17之方法,更包含:把一第三基體鎖固到該第二頂表面,其中,該第三基體覆蓋該第一孔洞而且是光學上透明或半透明,且其中,該半導體裝置是為一影像感測器、一紅外線感測器、與一光線感測器中之一者。
- 如請求項17之方法,更包含:以包封劑覆蓋該等導線,並充填該一個或多個第二孔洞。
- 如請求項17之方法,更包含:提供一第三基體,該第三基體包括:第三頂表面和第三底表面,及位於該第三頂表面的數個第四銲墊;及利用各把該等第三銲墊中之一者電氣耦合到該等第四銲墊中之一者的電氣互連件,來把該第三頂表面鎖固到該第二底表面。
- 一種形成封裝晶片總成的方法,包含:提供一半導體晶片,該半導體晶片包括:由半導體材料形成的一第一基體,其具有第一頂表面與第一底表面,一體地形成於該第一頂表面上或中的一半導體裝置,及位於該第一頂表面的數個第一銲墊,其電氣耦合到該半導體裝置,及形成一個或多個溝渠到該第一頂表面中; 形成數個導電軌跡,各具有電氣連接到該等第一銲墊中之一者之一第一部份、延伸在該第一上表面之上且是與該第一上表面隔絕之一第二部份、與向下延伸至該一個或多個溝渠中之一者內之一第三部份;提供一第二基體,該第二基體包括:第二頂表面與第二底表面,位於該第二頂表面的數個第二銲墊,位於該第二底表面的數個第三銲墊,及電氣耦合到該等第二銲墊和到該等第三銲墊的數個導體;把該第一底表面鎖固到該第二頂表面;將數條導線中之每一者電氣連接在該等數個導電軌跡中之一者之第三部份中之一者、與該等第二銲墊中之一者之間;以及提供一第三基體,該第三基體包括:第三頂表面和第三底表面,及位於該第三頂表面的數個第四銲墊;利用各把該等第三銲墊中之一者電氣耦合到該等第四銲墊中之一者的電氣互連件,來把該第三頂表面鎖固到該第二底表面。
- 如請求項21之方法,更包含:鎖固一第四基體到該第一頂表面,其中,該第四基體是設置在該半導體裝置之上。
- 如請求項22之方法,其中,該第四基體包含複數片以不 同晶體平面方位層疊的單晶藍寶石。
- 如請求項21之方法,更包含:以包封劑覆蓋該等導線和該等導電軌跡。
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- 2015-08-18 JP JP2015160774A patent/JP2016054289A/ja active Pending
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JP2016054289A (ja) | 2016-04-14 |
CN105374839A (zh) | 2016-03-02 |
US20170222065A1 (en) | 2017-08-03 |
US9666730B2 (en) | 2017-05-30 |
US9893213B2 (en) | 2018-02-13 |
KR20160021725A (ko) | 2016-02-26 |
HK1222260A1 (zh) | 2017-06-23 |
CN105374839B (zh) | 2018-11-09 |
TW201614747A (en) | 2016-04-16 |
US20160049526A1 (en) | 2016-02-18 |
KR101837808B1 (ko) | 2018-03-12 |
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