CN111052371A - 具有横向偏移堆叠的半导体裸片的半导体装置 - Google Patents

具有横向偏移堆叠的半导体裸片的半导体装置 Download PDF

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CN111052371A
CN111052371A CN201880054975.9A CN201880054975A CN111052371A CN 111052371 A CN111052371 A CN 111052371A CN 201880054975 A CN201880054975 A CN 201880054975A CN 111052371 A CN111052371 A CN 111052371A
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semiconductor die
semiconductor
package substrate
die
conductive
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CN201880054975.9A
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C·H·育
A·帕查穆图
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明揭示包含堆叠半导体裸片的半导体装置以及相关联***及方法。在一个实施例中，一种半导体装置包含：第一半导体裸片，其耦合到封装衬底；及第二半导体裸片，其堆叠在所述第一半导体裸片上方且从所述第一半导体裸片横向偏移。因此，所述第二半导体裸片可包含延伸超过所述第一半导体裸片的侧且面向所述封装衬底的外伸部分。在一些实施例中，所述第二半导体裸片在所述外伸部分处包含接合垫，其经由安置在所述接合垫与所述封装衬底之间的导电构件电耦合到所述封装衬底。在特定实施例中，所述第一半导体裸片可包含经由导线接合电耦合到所述封装衬底的第二接合垫。

Description

具有横向偏移堆叠的半导体裸片的半导体装置
技术领域
本发明大体上涉及半导体装置。特定来说，本技术涉及具有包含横向偏移半导体裸片的半导体裸片堆叠的半导体装置以及相关联***及方法。
背景技术
微电子装置(例如存储器装置、微处理器及发光二极管)通常包含安装到衬底且包装在保护覆盖物中的一或多个半导体裸片。半导体裸片包含功能构件，例如存储器单元、处理器电路、互连电路等等。半导体裸片制造商面临减小由半导体裸片占用的体积但又提高所得囊封组合件的容量及/或速度的越来越大压力。为满足这些要求，半导体裸片制造商通常使多个半导体裸片彼此上下垂直堆叠以提高安装半导体裸片的电路板或其它元件上的有限体积内的微电子装置的容量或性能。
在一些半导体裸片堆叠中，使堆叠裸片直接电互连(例如，使用硅穿孔(TSV)或倒装接合)以提供到安装裸片的电路板或其它元件的电连接。但是，以此方式使裸片互连需要额外处理步骤来产生使裸片互连所需的通路及/或金属化构件。在其它半导体裸片堆叠中，将堆叠裸片导线接合到电路板或其它元件。尽管使用导线接合可避免与使裸片互连相关联的成本及复杂性，但导线接合增大裸片堆叠的总高度，这是因为导线接合在堆叠中的每一裸片(包含最上裸片)上方连结成环。
附图说明
图1A及1B分别是说明根据本技术的实施例的半导体装置的横截面图及俯视图。
图2A到2J是说明根据本技术的实施例的各种制造阶段中的半导体装置的横截面图。
图3A及3B分别是说明根据本技术的实施例的半导体装置的横截面图及俯视图。
图4是根据本技术的实施例的半导体装置的俯视图。
图5是包含根据本技术的实施例所配置的半导体装置的***的示意图。
具体实施方式
下文将描述半导体装置的若干实施例的特定细节。在下文描述的若干实施例中，一种半导体装置包含：第一半导体裸片，其耦合到封装衬底；及第二半导体裸片，其堆叠在所述第一半导体裸片上方且从所述第一半导体裸片横向偏移。因此，所述第二半导体裸片可包含延伸超过所述第一半导体裸片的至少一个侧的外伸部分。在一些实施例中，所述第二半导体裸片仅堆叠在所述第一半导体裸片的第一部分上方且不堆叠在所述第一半导体裸片的第二部分上方。在特定实施例中，(a)所述第一半导体裸片的接合垫定位在所述第一部分处且经由导线接合电耦合到所述封装衬底，及(b)所述第二半导体裸片的接合垫定位在所述外伸部分处且经由导电支柱电耦合到所述封装衬底。由于所述第一半导体裸片及所述第二半导体裸片两者的接合垫直接电耦合到所述封装衬底，所以无需在堆叠裸片之间形成电互连。此外，所述半导体装置的高度不限于所述导线接合的高度，这是因为所述导线接合仅耦合到所述第一半导体装置且无需延伸超过所述第二半导体裸片的上表面。
在以下描述中，讨论许多特定细节以提供对本技术的实施例的透彻且可行描述。但是，相关领域的技术人员将认识到，可在无一或多个特定细节的情况下实践本发明。在其它例子中，未展示或未详细描述通常与半导体装置相关联的众所周知的结构或操作以使本技术的其它方面模糊不清。一般来说，应了解，除本文中所揭示的特定实施例之外，各种其它装置、***及方法也可在本技术的范围内。
如本文中所使用，术语“垂直”、“横向”、“上”及“下”可指半导体装置中的构件鉴于图中所展示的定向的相对方向或位置。例如，“上”或”最上”可指比构件更靠近于页的顶部的另一构件。但是，这些术语应被广义解释为包含具有其它定向(例如其中顶部/底部、上方/下方、上面/下面、上/下及左/右可取决于定向而互换的相反或倾斜定向)的半导体装置。
图1A是说明根据本技术的实施例的半导体装置100(“装置100”)的横截面图且图1B是说明根据本技术的实施例的半导体装置100(“装置100”)的俯视图。参考图1A，装置100包含由封装衬底130承载的第一半导体裸片110及第二半导体裸片120(统称为“半导体裸片110、120”)。半导体裸片110、120可各自具有集成电路或组件、数据存储元件、处理组件及/或制造在半导体衬底上的其它构件。例如，半导体裸片110、120可包含集成存储器电路及/或逻辑电路，其可包含各种类型的半导体组件及功能构件，例如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、快闪存储器、其它形式的集成电路存储器、处理电路、成像组件及/或其它半导体构件。在一些实施例中，半导体裸片110、120可为相同的(例如经制造以具有相同设计及规格的存储器裸片)，但在其它实施例中，半导体裸片110、120可彼此不同(例如不同类型的存储器裸片或控制器、逻辑及/或存储器裸片的组合)。
第一半导体裸片110包含面向封装衬底130的下表面113b及与下表面113b相对的上表面113a。类似地，第二半导体裸片120包含面向第一半导体裸片110的上表面113a及封装衬底130的下表面123b及与下表面123b相对的上表面123a。在图1A所说明的实施例中，第二半导体裸片120堆叠在第一半导体裸片110上方，使得第二半导体裸片120的下表面123b的部分位于第一半导体裸片110的上表面113a上方(例如，直接在第一半导体裸片110的上表面113a上方及/或相邻于第一半导体裸片110的上表面113a)。即，第二半导体裸片120从第一半导体裸片110横向偏移，使得第二半导体裸片120包含不定位在第一半导体裸片110上方的外伸部分124，且第一半导体裸片110包含其中第二半导体裸片120未定位在第一半导体裸片110上方的对应敞露部分114。更特定来说，参考图1B，第一半导体裸片110可包含相对第一侧116及相对第二侧118，且第二半导体裸片120可仅延伸超过第一半导体裸片110的第一侧116中的一者(图1B中以虚线展示)(例如，沿大体上平行于第二侧118的轴线X1的方向)以界定外伸部分124。在其它实施例(例如，如图4中所展示)中，第二半导体裸片120可延伸超过第一半导体裸片110的第一侧116及/或第二侧118中的一者以上以界定外伸部分124。
第一半导体裸片110的敞露部分114及第二半导体裸片120的外伸部分124的大小、形状及相对范围至少取决于半导体裸片110、120的相对尺寸(例如宽度、厚度及长度)及定位(例如横向偏移)。例如，如图1B的俯视图中所展示，半导体裸片110、120可各自具有相同矩形平面形状及相同或大体上类似尺寸。因此，敞露部分114及外伸部分124两者可具有矩形平面形状及相同或大体上类似尺寸。但是，在其它实施例中，半导体裸片110、120的形状、大小及偏移可不同。例如，第一半导体裸片110及/或第二半导体裸片120可呈圆形、方形、多边形及/或其它适合形状。因此，第一半导体裸片110的敞露部分114及/或第二半导体裸片120的外伸部分124可具有不同相对形状及/或大小。
第一半导体裸片110进一步包含位于敞露部分114处的上表面113a上(例如，暴露在敞露部分114处的上表面113a处)且背向封装衬底130的第一接合垫112。类似地，第二半导体裸片120包含位于外伸部分124处的下表面113b上且面向封装衬底130的第二接合垫122。即，半导体裸片110、120可布置成其中每一半导体裸片的接合垫面向相反方向的面对面配置。如图1B中所说明，第一接合垫112及第二接合垫122(统称为“接合垫112、122”；图1B中以虚线展示第二半导体裸片的接合垫122)可各自具有直线形状且可分别沿半导体裸片110、120的一个侧形成单个列。但是，在其它实施例中，接合垫112、122可具有任何其它形状或配置。例如，接合垫112、122可呈圆形、多边形等等且可沿半导体裸片110、120的一个以上侧布置成多个行及/或列，等等。
如图1A中所展示，装置100仅包含两个半导体裸片。但是，在其它实施例中，装置100可包含任何数目个半导体裸片。例如，装置100可包含堆叠在第一半导体裸片110及/或第二半导体裸片120上的一或多个额外半导体裸片，或装置100可具有相邻于第一半导体裸片110及/或第二半导体裸片120耦合到封装衬底130的其它半导体裸片。
再次参考图1A，装置100可进一步包含至少部分形成在第一半导体裸片110的下表面113b与封装衬底130之间的第一裸片附接材料142及至少部分形成在第一半导体裸片110的上表面113a与第二半导体裸片120的下表面123b之间的第二裸片附接材料144。第一及第二裸片附接材料142、144可为(例如)粘合膜(例如裸片附接膜)、环氧树脂、胶带、糊膏或其它适合材料。在一些实施例中，第一及第二裸片附接材料142、144是相同材料及/或具有大体上相同厚度。如图1A的实施例中所展示，第二裸片附接材料144可至少部分延伸到第二半导体裸片120的外伸部分124上。但是，在其它实施例中，第二裸片附接材料144可仅延伸在第一半导体裸片110与第二半导体裸片120之间。同样地，在一些实施例中，第二裸片附接材料144可至少部分延伸到第一半导体裸片110的敞露部分114上。
封装衬底130可包含再分布结构、中介层、印刷电路板、介电间隔物、另一半导体裸片(例如逻辑裸片)或另一适合衬底。更明确来说，在图1A所说明的实施例中，封装衬底130具有第一侧133a及与第一侧133a相对的第二侧133b，且包含使封装衬底130的导电部分绝缘的绝缘材料135。封装衬底的导电部分可包含位于绝缘材料135中及/或其上且暴露在第一表面133a处的第一接点132及第二接点134。如图1B中所更清楚说明，第一接点132与第一半导体裸片110的第一侧116中的一者横向向外间隔(例如，在外部)。第二接点134(在图1B中被遮蔽)可与第一侧116中的另一者横向向外间隔且位于第二半导体裸片120的外伸部分124下方。在一些实施例中，第二接点134与第二半导体裸片120的第二接合垫122垂直对准(例如，叠加在其下方)。
封装衬底130的导电部分也可包含：(a)导电第三接点136，其位于绝缘材料135中及/或其上且暴露在封装衬底130的第二表面133b处；及(b)导线138(例如通路及/或迹线)，其延伸在绝缘材料135内及/或其上以将第一接点132及第二接点134中的个别者电耦合到第三接点136中的对应者。在一些实施例中，第三接点136中的一或多者可定位在与第三接点136电耦合的对应第一接点132或第二接点134的横向外部(例如，从其扇出)。将第三接点136中的至少一些定位在第一接点132及/或第二接点134的横向外部促进装置100连接到其它装置及/或接口(其含有具有大于第一半导体裸片110及/或第二半导体裸片120的节距的节距的连接)。在一些实施例中，第三接点136中的个别者可经由对应导线138电耦合到第一接点132及/或第二接点134中的一者以上。以此方式，装置100可经配置使得半导体裸片110、120的个别引脚被个别隔离且可经由单独第三接点136接取(例如信号引脚)，及/或经配置使得多个引脚可经由相同第三接点136共同接取(例如电力供应或接地引脚)。在特定实施例中，第一接点132、第二接点134、第三接点136及导线138可由例如铜、镍、焊料(例如基于SnAg的焊料)、填充有导体的环氧树脂及/或其它导电材料的一或多个导电材料形成。
在一些实施例中，封装衬底130是不包含预成形衬底(即，与载体晶片分开形成且接着附接到载体晶片的衬底)的再分布结构。在这些实施例中，且如下文将参考图2A到2D进一步详细描述，绝缘材料135可包括(例如)使层添加地彼此上下叠置成形的适合介电材料(例如钝化材料)的一或多个层。同样地，可经由适合堆积工艺来添加地形成再分布结构的导电部分。在其中再分布结构不包含预成形衬底的实施例中，封装衬底130可为极薄的。例如，在一些这些实施例中，封装衬底130的第一及第二表面133a、133b之间的距离D可小于50μm。在特定实施例中，距离D是约30μm或小于30μm。因此，与(例如)包含形成在预成形衬底上方的传统再分布层的装置相比可减小半导体装置100的总大小。但是，封装衬底130的厚度是不受限制的。在其它实施例中，封装衬底130可包含不同构件及/或构件可具有不同布置。
装置100进一步包含电耦合到封装衬底130的第三接点138且经配置以将装置100电耦合到外部装置或电路(未展示)的电连接器108(例如焊球、导电凸块、导电支柱、导电环氧树脂及/或其它适合导电元件)。在一些实施例中，电连接器108在封装衬底130的第二表面133b上形成球栅阵列。在特定实施例中，可省略电连接器108且可将第三接点136直接连接到外部装置或电路。
装置100进一步包含：(a)导线接合104，其将第一半导体裸片110的第一接合垫112电耦合到封装衬底130的第一接点132；及(b)导电构件106，其将第二半导体裸片120的第二接合垫122电耦合到封装衬底130的第二接点134。尤其在图1A所说明的实施例中，封装衬底130(或(例如)第一半导体裸片110的上表面113a)上方的导线接合104的最大高度不大于封装衬底130上方的第二半导体裸片120的高度。即，导线接合104不向上延伸超过与第二半导体裸片120的上表面123a共面的平面。此外，如图1B的俯视图中所说明，每一第一接点132可经由导线接合104中的单个者电耦合到第一半导体裸片110的接合垫112中的仅单个者。但是，在其它实施例中，第一接点132中的个别者可经由两个或两个以上导线接合104电耦合到两个或两个以上第一接合垫112(例如，用于将共同信号提供到第一半导体裸片110的两个引脚)。导电构件106可具有各种适合结构(例如支柱、柱、螺柱、凸块等等)且可由铜、镍、焊料(例如基于SnAg的焊料)、填充有导体的环氧树脂及/或其它导电材料制成。在特定实施例中，导电构件106是焊料接头，而在特定实施例中，导电构件106是铜柱。在其它实施例中，导电构件106可包含更复杂结构，例如氮化物上凸块结构或其它已知倒装安装结构。
显而易见，第二半导体裸片120无需与第一半导体裸片110直接电互连或通过第一半导体裸片110电互连，这是因为第二半导体裸片120直接连接到封装衬底130。相比来说，许多传统半导体装置需要相对较复杂且昂贵的互连结构来将堆叠半导体裸片耦合到封装衬底。例如，许多已知半导体装置包含延伸穿过堆叠中的下半导体裸片以将堆叠中的上裸片电连接到封装衬底的硅穿孔(TSV)。这些装置不仅需要形成TSV，且也需要形成用于连接堆叠中的相邻半导体裸片的TSV的互连件(例如凸块下金属化构件、焊料连接等等)。同样地，许多已知半导体装置包含面对面布置且倒装接合在一起的堆叠半导体裸片。此外，这些装置需要形成连接对向裸片的接合垫的互连结构且在许多例子中，需要形成半导体裸片之间的再分布层(RDL)来提供每一裸片的接合垫之间的适合映射。本文中所描述的装置100无需半导体裸片110、120之间的直接电互连且因此避免与相关联互连结构相关联的成本及复杂性。例如，装置100可仅包含半导体裸片110、120之间的第二裸片附接材料144来替代形成半导体裸片110、120之间的RDL。
如图1A中所进一步展示，装置100包含封装衬底130的第一侧133a上方的模制材料146(为便于说明，图1B中未展示模制材料146)。模制材料146至少部分包围第一半导体裸片110、第二半导体裸片120、导线接合104及/或导电构件106以保护这些组件中的一或多者免受污染及/或物理损坏。例如，在图1A所说明的实施例中，模制材料146囊封(例如，密封)第一半导体裸片110、导线接合104及导电构件106，而仅从模制材料146暴露第二半导体裸片120的上表面123a。
显而易见，模制材料146未相对于封装衬底130延伸超过第二半导体裸片120(例如，超过与第二半导体裸片120的上表面123a共面的平面)，同时也大体上囊封导线接合104及导电构件106。相比来说，许多传统半导体装置包含各自导线接合到封装衬底的半导体裸片的堆叠。在这些装置中，堆叠中的最上半导体裸片的导线接合延伸超过最上裸片以连接到所述裸片的接合垫(例如，以类似于图1A中的导线接合104的方式，其包含第一半导体裸片110的上表面113a上方的“环圈高度”)。但是，由于第二半导体裸片120经由导电构件106(而非经由导线接合)直接电耦合到封装衬底130，所以模制材料146无需延伸超过第二半导体裸片120。
因此，可减小装置100的高度(例如厚度)及装置100中所使用的模制材料146的总量。减小装置100中的模制材料146的数量可降低装置100随温度变化而翘曲的趋势。特定来说，模制材料一般具有大于硅半导体裸片的热膨胀系数(CTE)。因此，通过减小模制材料的高度来减小模制材料146的体积可降低装置100的总平均CTE(例如，通过增大由半导体裸片110、120占用的相对体积)。但是，在其它实施例中，模制材料146可延伸超过第二半导体裸片120。例如，在一些实施例中，模制材料146可略微延伸超过第二半导体裸片120以覆盖上表面123a，同时与(例如)其中将最上半导体裸片导线接合到封装衬底的半导体装置相比仍减小装置100的总高度。
此外，在一些实施例中，模制材料146可至少部分填充第二半导体裸片120的外伸部分124下方的空间。因此，模制材料146可支撑外伸部分124以防止第二半导体裸片120因外力而翘曲或受其它损坏。此外，在其中封装衬底130是不包含预成形衬底的再分布结构的实施例中，模制材料146也可为装置100提供所要结构强度。例如，模制材料146可经选择以防止装置100在将外力施加到装置100时翘曲、弯曲等等。因此，在一些实施例中，再分布结构可被制成极薄的(例如，小于50μm)，这是因为再分布结构无需为装置100提供很大结构强度。因此，可进一步减小装置100的总高度(例如厚度)。
图2A到2J是说明根据本技术的实施例的制造半导体装置100的方法中的各种阶段的横截面图。一般来说，可将半导体装置100制造成(例如)离散装置或较大晶片或面板的部分。在晶片级或面板级制造中，形成较大半导体装置，接着将其分割以形成多个个别装置。为便于解释及理解，图2A到2J说明两个半导体装置100的制造。但是，所属领域的技术人员应易于了解，可将半导体装置100的制造扩展到晶片及/或面板级(即，包含能够分割为两个以上半导体装置100的更多组件)，同时包含类似构件且使用如本文中所描述的类似工艺。
更明确来说，图2A到2D说明半导体装置100(图1A)的封装衬底(其是不包含预成形衬底的再分布结构)的制造。在其它实施例中，可为半导体装置100提供不同类型的封装衬底(例如中介层、印刷电路板等等)，且制造半导体装置100的方法可开始于(例如)在提供封装衬底之后的图2E中所说明的阶段。
参考图2A，在具有背面251b及正面251a的载体250上形成封装衬底130(即，再分布结构)，载体250包含形成于其上的释放层252。载体250为后续处理阶段提供机械支撑且可为由(例如)硅、绝缘体上硅、化合物半导体(例如氮化镓)、玻璃或其它适合材料形成的临时载体。在一些实施例中，可在随后移除载体250之后重新使用载体250。载体250也在后续处理阶段期间保护释放层252的表面以确保稍后可从封装衬底130适当移除释放层252。释放层252防止封装衬底130与载体250直接接触且因此保护封装衬底130免受载体250上的可能污染。释放层252可为一次性膜(例如基于环氧树脂的材料的层压膜)或其它适合材料。在一些实施例中，释放层252对激光敏感或对光敏感以促进其在后续阶段中被移除。
封装衬底130(图1A)包含可由添加堆积工艺形成的导电及介电材料。即，封装衬底130添加地直接堆积在载体250及释放层252上而非另一层压或有机衬底上。明确来说，通过例如溅镀、物理气相沉积(PVD)、电镀、光刻等等的半导体晶片制造工艺来制造封装衬底130。例如，参考图2B，可在释放层252上直接形成第三接点136，且可在释放层252上形成一层绝缘材料135以电隔离第三接点136。绝缘材料135可由(例如)聚对二甲苯、聚酰亚胺、低温化学气相沉积(CVD)材料(例如正硅酸乙酯(TEOS)、氮化硅(Si3Ni4)、氧化硅(SiO2))及/或其它适合介电、非导电材料形成。参考图2C，可形成堆积绝缘材料135的一或多个额外绝缘材料层，且可形成一或多个额外导电材料层以将导线138堆积在绝缘材料135上及/或其内。
图2D展示完全形成在载体250上方之后的封装衬底130。如上文所描述，形成经由导线138中的一或多者电耦合到第三接点136中的对应者的第一接点132及第二接点134。第一接点132、第二接点134、第三接点136及导线138可由铜、镍、焊料(例如基于SnAg的焊料)、填充有导体的环氧树脂及/或其它导电材料制成。在一些实施例中，这些导电部分全部由相同导电材料制成。在其它实施例中，第一接点132、第二接点134、第三接点136及/或导线138可包括一个以上导电材料。第一接点132及第二接点134可经布置以界定封装衬底130上的裸片附接区域239。
参考图2E，半导体装置100的制造接着在封装衬底130的第二接点134上形成导电构件106。可通过此项技术中众所周知的适合电镀或无电电镀技术来制造导电构件106。在其它实施例中，可使用其它沉积技术(例如溅镀沉积)来替代电镀。在其它实施例中，导电构件106可包括安置在第二接点134上的焊球或焊料凸块。导电构件106可具有圆形、矩形、六边形、多边形或其它横截面形状且可为单层或多层结构。
参考图2F，半导体装置100的制造接着(a)将第一半导体裸片110耦合到封装衬底130的裸片附接区域239(图2D)中的对应者且(b)形成导线接合104使得其将第一半导体裸片110的第一接合垫112电耦合到封装衬底130的第一接点132。更特定来说，第一半导体裸片110可经由第一裸片附接材料142附接到封装衬底的裸片附接区域239。第一裸片附接材料142可为裸片附接粘合膏或粘合元件，例如裸片附接膜或切割裸片附接膜(所属领域的技术人员分别称为“DAF”或“DDF”)。在一些实施例中，第一裸片附接材料142可包含在其被超过阈值水平的压力压缩时将第一半导体裸片110粘合到封装衬底230的压力固化粘合元件(例如胶带或膜)。在其它实施例中，第一裸片附接材料142可为通过暴露于UV辐射来固化的UV固化胶带或膜。
图2G展示将第二半导体裸片120堆叠在第一半导体裸片110上方且耦合到导电构件106之后的半导体装置100。更明确来说，可将第二半导体裸片120倒装接合到封装衬底130，使得第二半导体裸片120的第二接合垫122经由导电构件106电耦合到封装衬底130的第二接点134中的对应者。在一些实施例中，使用焊料或焊料膏来将第二接合垫122耦合到导电构件106。在其它实施例中，可使用例如热压接合(例如铜-铜(Cu-Cu)接合)的另一工艺来形成第二接合垫122与导电构件106之间的导电Cu-Cu接头。
可经由第二裸片附接材料144将第二半导体裸片120附接到第一半导体裸片110的至少一部分。如上文所描述，无需在半导体裸片110与120之间形成电互连(例如金属化构件、焊料凸块、RDL等等)。第二裸片附接材料144可大体上类似于第一裸片附接材料142(例如DAF、DDF等等)且在一些实施例中是与第一裸片附接材料142的材料相同及/或具有与第一裸片附接材料142相同的厚度。在图2G所说明的实施例中，第二裸片附接材料144延伸到第二半导体裸片120的外伸部分124上。在一些这些实施例中，在将第二接合垫122耦合到导电构件106之前从第二半导体裸片120的第二接合垫122剥离或以其它方式移除第二裸片附接材料144或防止第二裸片附接材料144覆盖第二半导体裸片120的第二接合垫122。在其它实施例中，不在外伸部分124上形成或从其完全移除第二裸片附接材料144。
图2H展示在封装衬底130的第一表面133a上且至少部分围绕第一半导体裸片110、导线接合104、第二半导体裸片120及/或导电构件106安置模制材料146之后的半导体装置100。模制材料146可由树脂、环氧树脂、基于聚硅氧的材料、聚酰亚胺及/或此项技术中使用或已知的其它适合树脂形成。一旦被沉积，模制材料146便可通过UV光、化学硬化剂、热或此项技术中已知的其它适合固化方法来固化。固化模制材料146可包含上表面247。在图2H所说明的实施例中，上表面247大体上与第二半导体裸片120的上表面123a共面，使得上表面123a不被模制材料146覆盖。在一些实施例中，在一个步骤中形成模制材料146，使得第二半导体裸片120的上表面123a暴露在模制材料146的上表面247处。在其它实施例中，形成且接着磨削模制材料146以平坦化上表面247且借此暴露第二半导体裸片120的上表面123a。如图2H中所进一步展示，在一些实施例中，模制材料146囊封第一半导体裸片110、导线接合104及导电构件106，使得这些构件被密封在模制材料146内。
图2I说明(a)在使封装衬底130与载体250(图2H)分离且(b)在封装衬底130的第三接点136上形成电连接器108之后的半导体装置100。在一些实施例中，真空、杆销、激光或其它光源或此项技术中已知的其它适合方法可使封装衬底130脱离释放层252(图2H)。在特定实施例中，释放层252(图2H)允许载体250被容易地移除，使得载体250可被再次重新使用。在其它实施例中，可通过薄化载体250及/或释放层252(例如使用背面研磨、干式蚀刻工艺、化学蚀刻工艺、化学机械抛光(CMP)等等)来至少部分移除载体250及释放层252。移除载体250及释放层252暴露封装衬底130的第二表面133b(包含第三接点136)。电连接器108形成在第三接点136上且可经配置以将第三接点136电耦合到外部电路(未展示)。在一些实施例中，电连接器108包括多个焊球或焊料凸块。例如，模板印刷机可将焊料膏的离散块沉积到第三接点136上，接着可回焊焊料膏以在第三接点136上形成焊球或焊料凸块。
图2J展示彼此单粒化之后的半导体装置100。如展示，可在多个切割道255(如图2I中所说明)处切割封装衬底130及模制材料146以单粒化堆叠半导体裸片110、120且使半导体装置100彼此分离。一旦被单粒化，个别半导体装置100便可经由电连接器108附接到外部电路且因此并入到大量***及/或装置中。
图3A是横截面图且图3B是俯视图，其说明根据本技术的另一实施例的半导体装置300(“装置300”)。此实例更明确地展示具有两个以上堆叠半导体裸片的根据本技术所配置的另一半导体装置。装置300可包含大体上类似于上文所详细描述的半导体装置100的构件的构件。例如，在图3A所说明的实施例中，装置300包含由封装衬底330(例如不包含预成形衬底的再分布结构)承载的第一半导体裸片310及第二半导体裸片320(统称为“半导体裸片310、320”)。更明确来说，第二半导体裸片320堆叠在第一半导体裸片310上方且从第一半导体裸片310横向偏移以界定第二半导体裸片320的外伸部分324及第一半导体裸片310的敞露部分314。第一半导体裸片310具有经由第一裸片附接材料342附接到封装衬底330的下表面313b及面向第二半导体裸片320且具有暴露在第一半导体裸片310的敞露部分314处的第一接合垫312的上表面313a。第二半导体裸片320具有经由第二裸片附接材料344部分附接到第一半导体裸片310的上表面313a的下表面323b及与下表面323b相对的上表面323a。第二半导体裸片320进一步包含下表面323b上的第二接合垫322，其暴露在第二半导体裸片320的外伸部分324处且面向封装衬底330。封装衬底330包含第一接点332及第二接点334。第一导线接合304将第一接合垫312电耦合到封装衬底330的第一接点332，且第一导电构件306将第二接合垫322电耦合到封装衬底330的第二接点334。第一及第二接点332及334经由导线338电耦合到封装衬底的对应第三接点336。
装置300进一步包含堆叠在半导体裸片310、320上方的第三半导体裸片360及第四半导体裸片370(统称为“半导体裸片360、370”)。半导体裸片360、370可大体上类似于半导体裸片110、120(图1)及半导体裸片310、320来布置。例如，如图3A的实施例中所说明，第四半导体裸片370可从第三半导体裸片360横向偏移以界定第四半导体裸片370的外伸部分374及第三半导体裸片360的敞露部分364。更特定来说，参考图3B，第三半导体裸片360可具有相对第一侧316及相对第二侧318。如展示，第四半导体裸片370可仅延伸超过第三半导体裸片360的第一侧316中的一者(图3B中以虚线展示)(例如，沿大体上平行于第二侧318的轴线X3的方向)以界定外伸部分374。在一些实施例中，半导体裸片360、370的横向偏移量(例如沿轴线X3的距离)与半导体裸片310、320的横向偏移相同或大体上相同。此外，如图3B的俯视图中所更清楚说明，半导体裸片310、320及半导体裸片360、370可沿相同或大体上相同方向(例如，沿轴线X3的方向)横向偏移。在其它实施例中，半导体裸片310、320及半导体裸片360、370可沿一个以上方向偏移或偏移不同量(例如，第二半导体裸片320的外伸部分324及第四半导体裸片370的外伸部分374可具有不同形状、定向及/或尺寸)。
第三半导体裸片360可具有经由第三裸片附接材料348附接到第二半导体裸片320的上表面323a的下表面363b及面向第四半导体裸片370且具有暴露在第三半导体裸片360的敞露部分314处的第三接合垫362的上表面363a。第四半导体裸片370具有上表面373a及经由第四裸片附接材料349部分附接到第三半导体裸片360的上表面363a的下表面373b。第四半导体裸片370的下表面373b包含外伸部分374处的第四接合垫372。第四接合垫372定位在封装衬底330的第二接点334的至少一部分上方(例如，与其垂直对准，叠加在其上方，等等)。
装置300进一步包含：(a)第二导线接合368，其将第三半导体裸片360的第三接合垫362电耦合到封装衬底130的第一接点332中的对应者；及(b)第二导电构件376，其将第四半导体裸片370的第四接合垫372电耦合到封装衬底330的第二接点334中的对应者。在特定实施例中，封装衬底330上方及/或第三半导体裸片360的上表面363a上方的第二导线接合368的最大高度不大于封装衬底330上方及/或第三半导体裸片360的上表面363a上方的第四半导体裸片370的高度。如图3B的实施例中所说明，第一接点332及第二接点334(未绘制；位于以虚线展示的第二接合垫322及第四接合垫372下方)可布置成一或多个列(例如两列)且可各耦合到各种半导体裸片的接合垫中的一或多者。在其它实施例中，第一及第二接点332、334的布置可具有任何其它适合配置(例如，布置成一列，布置成行、偏移行及/或列，等等)。第一及第二导电构件306、376可具有各种适合结构(例如支柱、柱、螺柱、凸块等等)且可由铜、镍、焊料(例如基于SnAg的焊料)、填充有导体的环氧树脂及/或其它导电材料制成。
显而易见，装置100中的每一半导体裸片直接电耦合到封装衬底330的第一接点332或第二接点334。因此，第一半导体裸片310、第二半导体裸片320、第三半导体裸片360及第四半导体裸片370(统称为“半导体裸片310到370”)中的任何者之间无需互连件或其它结构来将半导体裸片310到370电连接到封装衬底330。例如，在一些实施例中可经由第二裸片附接材料344、第三裸片附接材料348及第四裸片附接材料349中的一或多者将半导体裸片310到370耦合在一起以替代半导体裸片310到370之间的互连结构(例如RDL)。在一些实施例中，装置300中的每一裸片附接材料是相同材料及/或具有相同厚度。
装置100可进一步包含封装衬底330的上表面上方的模制材料346(为便于说明，图3B中未展示模制材料346)。在一些实施例中，模制材料346至少部分包围半导体裸片310到370、第一及第二导线接合304、368及/或第一及第二导电构件306、376以保护这些组件中的一或多者免受污染及/或物理损坏。例如，在图3A所说明的实施例中，仅第四半导体裸片370的上表面373a从模制材料346暴露。显而易见，模制材料346未相对于封装衬底330延伸超过第四半导体裸片370(例如，超过与第四半导体裸片370的上表面373a共面的平面)，同时仍囊封第一及第二导线接合304、368以及第一及第二导电构件306、376。因此，与(例如)具有耦合装置中的最上裸片的导线接合且因此具有高于最上裸片的线环高度的传统半导体装置相比可减小装置100的高度(例如厚度)。同样地，由于模制材料346无需延伸超过第四半导体裸片370的上表面373a，所以可减少装置300中所使用的模制材料346的总量(例如，降低装置300的成本及/或翘曲)。
图4是根据本技术的另一实施例的半导体装置400(“装置400”)的俯视图。此实例更明确地说明沿半导体装置的两个轴线横向偏移的堆叠半导体裸片。装置400可包含大体上类似于上文所详细描述的半导体装置100的构件的构件。例如，装置400包含耦合到封装衬底430的第一半导体裸片410及堆叠在第一半导体裸片410上方且从第一半导体裸片410横向偏移的第二半导体裸片420(统称为“半导体裸片410、420”)。与参考图1A到3B所详细描述的许多实施例相比，第二半导体裸片420从第一半导体裸片410的两侧横向偏移。更明确来说，第一半导体裸片410可包含相对第一侧416及相对第二侧418。第二半导体裸片420可延伸超过(例如，沿大体上平行于第二侧418的轴线X4的方向)第一侧416中的一者(以虚线部分展示)且超过(例如，沿大体上平行于第一侧416的轴线Y4的方向)第二侧418中的一者(以虚线部分展示)以界定第二半导体裸片420的外伸部分424及第一半导体裸片410的敞露部分414。在图4所说明的实施例中，第二半导体裸片420的外伸部分424及第一半导体裸片410的敞露部分414具有大体上“L形”形状。在一些实施例中，当半导体裸片410、420具有相同平面形状及尺寸时，敞露部分414及外伸部分424的尺寸可相同。在其它实施例中，半导体裸片410、420可具有不同平面形状及/或尺寸，使得外伸部分424及敞露部分414具有不同形状及/或尺寸。例如，当两个半导体裸片410、420中的一者大于另一者时，敞露部分414及/或外伸部分424可具有沿较大裸片的三个边缘的大体上“U形”形状。
如图4中所进一步展示，第一半导体裸片410可具有位于第一半导体裸片410的上表面上且暴露在敞露部分414处的第一接合垫412。类似地，第二半导体裸片420可具有位于第二半导体裸片420的下表面上、暴露在外伸部分424处且面向封装衬底430的第二接合垫422(以虚线展示)。如图4中所说明，第一及第二接合垫412、422(统称为“接合垫412、422”)可分别沿第一半导体裸片410的敞露部分414及第二半导体裸片420的外伸部分424布置成L形形状。在其它实施例中，接合垫412、422可具有其它布置(例如，定位成仅相邻于半导体裸片410、420的单个侧，定位成一个以上行及/或列，等等)。在特定实施例中，半导体裸片410、420取决于半导体裸片410、420的接合垫412、422的配置而横向偏移。例如，半导体裸片410、420的偏移可经选择使得第一半导体裸片410的第一接合垫412中的每一者暴露在敞露部分414处且第二半导体裸片420的第二接合422中的每一者暴露在外伸部分424处。
封装衬底430可包含第一接点432及第二接点(在图4中被遮蔽；例如，在第二接合垫422下方垂直对准)。装置400进一步包含：导线接合404，其将第一半导体裸片410的第一接合垫412电耦合到封装衬底430的第一接点432；及导电构件(未绘制；例如导电支柱)，其将第二半导体裸片420的第二接合垫422电耦合到封装衬底430的第二接点。第一接点432及第二接点可具有任何适合布置。例如，在一些实施例中，封装衬底430是不包含预成形衬底且添加地堆积(图2A到2D)的再分布结构。因此，封装衬底430可为可适应半导体裸片410、420及接合垫412、422的特定布置的灵活结构。
具有上文参考图1A到4所描述的构件的半导体装置的任一者可并入到大量更大及/或更复杂***的任何者中，图5中所示意性展示的***500是所述***的代表性实例。***500可包含处理器502、存储器504(例如SRAM、DRAM、快闪存储器及/或其它存储器装置)、输入/输出装置505及/或其它子***或组件508。上文参考图1A到4所描述的半导体装置可包含在图5所展示的元件的任何者中。所得***500可经配置以执行多种适合运算、处理、存储、感测、成像及/或其它功能中的任何者。因此，***500的代表性实例包含(但不限于)计算机及/或其它数据处理器，例如台式计算机、膝上型计算机、因特网器具、手持式装置(例如掌上型计算机、可佩戴计算机、蜂窝式或移动电话、个人数字助理、音乐播放器等等)、平板计算机、多处理器***、基于处理器的或可编程的消费型电子产品、网络计算机及迷你计算机。***500的额外代表性实例包含灯、相机、车辆等等。关于这些及其它实例，***500可收容于单个单元中或分布在多个互连单元上(例如，通过通信网络)。因此，***500的组件可包含本地及/或远程存储器存储装置及多种适合计算机可读媒体中的任何者。
应从上文了解，本文已为了说明而描述本技术的特定实施例，但可在不背离本发明的情况下作出各种修改。此外，也可在其它实施例中组合或消除特定实施例的上下文中所描述的本发明的特定方面。例如，参考图1A到4所描述的各种实施例可经组合以并入依不同方式横向偏移的不同数目个堆叠半导体裸片(例如3个裸片、5个裸片、6个裸片、8个裸片等等)。因此，本发明仅受限于所附权利要求书。此外，尽管已在所述实施例的上下文中描述与新技术的特定实施例相关联的优点，但其它实施例也可展示这些优点，且未必全部实施例需要展现这些优点以落入本技术的范围内。因此，本发明及相关联技术可涵盖本文中未明确展示或描述的其它实施例。

Claims (28)

1.一种半导体装置，其包括：
封装衬底；
第一半导体裸片，其耦合到所述封装衬底且具有背向所述封装衬底的上表面，所述上表面包含第一接合垫；
导线接合，其将所述第一半导体裸片的所述第一接合垫电耦合到所述封装衬底；
第二半导体裸片，其耦合到所述第一半导体裸片的所述上表面且具有面向所述封装衬底的下表面，其中所述第二半导体裸片横向延伸超过所述第一半导体裸片的至少一个侧以界定所述第二半导体裸片的外伸部分，且其中所述下表面包含所述外伸部分处的第二接合垫；及
导电构件，其将所述第二半导体裸片的所述第二接合垫电耦合到所述封装衬底。
2.根据权利要求1所述的半导体装置，其进一步包括：
模制材料，其位于所述封装衬底上方且至少部分围绕所述第一半导体裸片、所述导线接合、所述第二半导体裸片及/或所述导电构件，其中所述第二半导体裸片包含与所述下表面相对的上表面，且其中所述模制材料不远离所述封装衬底延伸超过与所述第二半导体裸片的所述上表面共面的平面。
3.根据权利要求2所述的半导体装置，其中所述模制材料囊封所述第一半导体裸片、所述导线接合及所述导电构件。
4.根据权利要求1所述的半导体装置，其中所述导电构件是延伸在所述第二接合垫与所述封装衬底之间的导电支柱。
5.根据权利要求1所述的半导体装置，其中所述封装衬底是具有第一表面及与所述第一表面相对的第二表面的再分布结构，其中所述第一表面包含第一导电接点及第二导电接点，其中所述第二表面包含第三导电接点，其中所述第一导电接点及所述第二导电接点通过延伸穿过绝缘材料及/或在其上延伸的导线来电耦合到所述第三导电接点中的对应者，且其中所述再分布结构不包含预成形衬底。
6.根据权利要求5所述的半导体装置，其中所述导线接合将所述第一半导体裸片的所述第一接合垫电耦合到所述再分布结构的所述第一导电接点中的对应者，且其中所述导电构件是形成在所述第二导电接点上且将所述第二半导体裸片的所述第二接合垫电耦合到所述第二导电接点中的对应者的铜柱。
7.根据权利要求1所述的半导体装置，其中所述第一半导体裸片的所述上表面上方的所述导线接合的最大高度小于或等于所述第一半导体裸片的所述上表面上方的所述第二半导体裸片的高度。
8.根据权利要求1所述的半导体装置，其中所述第一半导体裸片的所述上表面包含第一部分及第二部分，其中所述第二半导体仅位于所述第二部分处的所述第一半导体裸片上方，且其中所述第一接合垫定位在所述第一部分处。
9.根据权利要求1所述的半导体装置，其中所述第一半导体裸片包含相对第一侧及相对第二侧，且其中所述第二半导体裸片仅横向延伸超过所述第一侧中的一者或所述第二侧中的一者。
10.根据权利要求1所述的半导体装置，其中所述第一半导体裸片包含相对第一侧及相对第二侧，且其中所述第二半导体裸片横向延伸超过所述第一侧中的一者及所述第二侧中的一者。
11.根据权利要求1所述的半导体装置，其中所述第一半导体裸片及所述第二半导体裸片具有相同形状及尺寸。
12.根据权利要求1所述的半导体装置，其进一步包括：
第一裸片附接材料，其介于所述第一半导体裸片与所述封装衬底之间；及
第二裸片附接材料，其介于所述第一半导体裸片与所述第二半导体裸片之间。
13.根据权利要求1所述的半导体装置，其中所述导线接合是第一导线接合，其中所述导电构件是第一导电构件，且所述半导体装置进一步包括：
第三半导体裸片，其耦合到所述第二半导体裸片的上表面且具有背向所述第二半导体裸片及所述封装衬底的上表面，所述第三半导体裸片的所述上表面包含第三接合垫；及
第二导线接合，其将所述第三半导体裸片的所述第三接合垫电耦合到所述封装衬底。
14.根据权利要求13所述的半导体装置，其进一步包括所述第二半导体裸片的所述上表面上的裸片附接材料，其中所述第三半导体裸片经由所述裸片附接材料耦合到所述第二半导体裸片，且其中所述第三半导体裸片大体上位于所述第二半导体裸片的整个所述上表面上方。
15.根据权利要求13所述的半导体装置，其进一步包括：
第四半导体裸片，其耦合到所述第三半导体裸片的所述上表面且具有面向所述封装衬底的下表面，其中所述第四半导体裸片横向延伸超过所述第三半导体裸片的至少一个侧以界定所述第四半导体裸片的外伸部分，且其中所述第四半导体裸片的所述下表面包含所述第四半导体裸片的所述外伸部分处的第四接合垫；及
第二导电构件，其将所述第四半导体裸片的所述第四接合垫电耦合到所述封装衬底。
16.根据权利要求15所述的半导体装置，其中所述第四半导体裸片具有与所述下表面相对的上表面，且所述半导体装置进一步包括所述封装衬底上方的模制材料，其中所述模制材料不远离所述封装衬底延伸超过与所述第四半导体裸片的所述上表面共面的平面。
17.根据权利要求1所述的半导体装置，其中所述封装衬底是中介层、印刷电路板、介电间隔物或另一半导体裸片中的至少一者。
18.一种半导体装置，其包括：
再分布结构，其具有第一表面及与所述第一表面相对的第二表面，其中所述第一表面包含第一导电接点及第二导电接点，其中所述第二表面包含第三导电接点，且其中所述第一导电接点及所述第二导电接点通过延伸穿过绝缘材料及/或在其上延伸的导线来电耦合到所述第三导电接点中的对应者；
第一半导体裸片，其耦合到所述再分布结构且具有第一接合垫；
导线接合，其将所述第一接合垫电耦合到所述再分布结构的所述第一导电接点；
第二半导体裸片，其堆叠在所述第一半导体裸片上方且从所述第一半导体裸片横向偏移，其中所述第二半导体裸片包含具有所述第一半导体裸片上方的第一部分及所述再分布结构的所述第二导电接点上方的第二部分的表面，且其中所述第二部分包含第二接合垫；及
导电支柱，其将所述第二导电接点耦合到所述第二接合垫。
19.根据权利要求18所述的半导体装置，其中所述第一半导体裸片及所述第二半导体裸片具有相同平面形状。
20.根据权利要求19所述的半导体装置，其中所述第一半导体裸片及所述第二半导体裸片是相同的，且其中所述第一半导体裸片上的所述第一接合的布置与所述第二半导体裸片上的所述第二接合垫的布置相同。
21.根据权利要求18所述的半导体装置，其中所述第一半导体裸片包含一对相对侧，且其中所述第二半导体仅沿延伸在所述对相对侧之间且平行于所述对相对侧的轴线从所述第一半导体裸片横向偏移。
22.根据权利要求21所述的半导体装置，其中所述再分布结构的所述第一导电接点与所述对相对侧中的一者横向向外间隔，且其中所述再分布结构的所述第二导电接点与所述对相对侧中的另一者横向向外间隔。
23.根据权利要求19所述的半导体装置，其进一步包括：
第一裸片附接材料，其将所述第一半导体裸片耦合到所述再分布结构；及
第二裸片附接材料，其将所述第二半导体裸片耦合到所述第一半导体裸片，其中所述第二裸片附接材料相同于所述第一裸片附接材料。
24.根据权利要求17所述的半导体装置，其中所述再分布结构不包含预成形衬底，且其中所述第一表面与所述第二表面之间的所述再分布结构的厚度小于约50μm。
25.一种制造半导体装置的方法，所述方法包括：
形成位于封装衬底的第一表面上且电耦合到所述封装衬底的导电支柱；
将第一半导体裸片耦合到所述封装衬底；
经由导线接合将所述第一半导体裸片的第一接合垫电耦合到所述封装衬底；
将第二半导体裸片耦合到所述第一半导体裸片及所述导电支柱，其中所述导电支柱将所述第二半导体裸片的第二接合垫电耦合到所述封装衬底；及
形成位于所述封装衬底的所述第一表面上方且至少部分围绕所述第一半导体裸片、所述导电支柱、所述导线接合及所述第二半导体裸片的模制材料。
26.根据权利要求25所述的方法，其中所述模制材料不相对于所述封装衬底延伸超过所述第二半导体裸片。
27.根据权利要求25所述的方法，其中所述封装衬底是再分布结构，且所述方法进一步包括：
在载体上形成所述再分布结构；
在形成所述模制材料之后，移除所述载体以暴露所述再分布结构的第二表面；及
在所述第二表面上形成多个导电元件，所述导电元件经由所述再分布结构电耦合到所述导电支柱及/或所述导线接合中的一或多者。
28.根据权利要求23所述的方法，其中将所述第二半导体裸片耦合到所述导电支柱包含将所述第二半导体裸片的所述第二接合垫热压接合到所述导电支柱。
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