JP5078725B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5078725B2 JP5078725B2 JP2008111087A JP2008111087A JP5078725B2 JP 5078725 B2 JP5078725 B2 JP 5078725B2 JP 2008111087 A JP2008111087 A JP 2008111087A JP 2008111087 A JP2008111087 A JP 2008111087A JP 5078725 B2 JP5078725 B2 JP 5078725B2
- Authority
- JP
- Japan
- Prior art keywords
- marking
- area
- semiconductor substrate
- back surface
- image sensor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 61
- 239000000758 substrate Substances 0.000 claims description 62
- 230000001681 protective effect Effects 0.000 claims description 23
- 230000002093 peripheral effect Effects 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 4
- 238000003384 imaging method Methods 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 33
- 239000011521 glass Substances 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 15
- 238000010330 laser marking Methods 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 238000001514 detection method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000006059 cover glass Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02313—Subtractive methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
図2は、本発明の第1実施例であるW−CSP構造を有するイメージセンサ1の断面構造図である。シリコン単結晶からなる半導体基板100は、イメージセンサ1の本体を構成し、その表面にCMOS回路或いはCCD等の受光素子140が形成されている。半導体基板100上には、多数の受光素子が画素数分だけ形成されており、外部に設けられるレンズ等の光学系によって撮像対象から発せられた光が受光素子140の受光面に結像されるようになっている。受光素子140は受光した光の強度に応じた光電変換信号を検知出力信号として出力する。そして、各受光素子の位置と検知出力信号から画像データが生成される。
図8は、本発明の第2実施例であるW−CSP構造を有するイメージセンサ2の断面構造図である。イメージセンサ2は、捺印マーク200が半導体基板100の裏面側ではなく、ガラス基板102に貼着された保護フィルム150上に形成される点において第1実施例に係るイメージセンサ1と異なる。すなわち、イメージセンサ2の保護フィルム150の直下には、捺印マークの形成を避けるべき裏面配線が存在せず、また、保護フィルム150は、イメージセンサが実装基板に実装される前に剥離されるため、使用時において捺印マークが受光の妨げとなることはなく、その全面を捺印エリアとすることができる。尚、通常、保護フィルム150はダイシング前に剥離されるのが一般的であるが、保護フィルムを貼り付けたまま、ウエハ状態或いは個片化されたチップ状態で出荷される場合もあり得る。ユーザにおいては保護フィルム150を剥離する前に保護フィルム150上に形成された捺印マーク200を実装基板への実装する際の位置認識マークや方向認識マークとして使用することができる。
100 半導体基板
102 ガラス基板
105a 貫通電極
105b 裏面配線
108 バンプ半田
110 表面電極
111 絶縁膜
150 保護フィルム
200 捺印マーク
300 捺印エリア
Claims (6)
- 矩形状の半導体基板と、前記半導体基板の表面に形成された複数の表面電極と、前記半導体基板の内部において前記半導体基板の裏面から前記表面電極の各々に達する複数の貫通孔と、前記貫通孔の各々の内壁を覆う導電体と、前記半導体基板の裏面に設けられて前記導電体に接続された裏面配線網と、前記裏面配線網を覆う絶縁膜と、前記絶縁膜上に形成された捺印マークを有する捺印エリアと、を含む半導体装置であって、
前記捺印エリアの外縁が前記捺印マーク形成面に平行な方向において前記裏面配線網から離間し、且つ前記半導体基板の外縁に一致していることを特徴とする半導体装置。 - 前記捺印エリアは、前記半導体基板のコーナに配置されていることを特徴とする請求項1に記載の半導体装置。
- 前記捺印マークはレーザ照射によって形成されることを特徴とする請求項1又は2に記載の半導体装置。
- 前記半導体基板上に形成された透明基板と、
前記光透過性基板の全面に貼着された保護フィルムと、
前記保護フィルム上に形成された捺印マークを有する表面捺印エリアと、
を更に有することを特徴とする請求項1乃至3のいずれか1に記載の半導体装置。 - 前記半導体基板は、その表面に受光素子を有し、
前記表面捺印エリアは、前記保護フィルム上の前記受光素子によって受光されるべき撮像対象からの光が透過する受光エリア以外の領域に配置されることを特徴とする請求項4に記載の半導体装置。 - 前記受光エリアは、前記保護フィルム上の中央部に配置され、
前記表面捺印エリアは、前記保護フィルム上の前記受光エリアを囲む外周領域に配置されることを特徴とする請求項5に記載の半導体装置。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008111087A JP5078725B2 (ja) | 2008-04-22 | 2008-04-22 | 半導体装置 |
CN200910005615.2A CN101567350B (zh) | 2008-04-22 | 2009-01-20 | 半导体器件 |
CN201510217327.9A CN104882437A (zh) | 2008-04-22 | 2009-01-20 | 半导体器件 |
CN201510217313.7A CN104952852B (zh) | 2008-04-22 | 2009-01-20 | 半导体器件的制造方法 |
US12/403,430 US20090289319A1 (en) | 2008-04-22 | 2009-03-13 | Semiconductor device |
US14/140,842 US20140103528A1 (en) | 2008-04-22 | 2013-12-26 | Semiconductor device |
KR1020150092374A KR101547091B1 (ko) | 2008-04-22 | 2015-06-29 | 반도체 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008111087A JP5078725B2 (ja) | 2008-04-22 | 2008-04-22 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009266862A JP2009266862A (ja) | 2009-11-12 |
JP5078725B2 true JP5078725B2 (ja) | 2012-11-21 |
Family
ID=41283442
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008111087A Active JP5078725B2 (ja) | 2008-04-22 | 2008-04-22 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US20090289319A1 (ja) |
JP (1) | JP5078725B2 (ja) |
KR (1) | KR101547091B1 (ja) |
CN (3) | CN104882437A (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102782862B (zh) * | 2010-02-26 | 2015-08-26 | 精材科技股份有限公司 | 芯片封装体及其制造方法 |
US9653500B2 (en) * | 2010-03-22 | 2017-05-16 | Xintec Inc. | Optical cover plate with improved solder mask dam on glass for image sensor package and fabrication method thereof |
JP5703730B2 (ja) * | 2010-12-13 | 2015-04-22 | 富士通株式会社 | 赤外線撮像装置 |
US8872293B2 (en) * | 2011-02-15 | 2014-10-28 | Sony Corporation | Solid-state imaging device and method of manufacturing the same and electronic apparatus |
TWI464857B (zh) * | 2011-05-20 | 2014-12-11 | Xintec Inc | 晶片封裝體、其形成方法、及封裝晶圓 |
US9170222B2 (en) | 2012-05-11 | 2015-10-27 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Detecting thermal interface material (‘TIM’) between a heat sink and an integrated circuit |
US9316603B2 (en) | 2012-05-11 | 2016-04-19 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Detecting thermal interface material (‘TIM’) between a heat sink and an integrated circuit |
US9666730B2 (en) * | 2014-08-18 | 2017-05-30 | Optiz, Inc. | Wire bond sensor package |
JP2016171149A (ja) | 2015-03-11 | 2016-09-23 | 株式会社東芝 | 半導体装置およびその製造方法 |
KR102503892B1 (ko) | 2015-12-31 | 2023-02-28 | 삼성전자주식회사 | 패키지-온-패키지 타입의 반도체 패키지 및 그 제조방법 |
KR102564805B1 (ko) * | 2016-04-25 | 2023-08-10 | 에스케이하이닉스 주식회사 | 외부 및 내부 어드레스 마커들을 가진 이미지 센서 |
CN107634019A (zh) * | 2017-09-27 | 2018-01-26 | 江苏凯尔生物识别科技有限公司 | 一种薄膜冲压装置以及芯片喷码工艺 |
US10574025B2 (en) * | 2018-01-26 | 2020-02-25 | Lightwave Logic Inc. | Hermetic capsule and method for a monolithic photonic integrated circuit |
CN108693189A (zh) * | 2018-04-02 | 2018-10-23 | 中国工程物理研究院激光聚变研究中心 | 大口径熔石英光学元件基准标识的构建方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61284932A (ja) * | 1985-06-11 | 1986-12-15 | Nec Yamagata Ltd | 半導体製造用樹脂封入金型 |
JPH07321146A (ja) * | 1994-05-25 | 1995-12-08 | Fuji Xerox Co Ltd | ワイヤーボンディング用認識マークの配置方法 |
US5734155A (en) * | 1995-06-07 | 1998-03-31 | Lsi Logic Corporation | Photo-sensitive semiconductor integrated circuit substrate and systems containing the same |
US5937270A (en) * | 1996-01-24 | 1999-08-10 | Micron Electronics, Inc. | Method of efficiently laser marking singulated semiconductor devices |
US6849308B1 (en) * | 1999-05-27 | 2005-02-01 | Stuart Speakman | Method of forming a masking pattern on a surface |
JP3827497B2 (ja) * | 1999-11-29 | 2006-09-27 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP2002217377A (ja) * | 2001-01-18 | 2002-08-02 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP4790157B2 (ja) * | 2001-06-07 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP3878868B2 (ja) * | 2002-03-01 | 2007-02-07 | シャープ株式会社 | GaN系レーザ素子 |
JP2004056061A (ja) * | 2002-05-27 | 2004-02-19 | Kyocera Corp | 撮像素子収納用パッケージ |
JP4257844B2 (ja) | 2003-11-04 | 2009-04-22 | パナソニック株式会社 | 半導体装置およびその製造方法 |
TWI233323B (en) * | 2004-04-22 | 2005-05-21 | Phoenix Prec Technology Corp | Circuit board with identifiable information and method for fabricating the same |
TWI247409B (en) * | 2004-05-13 | 2006-01-11 | Via Tech Inc | Flip chip package and process thereof |
JP2006012952A (ja) * | 2004-06-23 | 2006-01-12 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2006073852A (ja) | 2004-09-03 | 2006-03-16 | Dainippon Printing Co Ltd | センサーパッケージおよびその製造方法 |
JP4471213B2 (ja) * | 2004-12-28 | 2010-06-02 | Okiセミコンダクタ株式会社 | 半導体装置およびその製造方法 |
JP2006190879A (ja) * | 2005-01-07 | 2006-07-20 | Matsushita Electric Ind Co Ltd | 固体撮像装置 |
JP2007180200A (ja) * | 2005-12-27 | 2007-07-12 | Yamaha Corp | 識別マークの読取方法及び識別マークの読取装置 |
JP2007184680A (ja) * | 2006-01-04 | 2007-07-19 | Fujifilm Corp | 固体撮像装置及びその製造方法 |
JP2007208081A (ja) * | 2006-02-02 | 2007-08-16 | Oki Electric Ind Co Ltd | アラインメントマーク、合わせマーク及び半導体装置の製造方法 |
TW200733336A (en) * | 2006-02-17 | 2007-09-01 | Advanced Semiconductor Eng | Ball grid array package structure with identification marks and substrate thereof |
TW200739851A (en) * | 2006-04-12 | 2007-10-16 | Advanced Semiconductor Eng | Chip package structure and process thereof |
JP2007305960A (ja) * | 2006-04-14 | 2007-11-22 | Sharp Corp | 半導体装置およびその製造方法 |
US7884472B2 (en) * | 2008-03-20 | 2011-02-08 | Powertech Technology Inc. | Semiconductor package having substrate ID code and its fabricating method |
-
2008
- 2008-04-22 JP JP2008111087A patent/JP5078725B2/ja active Active
-
2009
- 2009-01-20 CN CN201510217327.9A patent/CN104882437A/zh active Pending
- 2009-01-20 CN CN201510217313.7A patent/CN104952852B/zh active Active
- 2009-01-20 CN CN200910005615.2A patent/CN101567350B/zh active Active
- 2009-03-13 US US12/403,430 patent/US20090289319A1/en not_active Abandoned
-
2013
- 2013-12-26 US US14/140,842 patent/US20140103528A1/en not_active Abandoned
-
2015
- 2015-06-29 KR KR1020150092374A patent/KR101547091B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
CN104882437A (zh) | 2015-09-02 |
CN104952852B (zh) | 2018-06-12 |
CN101567350A (zh) | 2009-10-28 |
JP2009266862A (ja) | 2009-11-12 |
CN101567350B (zh) | 2016-06-15 |
US20090289319A1 (en) | 2009-11-26 |
US20140103528A1 (en) | 2014-04-17 |
KR20150082164A (ko) | 2015-07-15 |
CN104952852A (zh) | 2015-09-30 |
KR101547091B1 (ko) | 2015-08-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5078725B2 (ja) | 半導体装置 | |
US8513756B2 (en) | Semiconductor package and manufacturing method for a semiconductor package as well as optical module | |
KR101453158B1 (ko) | 이미지 센서를 위한 계단형 패키지 및 그 제조 방법 | |
KR100616670B1 (ko) | 웨이퍼 레벨의 이미지 센서 모듈 및 그 제조방법 | |
US7893514B2 (en) | Image sensor package, method of manufacturing the same, and image sensor module including the image sensor package | |
JP4660259B2 (ja) | 半導体装置の製造方法 | |
TWI437699B (zh) | And a solid-state imaging device having a through-electrode | |
JP2010040672A (ja) | 半導体装置およびその製造方法 | |
JP6406404B2 (ja) | イメージセンサモジュール | |
JP2005209967A (ja) | 半導体装置、光学装置用モジュール及び半導体装置の製造方法 | |
US11282879B2 (en) | Image sensor packaging method, image sensor packaging structure, and lens module | |
JP2010186947A (ja) | 固体撮像装置 | |
US8547471B2 (en) | Camera module and method of manufacturing the camera module | |
JP7389029B2 (ja) | 固体撮像装置、電子機器、および固体撮像装置の製造方法 | |
US7888157B2 (en) | Image sensor chip package method | |
JP2006173463A (ja) | センサーモジュール | |
CN111009542B (zh) | 一种封装方法及封装结构 | |
JP5045952B2 (ja) | 光デバイス、光モジュール及び電子機器 | |
JP4292383B2 (ja) | 光デバイスの製造方法 | |
KR100716870B1 (ko) | 반도체패키지 및 그 제조 방법 | |
KR20090111750A (ko) | 반도체 장치 | |
JP2010027886A (ja) | 半導体装置とそれを用いたカメラモジュール |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110329 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120723 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120731 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120828 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150907 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5078725 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |