TWI567804B - 半導體元件及其製造方法 - Google Patents
半導體元件及其製造方法 Download PDFInfo
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- TWI567804B TWI567804B TW103100766A TW103100766A TWI567804B TW I567804 B TWI567804 B TW I567804B TW 103100766 A TW103100766 A TW 103100766A TW 103100766 A TW103100766 A TW 103100766A TW I567804 B TWI567804 B TW I567804B
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- 239000004065 semiconductor Substances 0.000 title claims description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 229910044991 metal oxide Inorganic materials 0.000 claims description 44
- 150000004706 metal oxides Chemical class 0.000 claims description 44
- 239000007943 implant Substances 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 27
- 210000000746 body region Anatomy 0.000 claims description 25
- 239000002019 doping agent Substances 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 20
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 238000002513 implantation Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 229910000420 cerium oxide Inorganic materials 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 description 47
- 230000015556 catabolic process Effects 0.000 description 15
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 10
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Description
本篇發明說明書是有關於一種半導體元件及一種製造它的方法,且特別是有關於一種橫向汲極金屬氧化物半導體(Lateral Drain Metal Oxide Semiconductor,LDMOS)元件及一種製造的方法。
電源管理積體電路(Power Management Integrated Circuits,PMIC)廣泛地用於顯示裝置、可攜式裝置及其他應用裝置。橫向汲極金屬氧化物半導體(LDMOS)元件是用於這些電源管理積體電路的一種高電壓裝置。電源管理積體電路的設計目標包括較低的耗能以及更有效率的功率轉換。為了達到這些目標,希望橫向汲極金屬氧化物半導體元件具有高的崩潰電壓和低的導通電阻(on-resistance)。
根據本發明說明書的一實施例,提出一種電晶體的製造方法。此方法包括形成一溝槽於一基板中,和利用溝槽的邊緣作為一植入遮罩,在垂直於基板之一主面的一方向上,植入一
具有第一導電類型的第一摻雜物至基板內,以形成一埋層於溝槽之一底面下。此方法也包括相對於垂直基板之主面的方向,以不同的植入角度(implant angle),植入一具有第二導電類型的第二摻雜物至基板內,以形成沿著溝槽的複數個側壁與該底面之一漂移植入層(drift implantation layer)。此方法更包括沉積一介電材料於溝槽中。
根據本發明說明書的另一實施例,提出一種橫向汲極金屬氧化物半導體(LDMOS)元件。此橫向汲極金屬氧化物半導體元件包括一井區、一體區域(body region)、一源極區、一汲極區、一閘極結構、一淺溝槽隔離結構以及一埋層,具有第二導電類型的井區位於一基板中,具有第一導電類型的體區域位於井區中,具有第二導電類型的漂移區位於井區中並與體區域隔開,具有第二導電類型的源極區位於體區域中,具有第二導電類型的汲極區位於漂移區中,閘極結構位於井區之上,並介於源極區與汲極區間,淺溝槽隔離(Shallow Trench Isolation)結構位於漂移區中,並介於源極區與汲極區間,具有第一導電類型的埋層位於井區中,並位於漂移區之下,埋層之中心對齊於淺溝槽隔離結構之中心。
10‧‧‧橫向汲極金屬氧化物半導體元件
100‧‧‧基板
102‧‧‧深井區
104‧‧‧體區域
106‧‧‧漂移區
108‧‧‧源極區
110‧‧‧汲極區
112‧‧‧體接觸點
114‧‧‧閘極結構
116‧‧‧閘極電極
118‧‧‧閘極介電層
120、122‧‧‧閘極間隔物
124‧‧‧淺溝槽隔離結構
126‧‧‧埋層
200‧‧‧氮化層
200a、206a‧‧‧開口
202‧‧‧STI溝槽
204‧‧‧襯墊氧化層
206‧‧‧光阻層
208‧‧‧埋層植入處理
210‧‧‧漂移區植入處理
212‧‧‧漂移植入層
214‧‧‧緻密介電層
d1‧‧‧距離
d2‧‧‧距離
第1圖是依照一範例性實施例所形成的一橫向汲極金屬氧化物半導體(LDMOS)元件之局部剖面圖。
第2A~2H圖是繪示依照一實施例的第1圖中之橫向汲極金屬氧化物半導體元件之一範例性的製造方法的局部剖面圖。
現在將對於所提供的實施例進行詳細說明,其範例係繪示於所附圖式中。在可能的情況下,各圖將使用相同的元件符號來指示相同或相似的部分件。
第1圖是依照一範例性實施例所形成(construct)的一橫向汲極金屬氧化物半導體(LDMOS)元件10之局部剖面圖。請參照第1圖,橫向汲極金屬氧化物半導體元件10包括:形成於一基板100中的一N型深井區102;形成於N型深井區102中的一P型區104;形成於N型深井區102中,並與P型體區域104隔開的一N型漂移區106;形成於P型體區域104中的一N+源極區108,及形成於N型漂移區106中的一N+汲極區110;形成於P型體區域104中,且在N+源極區108相對於N型漂移區106之一側接觸N+源極區108的一P+體接觸點(body contact)112;形成於N型深井區102上,並介在N+源極區108與N+汲極區110之間的一閘極結構114,閘極結構114包括一閘極電極116、一閘極介電層118以及閘極間隔物(gate spacer)120與122,閘極間隔物120、122形成於閘極電極116與閘極介電層118側壁的上間隔物;形成於N型漂移區106中,並介於N+汲極區110與N+源極區108間的一淺溝槽隔離(STI)結構124;以及形成於N型深井區102中,並位於N型漂移區106之下的一P型埋層126。一般來
說,P型埋層126與N型漂移區106之中心對齊於淺溝槽隔離結構124之中心。
於橫向汲極金屬氧化物半導體元件10中,P型埋層126之摻雜濃度與N型深井區102之摻雜濃度為相同數量級。並且,N+源極區108與N+汲極區110之摻雜濃度高於P型體區域104與N型漂移區106之摻雜濃度。
P型埋層126的存在使得汲極-源極崩潰電壓(drain-to-source breakdown voltage,BVDSS)增加,且降低橫向汲極金屬氧化物半導體元件10的特定導通電阻(specific on-resistance,RONSP)。汲極-源極崩潰電壓係當關閉(switch off)橫向汲極金屬氧化物半導體元件10時,在橫向汲極金屬氧化物半導體10崩潰前,其所能承受的最大汲極-源極崩潰電壓。特定導通電阻係當開啟(switch on)橫向汲極金屬氧化物半導體元件10時,橫向汲極金屬氧化物半導體元件10的電阻。
特別是,當關閉橫向汲極金屬氧化物半導體元件10時,N+源極區108與P+體接觸點112係電性連接,一順向電壓係施加於N+汲極區110與N+源極區108間,且一零電壓係施加於閘極電極116與源極區108間。如此一來,一體電場(bulk electric field)係形成於N型漂移區106中,使得N型漂移區106實質上被空乏(deplete)。P型埋層126的存在係降低形成於N型漂移區106中的體電場,使得電場均勻分佈。因此,在N型漂移區106崩潰前,其可以完全地空乏。換句話說,P型埋層126的存在,使得橫向
汲極金屬氧化物半導體元件10的汲極-源極崩潰電壓BVDSS增加。
此外,為了使橫向汲極金屬氧化物半導體元件10得到低的特定導通電阻,N型漂移區106摻雜濃度係相對的高。然而,相對高的N型漂移區106摻雜濃度會有降低汲極-源極崩潰電壓BVDSS的效果。此一效果可由P型埋層126來抵銷。如上所述,於第1圖之橫向汲極金屬氧化物半導體元件10中,P型埋層126的存在具有相反的效用,使汲極-源極崩潰電壓BVDSS提升至一物理極限(physical limit),而可以維持低的特定導通電阻。為了達成橫向汲極金屬氧化物半導體元件10的特定應用,係基於汲極-源極崩潰電壓的特殊需求來決定P型埋層126的摻雜濃度。
除了摻雜濃度之外,P型埋層126之一邊緣與淺溝槽隔離結構124之一邊緣之間的一橫向距離d1,以及N型漂移區106之一邊緣與淺溝槽隔離結構124之一邊緣之間的一橫向距離d2,也影響崩潰電壓BVDSS與特定導通電阻RONSP。當製造條件改變時,橫向距離d1與橫向距離d2可能改變,而崩潰電壓BVDSS與特定導通電阻RONSP也可能跟著改變。因此,於第1圖之橫向汲極金屬氧化物半導體元件10中,係令P型埋層126與N型漂移區106對齊於淺溝槽隔離結構124而設置。換句話說,P型埋層126之中心與N型漂移區106之中心係對齊於淺溝槽隔離結構124之中心。如此,可穩定橫向距離d1與橫向距離d2。如以下所更詳細描述者,透過橫向汲極金屬氧化物半導體元件10的製造方法之特殊方式,來達到P型埋層126與N型漂移區106相對於淺溝槽隔離結構124的對準。
第2A~2H圖是繪示依照一實施例之橫向汲極金屬氧化物半導體元件10之一範例性的的製造方法的局部剖面圖。
請參照第2A圖,N型深井區102係形成於基板100之中。N型深井區102的形成可以藉由離子植入製程(ion implantation process)以植入一N型摻雜物至基板100內,而後進行熱處理,以驅使N型摻雜物深入基板100中至一預定深度。一個適合N型深井區102之N型摻雜物的範例係含有磷。N型深井區102中含磷摻雜物的摻雜濃度的一個範例性的範圍約為2×1012/cm2至5×1012/cm2。接著,形成一氮化層(nitride layer)200於基板100上,以覆蓋N型深井區102。氮化層200可包括氮化矽(SixNy),並可以由化學氣相沉積(Chemical Vapor Deposition,CVD)處理來形成。
請參照第2B圖,一開口200a係形成於氮化層200中,以使N型深井區102之一表面暴露在外。開口200a係先透過一微影處理,而後進行蝕刻處理來形成。開口200a的一個範例性的寬度範圍係為0.5μm到2.6μm。若開口200a的寬度增加,則橫向汲極金屬氧化物半導體元件10的汲極-源極崩潰電壓BVDSS與特定導通電阻RONSP也跟著增加;反之亦然。因此,為了達成橫向汲極金屬氧化物半導體元件10的特定應用,係基於汲極-源極崩潰電壓BVDSS與特定導通電阻RONSP的特殊需求來決定開口200a的寬度。隨後,利用氮化層200作為蝕刻遮罩,蝕刻N型深井區102的暴露表面,以形成一STI溝槽202於N型深井區102中。STI溝槽202的深度是可以改變的,且此一深度可由橫向汲極金屬氧化物半導體元件10的
特定應用來決定。舉例來說,STI溝槽202的深度可以被設定在約350nm到400nm的範圍間。
請參照第2C圖,一襯墊氧化層(liner oxide)204係形成於STI溝槽202的暴露表面上。舉例來說,可以熱氧化處理(thermal oxidation process)來形成矽氧化物,提供作為襯墊氧化層204。襯墊氧化層204的厚度可例如是數百埃(Å)。
請參照第2D圖,一光阻層(photoresist layer)206係形成於氮化層200之上,光阻層206具有一開口206a。開口206a係垂直對齊於氮化層200的開口200a,使得伴隨著襯墊氧化層204形成的STI溝槽202暴露在外。光阻層206的開口206a係藉由進行一微影處理來形成。其後,利用氮化層200、光阻層206與STI溝槽202的邊緣作為植入遮罩,進行一埋層植入處理(buried implantation process)208,以植入一P型摻雜物至N型深井區102內。控制埋層植入處理208,使得P型摻雜物係在垂直於基板100之主面的一方向上(以下稱為「垂直方向」)植入,且平均植入深度係低於STI溝槽202的底面。如此進行埋層植入處理208的結果,使P型摻雜物係在STI溝槽202之下局部性地摻雜,形成P型埋層126。P型埋層126與STI溝槽202之底面隔開一距離,例如是1μm。以這樣的方法,P型埋層126係對齊於STI溝槽202。埋層植入處理208中所使用之適合的P型摻雜物的一個範例為硼。P型埋層126之摻雜濃度與N型深井區102之摻雜濃度為相同數量級,如此一來,當關閉橫向汲極金屬氧化物半導體元件10
時,在使N型漂移區106崩潰前,N型漂移區106便可以完全地空乏。在一些實施例中,埋層植入處理208可包括一個或多個植入處理。埋層植入處理208的處理參數,舉例來說,例如是摻雜劑量(dopant dosage)和植入能量(implant energy),可依照橫向汲極金屬氧化物半導體元件10的特定應用而改變。舉例來說,埋層植入處理208的植入能量可以為800KeV至1200KeV,且植入角度可以為0°。
請參照第2E圖,利用氮化層200與光阻層206作為植入遮罩,進行一漂移區植入處理(drift implantation process)210,以植入一N型摻雜物至N型深井區102內。控制漂移區植入處理210,使得N型摻雜物係以相對於垂直方向的不同角度植入。如此進行漂移區植入處理210的結果,使N型摻雜物係沿著STI溝槽202的側壁與底面摻雜至N型深井區102內,以形成一N型漂移植入層212。因為漂移區植入處理210也使用了氮化層200與光阻層206作為植入遮罩,N型漂移植入層212也對齊於STI溝槽202。實施例中,漂移區植入處理210中使用之適合的N型摻雜物的一個範例係含有磷。N型漂移植入層212的摻雜濃度與橫向汲極金屬氧化物半導體元件10的崩潰電壓BVDSS及特定導通電阻RONSP有關,例如摻雜濃度越高,特定導通電阻RONSP就越低,崩潰電壓BVDSS也越低。N型漂移植入層212的摻雜濃度的一個範例性的範圍係約2×1012/cm2至4.5×1012/cm2。漂移區植入處理210的處理參數,舉例來說,例如是摻雜劑量、植
入能量和植入角度,可依照橫向汲極金屬氧化物半導體元件10的特定應用而改變。漂移區植入處理210的植入角度的一個範例性的範圍係約7°至30°。漂移區植入處理210的摻雜劑量的一個範例性的範圍係約1×1012/cm2至3×1012/cm2。
請參照第2F圖,移除光阻層206。而後,形成一介電層214覆蓋於第2E圖之結構上方,以填滿STI溝槽202。可以例如由化學氣相沉積處理形成的矽氧化物,提供作為介電層214。
請參照第2G圖,進行一熱退火處理,使介電層214更密實。舉例來說,熱退火處理可在溫度1150℃進行並維持150分鐘。在退火處理的過程中,N型漂移植入層212中的N型摻雜物由STI溝槽202處橫向地擴散,並且垂直地往N型深井區102的底部擴散,從而形成N型漂移區106。P型埋層126中的P型摻雜物也橫向並垂直擴散。接著進行平坦化處理(planarization process),以除去氮化層200與不想要的介電層214部分,使N型深井區102的一表面暴露在外。此一平坦化處理可以化學機械式研磨(Chemical Mechanical Polishing,CMP)處理來進行。如此一來,即形成包含STI溝槽202與緻密的介電層214的淺溝槽隔離結構124。由於埋層植入處理208使得P型埋層126與STI溝槽202對齊,且漂移區植入處理210使得N型漂移植入層212與STI溝槽202對齊,因此後續的處理步驟使得P型埋層126與N型漂移區106與淺溝槽隔離結構124對齊。
請參照第2H圖,接下來以本領域所屬技術領域之通常知識
者所熟知的方法繼續進行處理,以完成橫向汲極金屬氧化物半導體元件10的結構。如第2H圖所示,進行一P型植入處理(P-type implantation process)和一擴散處理,以形成與N型漂移區106分開的P型體區域104於N型深井區102中。P型植入處理中使用之適合的P型摻雜物的一個範例為硼,P型體區域104的深度的一個範例性的範圍係為1μm至2μm。P型體區域104的摻雜濃度係基於橫向汲極金屬氧化物半導體元件10的特定應用來決定。舉例來說,P型體區域104的摻雜濃度可為5×1012/cm2到1.2×1013/cm2。
閘極電極116與閘極氧化層118係形成於N型深井區102上,並與P型體區域104的一部分及N型漂移區106的一部分重疊。閘極電極116可包括例如多晶矽。閘極氧化層118可包括例如矽氧化物。接著,形成閘極間隔物120與122於閘極電極116與閘極氧化層118的側壁上。
在另一實施例中,閘極電極116與閘極氧化層118係在P型體區域104形成前形成。而後利用閘極電極116與閘極氧化層118,以一P型植入處理來形成P型體區域104。
接著,進行一N型離子植入製程(N-type ion implantation process),以形成N+源極區108於P型體區域104中,以及形成N+汲極區110於N型漂移區106中。N型離子植入製程中適合之N型摻雜物的一個範例係含有磷。N+源極區108與N+汲極區110的摻雜濃度的一個範例係約3×1015/cm2,以形成歐姆接觸點(ohmic contact)。進行一P型離子植入製程(P-type ion
implantation process),以形成P+體接觸點112於P型體區域104中。P型離子植入製程中適合之P型摻雜物的一個範例為硼。P+體接觸點112的摻雜濃度可例如約3×1015/cm2。
在前述的製造方法中,埋層植入處理208與漂移區植入處理210兩者皆使用相同的氮化層200與光阻層206作為植入遮罩。因此,N型漂移區106、淺溝槽隔離結構124與P型埋層126之中心係大致上對準。如此一來,既能降低不同元件之間崩潰電壓與導通電阻之差異,還能實現製程的穩定性。
除此之外,埋層植入處理208與漂移區植入處理210的進行不需要額外的微影處理。因此,製造橫向汲極金屬氧化物半導體元件10的製程可與製造互補式金屬氧化物半導體(Complementary Metal Oxide Semiconductor,CMOS)元件的標準製程整合在一起。
雖然上述的實施例是針對N型橫向汲極金屬氧化物半導體(NLDMOS)元件及製造方法,本發明所屬技術領域中具有通常知識者係能夠理解,所揭露的概念同樣能應用到P型橫向汲極金屬氧化物半導體(PLDMOS)元件上。本發明所屬技術領域中具有通常知識者也能夠理解,上述之方法可用來製造其他替代元件,例如延伸汲極金屬氧化物半導體(Extended Drain Metal Oxide Semiconductor,EDMOS),以及由雙極性接電電晶體(Bipolar Junction Transistors)、互補式金屬氧化物半導體與橫向汲極金屬氧化物半導體所組成的Bipolar/CMOS/LDMOS(BCD)積體電路。除此之外,上述
之方法也可用來製造具有其他結構的元件,這些其他結構例如是深溝槽隔離(Deep Trench Isolation,DTI)結構、絕緣體覆矽(Silicon On Insulator,SOI)結構與磊晶成長半導體層(epitaxially grown semiconductor layer)。
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧橫向汲極金屬氧化物半導體元件
100‧‧‧基板
102‧‧‧深井區
104‧‧‧體區域
106‧‧‧漂移區
108‧‧‧源極區
110‧‧‧汲極區
112‧‧‧體接觸點
114‧‧‧閘極結構
116‧‧‧閘極電極
118‧‧‧閘極介電層
120、122‧‧‧閘極間隔物
124‧‧‧淺溝槽隔離結構
126‧‧‧埋層
Claims (17)
- 一種電晶體之製造方法,包括:形成一溝槽於一基板中;利用該溝槽的邊緣作為一植入遮罩,在垂直於該基板之一主面的一方向上,植入一第一摻雜物至該基板內,以形成一埋層於該溝槽之一底面下,該埋層的植入深度低於該溝槽之該底面,該第一摻雜物具有一第一導電類型;相對於垂直該基板之該主面的該方向,以不同植入角度植入一第二摻雜物至該基板內,以形成沿著該溝槽的複數個側壁與該底面之一漂移植入層,該第二摻雜物具有一第二導電類型;以及沉積一介電材料於該溝槽中。
- 如申請專利範圍第1項所述之製造方法,更包括:在形成該溝槽於該基板中的步驟前,形成一第一遮罩於該基板上方,該第一遮罩具有一第一開口,使該基板之一表面暴露在外;蝕刻該基板暴露之該表面,以形成該溝槽於該基板中;形成一第二遮罩於該第一遮罩上方,該第二遮罩具有一第二開口,使該溝槽暴露在外;以及在沉積該介電材料於該溝槽中的步驟後,移除該第一遮罩與該第二遮罩。
- 如申請專利範圍第2項所述之製造方法,其中該第一遮罩包括沉積於該基板上方的一氮化物材料。
- 如申請專利範圍第2項所述之製造方法,其中該第二遮罩包括一光阻。
- 如申請專利範圍第1項所述之製造方法,其中該介電材料包括矽氧化物。
- 如申請專利範圍第1項所述之製造方法,其中該第一導電類型為P型,該第二導電類型為N型。
- 如申請專利範圍第1項所述之製造方法,其中該第一導電類型為N型,該第二導電類型為P型。
- 如申請專利範圍第1項所述之製造方法,更包括:進行一熱退火處理,以使得位於該溝槽中之該介電材料更密實,和擴散沿著該溝槽的該些側壁與該底面植入之該第二摻雜物以形成一漂移區。
- 如申請專利範圍第1項所述之製造方法,更包括:形成一井區於該基板中;以及 形成該溝槽與該埋層於該井區中。
- 如申請專利範圍第1項所述之製造方法,更包括:在沉積該介電材料於該溝槽中的步驟後,形成一閘極電極和一閘極介電層於一通道區上方,該通道區位於該井區中;形成一體區域於該井區中,該體區域具有該第一導電類型;形成一源極區於該體區域中並形成一汲極區於該漂移區中,該源極區具有該第二導電類型,該汲極區具有該第二導電類型;以及形成一體接觸點於該體區域中,該體接觸點具有該第一導電類型。
- 一種橫向汲極金屬氧化物半導體(lateral drain metal oxide semiconductor)元件,包括:一井區,位於一基板中,該井區具有一第二導電類型;一體區域,位於該井區中,該體區域具有一第一導電類型;一漂移區,位於該井區中並與該體區域隔開,該漂移區具有該第二導電類型;一源極區,位於該體區域中,該源極區具有該第二導電類型;一汲極區,位於該漂移區中,該汲極區具有該第二導電類型;一閘極結構,位於該井區上,並介於該源極區與該汲極區間;一淺溝槽隔離結構,位於該漂移區中,並介於該汲極區與該 源極區間;以及一埋層,位於該井區中,並位於該漂移區之下,該埋層具有該第一導電類型,該埋層之中心對齊於該淺溝槽隔離結構之中心。
- 如申請專利範圍第11項所述之橫向汲極金屬氧化物半導體元件,其中該埋層之一摻雜濃度與該井區之一摻雜濃度為相同數量級。
- 如申請專利範圍第11項所述之橫向汲極金屬氧化物半導體元件,其中該源極區與該汲極區之摻雜濃度高於該體區域與該漂移區之摻雜濃度。
- 如申請專利範圍第11項所述之橫向汲極金屬氧化物半導體元件,其中該埋層與該淺溝槽隔離結構之一底面隔開。
- 如申請專利範圍第11項所述之橫向汲極金屬氧化物半導體元件,其中該第一導電類型為P型,而該第二導電類型為N型。
- 如申請專利範圍第11項所述之橫向汲極金屬氧化物半導體元件,其中該第一導電類型為N型,而該第二導電類型為P 型。
- 如申請專利範圍第11項所述之橫向汲極金屬氧化物半導體元件,更包括一體接觸點,該體接觸點位於該體區域中,且在該源極區相對於該漂移區的之一側接觸該源極區,該體接觸點具有該第一導電類型。
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