TWI566354B - 中介板及其製法 - Google Patents

中介板及其製法 Download PDF

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TWI566354B
TWI566354B TW103127721A TW103127721A TWI566354B TW I566354 B TWI566354 B TW I566354B TW 103127721 A TW103127721 A TW 103127721A TW 103127721 A TW103127721 A TW 103127721A TW I566354 B TWI566354 B TW I566354B
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conductive
interposer
electrical contact
layer
contact pad
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TW103127721A
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TW201606968A (zh
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張文璟
林健民
吳柏毅
盧俊宏
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矽品精密工業股份有限公司
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Priority to TW103127721A priority Critical patent/TWI566354B/zh
Priority to CN201410460338.5A priority patent/CN105374798A/zh
Priority to US14/739,026 priority patent/US20160050753A1/en
Publication of TW201606968A publication Critical patent/TW201606968A/zh
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Description

中介板及其製法
本發明係有關一種中介板，尤指一種用於半導體封裝件之中介板及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)或多晶片模組封裝(Multi-Chip Module,MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知3D晶片堆疊之半導體封裝件之製法之剖面示意圖。如第1圖所示，提供一矽中介板(Through Silicon interposer,TSI)1，該矽中介板1具有具有相對之置晶側10b與轉接側10a、及連通該置晶側10b與轉接側10a之複數導電矽穿孔(Through-silicon via,TSV)100，且該置晶側10b上具有一線路重佈結構(Redistribution layer,RDL)11。將間距較小之半導體晶片6之電極墊60係藉由複數銲錫凸塊61電性結合至該線路重佈結構11上，再以底膠62包覆該些銲錫凸塊61，且於該導電矽穿孔100上 藉由複數如凸塊之導電元件18電性結合間距較大之封裝基板7之銲墊70，之後形成封裝膠體8於該封裝基板7上，以包覆該半導體晶片6。
第1A至1G圖係為習知矽中介板1之轉接側10a之製法之剖面示意圖。
如第1A圖所示，提供一具有相對之轉接側10a與置晶側10b之矽板體10，且該矽板體10具有連通該轉接側10a與置晶側10b之複數導電矽穿孔100，又該矽板體10之置晶側10b上具有一電性連接該導電矽穿孔100之線路重佈結構11，該轉接側10a係具有一鈍化層12。
如第1B圖所示，形成一導電層14(俗稱晶種層)於該鈍化層12與各該導電矽穿孔100上。
如第1C圖所示，利用阻層(圖略)圖案化電鍍形成電性接觸墊16上於各該導電矽穿孔100上，之後移除該阻層。目前一般矽中介板1之線寬/線高可為3μm以下(如第1C’圖所示之電性接觸墊16之厚度d)，而晶種層之厚度一般約在1μm以下(如第1C’圖所示之導電層14之厚度t)。
如第1D圖所示，濕蝕刻移除該阻層下之導電層14，且該電性接觸墊16電性連接該導電矽穿孔100。
如第1E圖所示，形成一絕緣保護層13於該鈍化層12與各該電性接觸墊16上，且該絕緣保護層13具有複數開孔130，以令各該電性接觸墊16對應外露於各該開孔130。
如第1F圖所示，形成另一導電層14’於該絕緣保護 層13與該電性接觸墊16上，再利用另一阻層17圖案化電鍍形成如銲錫材料之導電元件18於各該電性接觸墊16上。
如第1G圖所示，移除該阻層17及其下之導電層14’。
惟，前述習知矽中介板1之製法中，於第1C圖之製程之阻層下之導電層14尚未去除，故當移除該阻層下之導電層14時，濕蝕刻會等向性蝕刻，即使蝕刻濕蝕刻所使用的藥液會有選擇性蝕刻，但該電性接觸墊16下的導電層14亦會受蝕，而產生底切現象(如第1C’圖所示之導電層14之底切寬度r)，造成該電性接觸墊16之底部過細而無法立設於該導電矽穿孔100上。
再者，於進行濕蝕刻製程時，該電性接觸墊16亦會部分受蝕，致使該電性接觸墊16無法達到原先之預設寬度L(如第1C’圖所示)，因而會產生電性問題。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種中介板，係包括：板體，係具有相對之第一側與第二側、及連通該第一側與第二側之複數導電穿孔；絕緣保護層，係形成於該板體之第一側上，且該絕緣保護層具有複數開孔，以令各該導電穿孔對應外露於各該開孔；複數電性接觸墊，各設於各該開孔中，且電性連接該導電穿孔；以及導電層，係設於該開孔與該電性接觸墊之間。
本發明亦提供一種中介板之製法，係包括：提供一具 有相對之第一側與第二側之板體，且該板體具有連通該第一側與第二側之複數導電穿孔；形成絕緣保護層於該板體之第一側上，且該絕緣保護層具有複數開孔，以令各該導電穿孔對應外露於各該開孔；以及形成電性接觸墊於各該開孔中，且該電性接觸墊電性連接該導電穿孔。
前述之製法中，該電性接觸墊係以電鍍方式形成者。
前述之中介板及其製法中，該板體係為半導體板體。
前述之中介板及其製法中，該板體之第一側係具有鈍化層。
前述之中介板及其製法中，該板體之第二側上具有線路結構，且該導電穿孔電性連接該線路結構。
前述之中介板及其製法中，該電性接觸墊之表面齊平該絕緣保護層之表面。
前述之中介板及其製法中，該電性接觸墊之製程係包括：形成導電層於該絕緣保護層上與各該開孔中；形成導電材於該絕緣保護層上之導電層上與各該開孔中；移除該絕緣保護層上之導電層及其上之導電材，且保留各該開孔中之導電材以作為該電性接觸墊。因此，該導電層係設於該導電穿孔與該電性接觸墊之間、及該開孔與該電性接觸墊之間。
前述之中介板及其製法中，復包括形成導電元件於各該電性接觸墊上。
由上可知，本發明之中介板及其製法，藉由先形成該絕緣保護層於該板體之第一側上，以形成電性接觸墊於各 該開孔中，故相較於習知技術，本發明於製作該電性接觸墊時，無需移除圖案化用之阻層及無需進行濕蝕刻製程，因而可減少材料等使用成本，並能簡化製程，以提高產量。
再者，因無需進行濕蝕刻製程，故該電性接觸墊與該導電層不會產生底切現象，因而可避免習知技術所產生的問題。
1‧‧‧矽中介板
10,20‧‧‧板體
10a‧‧‧轉接側
10b‧‧‧置晶側
100‧‧‧導電矽穿孔
11‧‧‧線路重佈結構
12,22‧‧‧鈍化層
13,23‧‧‧絕緣保護層
130,230‧‧‧開孔
14,14’,24,24’‧‧‧導電層
16,26‧‧‧電性接觸墊
17,27‧‧‧阻層
18,28‧‧‧導電元件
2‧‧‧中介板
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧導電穿孔
21‧‧‧線路結構
210‧‧‧介電層
211‧‧‧線路層
23a,23b‧‧‧表面
25‧‧‧導電材
6‧‧‧半導體晶片
60‧‧‧電極墊
61‧‧‧銲錫凸塊
62‧‧‧底膠
7‧‧‧封裝基板
70‧‧‧銲墊
8‧‧‧封裝膠體
d,t‧‧‧厚度
L‧‧‧預設寬度
r‧‧‧底切寬度
第1圖係為習知矽中介板之剖面示意圖；第1A至1G圖係為習知矽中介板之製法的剖面示意圖；其中，第1C’圖係第1C圖之局部放大圖；以及第2A至2G圖係為本發明之中介板之製法的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅 為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之中介板2之製法之第一實施例的剖面示意圖。
如第2A圖所示，提供一具有相對之第一側20a(可視為轉接側)與第二側20b(可視為置晶側)之板體20，且該板體20係為半導體板體，其具有連通該第一側20a與第二側20b之複數導電穿孔200。
於本實施例中，該板體20係為含矽板體，例如，矽晶圓或玻璃基板，且藉由線路重佈層(Redistribution layer,RDL)製程，於該板體20之第二側20b上已製作出一電性連接該導電穿孔200之線路結構21，其中，該線路結構21具有至少一介電層210與設於該介電層210上並電性連接該導電穿孔200之線路層211。
再者，該板體20之第一側20a係具有一鈍化層22，且該鈍化層22係為氧化層(如二氧化矽)或氮化層(如氮化矽)。
如第2B圖所示，形成一絕緣保護層23於該板體20之第一側20a之鈍化層22上，且該絕緣保護層23具有複數開孔230，以令各該導電穿孔200對應外露於各該開孔230。
於本實施例中，該絕緣保護層23係為氧化層(如二氧化矽)或氮化層(如氮化矽層)。
如第2C圖所示，形成一導電層24於該絕緣保護層23上與各該開孔230中。接著，形成如銅之導電材25於該絕緣保護層23上之導電層24上與各該開孔230中。
於本實施例中，進行線路重佈層(Redistribution layer,RDL)製程，利用該導電層24進行電鍍步驟，以形成該導電材25。
如第2D圖所示，進行化學機械研磨(Chemical-Mechanical Polishing，簡稱CMP)製程，移除該絕緣保護層23上之導電層24及其上之導電材25，且保留各該開孔230中之導電材25，以形成複數電性接觸墊26於各該開孔230中，且該電性接觸墊26電性連接該導電穿孔200。
於本實施例中，該電性接觸墊26之表面26a齊平該絕緣保護層23之表面23a。
如第2E圖所示，形成另一導電層24’於該絕緣保護層23與該電性接觸墊26上，再利用阻層27圖案化電鍍形成如銲錫材料之導電元件28於各該電性接觸墊26上。
如第2F圖所示，移除該阻層27及其下之導電層24’。
如第2G圖所示，回銲各該導電元件28。
本發明之製法中，利用先形成該絕緣保護層23於該板體20之第一側20a上，以於該板體20之第一側20a上全面電鍍該導電材25，再移除多餘的導電材25及其下之導電層24，故相較於習知技術，本發明於製作該電性接觸墊26時，無需移除圖案化用之阻層及無需進行濕蝕刻製程， 因而可減少材料等使用成本，並能簡化製程，以提高產量。
再者，因無需進行濕蝕刻製程，故該電性接觸墊26與該導電層24不會有底切現象，因而無習知技術所產生的問題。
本發明係提供一種中介板2，係包括：一板體20、一絕緣保護層23、複數電性接觸墊26以及一導電層24。
所述之板體20係具有相對之第一側20a與第二側20b、及連通該第一側20a與第二側20b之複數導電穿孔200，且該板體20之第二側20b上具有線路結構21，又該導電穿孔200係電性連接該線路結構21。
所述之絕緣保護層23係形成於該板體20之第一側20a上，且該絕緣保護層23具有複數開孔230，以令各該導電穿孔200對應外露於各該開孔230。
所述之電性接觸墊26係設於各該開孔230中，且電性連接該導電穿孔200。
所述之導電層24係設於該開孔230與該電性接觸墊26之間、及該導電穿孔200與該電性接觸墊26之間。
於一實施例中，該板體20係為半導體板體。
於一實施例中，該板體20之第一側20a係具有一鈍化層22。
於一實施例中，該電性接觸墊26之表面26a齊平該絕緣保護層23之表面23a。
於一實施例中，所述之中介板2復包括複數導電元件28，係設於該電性接觸墊26上。
綜上所述，本發明之中介板及其製法，係藉由先形成該絕緣保護層，再製作該電性接觸墊，故無需進行濕蝕刻製程，因而可減少材料等使用成本，並能簡化製程以提高產量，且不會有底切現象，以提高製作良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
20‧‧‧板體
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧導電穿孔
21‧‧‧線路結構
22‧‧‧鈍化層
23‧‧‧絕緣保護層
23a‧‧‧表面
230‧‧‧開孔
24‧‧‧導電層
26‧‧‧電性接觸墊
26a‧‧‧表面

Claims (18)

  1. 一種中介板，係包括：板體，係具有相對之第一側與第二側、及連通該第一側與第二側之複數導電穿孔；絕緣保護層，係形成於該板體之第一側上，且該絕緣保護層具有複數開孔，以令各該導電穿孔對應外露於各該開孔；複數電性接觸墊，各設於各該開孔中，且電性連接該導電穿孔；以及導電層，係設於該開孔與該電性接觸墊之間。
  2. 如申請專利範圍第1項所述之中介板，其中，該板體係為半導體板體。
  3. 如申請專利範圍第1項所述之中介板，其中，該板體之第一側係具有至少一鈍化層。
  4. 如申請專利範圍第1項所述之中介板，其中，該板體之第二側上具有線路結構。
  5. 如申請專利範圍第4項所述之中介板，其中，該導電穿孔係電性連接該線路結構。
  6. 如申請專利範圍第1項所述之中介板，其中，該電性接觸墊之表面齊平該絕緣保護層之表面。
  7. 如申請專利範圍第1項所述之中介板，其中，該導電層復設於該導電穿孔與該電性接觸墊之間。
  8. 如申請專利範圍第1項所述之中介板，復包括導電元件，係設於該電性接觸墊上。
  9. 一種中介板之製法，係包括：提供一具有相對之第一側與第二側之板體，且該板體具有連通該第一側與第二側之複數導電穿孔；形成絕緣保護層於該板體之第一側上，且該絕緣保護層具有複數開孔，以令各該導電穿孔對應外露於各該開孔；以及形成電性接觸墊於各該開孔中，且令各該電性接觸墊電性連接對應之該導電穿孔，其中，一導電層係設於該開孔與該電性接觸墊之間。
  10. 如申請專利範圍第9項所述之中介板之製法，其中，該板體係為半導體板體。
  11. 如申請專利範圍第9項所述之中介板之製法，其中，該板體之第一側係具有至少一鈍化層。
  12. 如申請專利範圍第9項所述之中介板之製法，其中，該板體之第二側上具有線路結構。
  13. 如申請專利範圍第12項所述之中介板之製法，其中，該導電穿孔係電性連接該線路結構。
  14. 如申請專利範圍第9項所述之中介板之製法，其中，該電性接觸墊之表面齊平該絕緣保護層之表面。
  15. 如申請專利範圍第9項所述之中介板之製法，其中，該電性接觸墊係以電鍍方式形成者。
  16. 如申請專利範圍第9項所述之中介板之製法，其中，該電性接觸墊之製程係包括：形成該導電層於該絕緣保護層上與各該開孔中； 形成導電材於該絕緣保護層上之導電層上與各該開孔中；移除該絕緣保護層上之導電層及其上之導電材，且保留各該開孔中之導電材以作為該電性接觸墊。
  17. 如申請專利範圍第16項所述之中介板之製法，其中，該導電層復設於該導電穿孔與該電性接觸墊之間。
  18. 如申請專利範圍第9項所述之中介板之製法，復包括形成導電元件於各該電性接觸墊上。
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